Index: anr/section-2.tex
===================================================================
--- anr/section-2.tex	(revision 69)
+++ anr/section-2.tex	(revision 97)
@@ -1,101 +1,105 @@
-The emerging complex and integrated heterogeneous embedded system platforms require
-adequate design methods to efficiently model, explore, analyze and design the ever complex software
-and hardware architectures. In order to rapidly meet the increasing performance requirements and a pressure 
-to lower development cost and shorten time-to-market, future embedded systems suppliers
-will have to adopt new design methodologies and flows in order to keep pace with the increasing
-complexity of design problems. Such methods, addressing these challenges starting from high levels of
-abstraction, will have to perform large solution space explorations both for software and (possibly
-reconfigurable) hardware, reducing the design effort and offering a high predictability of results
-with respect to cost and performance objectives.
-\\
-Current design methodologies provide quite low-level abstraction capabilities. However in a few years
-from now, tens of programmable processors will be embedded in an IC with more than 100M
-transistors, therefore adding to the complexity of the problem of designing such systems.
-Taking into account that the complexity of the software part is increasing at an even
-faster rate, current solutions for design space exploration, mainly manually based, by no
-means do supply an adequate efficiency.
-Consequently, there is an urgent need to leverage system level
-exploration through the use of a high-level specification of the application and an early design
-space exploration step. The first system oriented approaches are appearing, among which those
-based on C/C++ and SystemC are the most popular. Such approaches can take place before and/or after
-the co-design or architecture refinement steps and target the design space pruning in order to fully
-exploit potential solutions that meet design and application constraints (power, latency,
-throughput) within the design and market timeframe.
-\\
-Thus, new system-level design flows need to be developed, enabling the exploration of an application
-independently of the implementation, almost at the beginning of the design process.
-A fundamental element of this evolution is the definition of abstraction layers that should allow the
-performance driven re-use of software and hardware components at the system level.
-In this context, COACH will combine modeling and estimation methods and compilers and
-design space exploration techniques. This approach will be a radical innovation in
-embedded system design methodology.
-\\
-The reason is that the COACH framework is applied before high-level design tools in the embedded
-systems design flow. In that way, it will make possible a real and efficiently combined
-exploitation of high-level synthesis tools, parallelizing approaches and compilers, already
-available on the market. These tools and approaches are not yet massively adopted, precisely
-because this preliminary design step is missing. COACH will indeed permit (i) to predict and
-control implementation optimizations, (ii) to target multiple implementation technologies
-(and thus the associated tools) from a unique specification and (iii) to efficiently integrate high
-and low-level design tools in a unique seamless design flow.
-\\
-The performance estimation methods combined with the design space exploration techniques will
-finally allow the design process to start from system level specification and automatically explore the
-potential architectures in order to find out the optimal implementation in a shorter design time and at
-a lower global cost.
+The first objective of COACH is to provide SMEs (Small and Medium Enterprises) an open-source framework to
+design embedded system on FPGA devices. 
+
+Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit) 
+is not an option for most SMEs. Fortunately, the new FPGA (Field Programmable Gate Array) components,
+such as the Virtex5 family from Xilinx, or the Stratix4 family from Altera can implement a complete
+multi-processor architecture on a single chip.
+
+%But the design of a SoC (System on Chip) or MPSoC (Multi-Processor System on Chip) is a complex
+%task, requiring adequate design methods to efficiently model, explore, and analyze the 
+%interactions between the software application and the hardware architectures. Moreover, most SMEs do not have 
+%in-home expertise in the field of hardware design or VHDL/Verilog modeling.
+%In order to meet the increasing performance requirements, to decrease the development cost, and to
+%shorten the time-to-market, they need new design methodologies. 
+
+%Current design methodologies provide quite low-level abstraction capabilities, and 
+%there is an urgent need to leverage system level exploration through the use of a high-level 
+%specification of the application and  design space exploration tools.
+
+%The first system oriented approaches are appearing, among which those
+%based on C/C++ and SystemC are the most popular, but few of them are specifically targetting FPGAs.
+
+The COACH project will leverage on the expertise gained in the field of virtual prototyping
+with the SoCLib platform, to propose a new design flow based on a small number of architectural templates.
+An architectural template is a generic, parametrized architecture, relying on a predefined library 
+of IP cores. 
+Besides using a specific collection of general purpose IP cores (such as processors cores,
+embedded memory controllers, system bus controllers, I/O and peripheral controllers), each architectural
+template can be enriched by dedicated hardware coprocessors, obtained by high level synthesis (HLS) tools.
+During this project, the COACH partners will develop three different architectural templates:
+
+\begin{enumerate}
+\item An \altera architectural template based on the \altera IP core library and the AVALON system bus.
+\item A \xilinx architectural template based on the Xlinx IP core library and the OPB system bus.
+\item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP communication infrastructure.
+\end{enumerate}
+
+The proposed design flow starts from a high level description of the application, specified as a set of 
+parallel tasks written in C, without any assumption on the hardware or software implementation
+of these tasks. It let the system
+designer in charge of expessing the coarse grain parallelism of the application, gives the designer
+the possibility to explore various mapping of the application on the selected template architecture,
+and offers a high predictability of results with respect to cost and performance objectives.
+
+When this interactive, system level, design space exploration is completed (converging to
+a specific mapping on a specific version of the selected architectural template), the rest of the flow 
+is fully automated: The synthesisable VHDL models for the various hardware components, as well as the binary
+code for the software running on the embedded processors, and the bit-stream to program the the target FPGA 
+will be automatically generated by the COACH tools.
+
 \par
-To get an efficient embedded system, the system designer has to take into account
-application characteristics when it chooses one of the available technologies.
-This choice is not easy and in most cases the designer has to try different
-technologies to retain the most adapted one.
-\\
-The first objective of COACH is to provide an open-source framework to
-design embedded system on FPGA devices.
-The COACH framework allows the designer to explore various software/hardware
-partitions of the target application, to run timing and functional
-simulations and to generate automatically both the software and the
-synthesizable description of the hardware.
-The main topics of the project are:
-\begin{itemize} 
-\item
-\textbf{Design space exploration}: It consists in analysing the application running
-on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and
-hardware/software partitioning of tasks depending on technology choice.
-This exploration is driven basically by throughput, latency and power
-consumption criteria.
-\item
-\textbf{Micro-architectural exploration}: When hardware components are required, the
-HLS tools of the framework generate them automatically. At this stage the
-framework provides various HLS tools that allow the micro-architectural space
-design exploration. The exploration criteria also are throughput, latency
-and power consumption.
-At this stage, preliminary source-level transformations will be
-required to improve the efficiency of the target component.
-For instance, one may transform a loop nest to expose parallelism,
-or shrink an array to promote it to a register or reduce a memory footprint.
+The strength of the COACH approach is the strong integration of the high-level synthesis tools 
+in a plat-form based design flow supporting virtual prototyping and design space exploration.
+Most building blocks already exist (resulting from previous projects): the GAUT 
+or UGH synthesis tools, the MutekH or DNA embedded operating systems, the ASIP technology,
+the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelisation tool,
+as well as the SoCLib library of systemC simulation models. They must now be integrated in
+a consistent design flow.
+%The five academic laboratories worked very closely during more than one year (one monthly meeting
+%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
+%those various technologies, and to define the detailed architecture of the proposed design flow.
+\par
 
-\item
-\textbf{Performance measurement}: For each point in the design space,
-figures of merit are available such as throughput, latency, power
-consumption, area, memory allocation and data locality. They are evaluated
-using virtual prototyping, estimation or analyzing methodologies.
-\item
-\textbf{Targeted hardware technology}: The COACH description of a system is
-independent of the FPGA family.  Every point of the design
-space can be implemented on any FPGA having the required resources.
-Basically, COACH handles both Altera and Xilinx FPGA families.
-\end{itemize}
-As an extension of embedded system design, COACH deals also with High
-Performance Computing (HPC).
-In HPC, the kind of targeted application is an existing one running on a PC.
-The COACH framework helps designer to accelerate it by migrating critical parts into a
-SoC implemented on an FPGA plugged to the PC bus.
-\par
-COACH is the result of the will of several laboratories to unify their knowhow
-and skills in the following domains: Operating system and hardware
-communication (\tima, \upmc), SoC and MPSoC (\upmc and \tima), ASIP (\irisa) and
-HLS (\upmc, \ubs) and compilation (\irisa, \lip).
-The project objective is to integrate these various domains into a unique
-free framework (licence ...) masking as much as possible these domains and
-its different tools to the user.
+In summary, the COACH project is clearly oriented toward industry, even if most technology building blocks
+have been previously developed by academic laboratories.
 
+
+%Finally, the key points of the proposed design flow are :
+%\begin{itemize} 
+%\item
+%\textbf{System level exploration}: The application coarse grain parallelism 
+%is explicitely described as a Tasks and Communication Graph (TCG).
+%A template architecture is selected, and the performances are evaluated
+%on various variant of this architecture using the SoCLib virtual protyping
+%environment. This result in a specific hardware/software partitioning.  
+%This system level exploration is fully controlled by the system designer, and is driven 
+%by cost, throughput, latency and power consumption criteria. 
+%
+%\item
+%\textbf{High Level Synthesis}: When dedicated hardware coprocessors have been
+%identified as mandatory, they will be generated by the high level synthesis (HLS) tools. 
+%The Coach framework will integrate various HLS tools, supporting the micro-architectural space
+%design exploration. Here again, the exploration criteria are cost, throughput, latency
+%and power consumption.
+%At this stage, preliminary source-level transformations and optimisations by front-end
+%tools will be required to improve the efficiency of the back-end HLS tools.
+%
+%\item
+%\textbf{Early performance evaluation}: For each point in the design space,
+%figures of merit must be available such as throughput, latency, power
+%consumption, area, memory allocation and data locality. They are evaluated
+%by reliable estimators obtained by running the actual multi-task software 
+%application on the virtual prototype.
+%
+%\item
+%\textbf{Independance from the Target FPGA}: The COACH description of the system 
+%(both hardware and software) should be independent of the FPGA family.  
+%Every point of the design space can be implemented on any FPGA component,
+%as long as it contains the hardware ressources required by the selected architectural template.
+%Basically, COACH will support both Altera and Xilinx FPGA families.
+%\end{itemize}
+%
+
+
+
