Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 96) +++ /anr/anr.tex (revision 97) @@ -111,5 +111,5 @@ % 2.1 -\pagefeed\subsection{Context, economic and societal issues} +\pagefeed\subsection{Economic and societal issues} \anrdoc{(2 pages maximum) Décrire le contexte économique, social, réglementaire dans lequel se situe le projet en présentant une analyse des enjeux sociaux, Index: /anr/section-1.tex =================================================================== --- /anr/section-1.tex (revision 96) +++ /anr/section-1.tex (revision 97) @@ -2,14 +2,14 @@ The market of digital systems is about 4,600 M\$ today and is estimated to 5,600 M\$ in 2012. However the ever growing applications complexity involves -higher integration of heterogeneous technologies and requires the design of +integration of heterogeneous technologies and requires the design of complex Multi-Processors System on Chip (MPSoC). -During the last decade, the design of complex digital ASICs (Application Specific +\par +During the last decade, the design of ASICs (Application Specific Integrated Circuits) appeared to be more and more reserved to high volume markets, because the design and fabrication costs of such components exploded, due to increasing NRE (Non Recurring-Engineering) costs. -\\ -FPGA (Field Programmable Gate Array) components, such as the +Fortunately, FPGA (Field Programmable Gate Array) components, such as the Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays -implement a complete MPSoC with multiple processors and several +implement a complete MPSoC with multiple processors and several dedicated coprocessors for a few keuros per device. In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping, @@ -20,25 +20,19 @@ major companies to design innovative devices and to enter new, low and medium volume markets. -\\ +\par The objective of COACH is to provide an integrated design flow, based on the SoCLib infrastructure~\cite{soclib}, and optimized for the design of -multi-processors digital systems targetting FPGA devices. +multi-processors digital systems targeting FPGA devices. Such digital systems are generally integrated into one or several chips, and there are two types of applications: -It can be embedded (autonomous) applications -such as personal digital assistants (PDA), ambiant computing components +They can be embedded (autonomous) applications +such as personal digital assistants (PDA), ambiant computing components, or wireless sensor networks (WSN) They can also be extension boards connected to a PC to accelerate a specific computation, as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP). -\\ -The COACH project fundamental issues are related to design methodologies -for digital systems, providing estimation, exploration and design tools -targeting both performance and power optimization at all the abstraction -levels of the flow (system, architecture, algorithm and logic). - +\par %verrous scientifiques et techniques \vspace*{.9ex}\par -The COACH environment mixes and integrates several hardware and software technologies. -The more important technologies are: +The COACH environment will integrate several hardware and software technologies: \begin{description} \item[Design Space Exploration] @@ -60,9 +54,10 @@ The HLS tools of COACH will support a common language and coding style to avoid re-engineering by the designer. -\item[Targeted hardware architecture and technology] +\item[Platform based design] COACH will handle both \altera and \xilinx FPGA devices. COACH will define architectural templates that can be customized by adding dedicated coprocessors and ASIPs and by fixing template parameters such as - the number of CPU and the operating system. + the number of embedded processors or the number of sizes of embedde memory banks, + or the embedded the operating system. Basically, the 3 following architectural templates will be provided: \begin{enumerate} @@ -76,9 +71,9 @@ Moreover, the specification of the application will be independant of both the architectural template and the target FPGA device. -\item[Communication interfaces] - Coach will define and implement an homogeneous HW/SW communication infrastructure and - communication APIs (Application Programming Interface). - These laters are on-chip communications between processors and coprocessors, - and external communications between the FPGA and the host PC. +\item[Hardware/Software communication middleware] + Coach will implement an homogeneous HW/SW communication infrastructure and + communication APIs (Application Programming Interface), that will be used for + communications between software tasks running on embedded processors and + dedicated hardware coprocessors, \end{description} The COACH design flow will be dedicated to system designers, and will as @@ -99,8 +94,6 @@ MPSoC architectures (\tima, \ubs, \upmc), ASIP architectures (\irisa), -High Level Synthesis (\tima, \ubs, \upmc) and compilation (\lip). +High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip). \\ -%The CoACH proposal can be described as an extension of the SoCLib virtual -%prototyping platform to the FPGA technologies. The COACH project does not start from scratch. It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping, @@ -115,34 +108,37 @@ \par The COACH proposal has been prepared during one year by a technical working group -involving all the academic partners (one monthly meeting from january 2009 to february -2010). The objective of these meetings was to analyse the issues of integrating -and enhancing the formers tools and tecnnologies into a unique framework allowing to both -virtual prototyping and hardware generation. +involving the 5 academic partners (one monthly meeting from january 2009 to february +2010). The objective was to analyse the issues of integrating +and enhancing the existing tools and tecnnologies into a unique framework. +Most of the general software architecture of the proposed design flow (including the +exchange format specification) has been define by this working group. Because the SocLib platform is the base of this project, it may be described as an extension of the SoCLib platform. + +%The main development steps of the COACH project are: +%\begin{enumerate} +% \item Definition of the end user inputs: +% The coarse grain parallelism of the application will be described as a communicating +% task graph, each task being described in C language. +% Similarly the architectural templates with their parameters and the design constraints +% will be specified. +% \item Definition of an internal format for representing task. +% \item Development of the GCC pluggin for generating the internal format of a +% C task. +% \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write +% the internal format. This will allow to swap from one tool to another one, and to +% chain them if necessary. +% \item Modification of the DSX tool (Design Space eXplorer) of the SocLib +% platform to generate the bitstream for the various FPGA families and architectural +% templates. +% \item Development of new tools such as ASIP compiler, HPC design environment and +% dynamic reconfiguration of FPGA devices. +%\end{enumerate} + \par -The main development steps of the COACH project are: -\begin{enumerate} - \item Definition of the end user inputs: - The coarse grain parallelism of the application will be described as a communicating - task graph, each task being described in C language. - Similarly the architectural templates with their parameters and the design constraints - will be specified. - \item Definition of an internal format for representing task. - \item Development of the GCC pluggin for generating the internal format of a - C task. - \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write - the internal format. This will allow to swap from one tool to another one, and to - chain them if necessary. - \item Modification of the DSX tool (Design Space eXplorer) of the SocLib - platform to generate the bitstream for the various FPGA families and architectural - templates. - \item Development of new tools such as ASIP compiler, HPC design environment and - dynamic reconfiguration of FPGA devices. -\end{enumerate} -\par -The two major FPGA companies \altera and \xilinx are participating in this -project to support the partners providing the software technologies, and to -help to generate efficient bitsream for both FPGA families. +Two major FPGA companies are involved in the project : \xilinx will contribute +as a contractual partner providing documentation and manpower; \altera will contribute as a supporter, +providing documentation and development boards (\altera). These two companies are strongly motivated +to help the COACH project to generate efficient bitsream for both FPGA families. The role of the industrial partners \bull, \thales, \navtel and \zied is to provide real use cases to benchmark the COACH design environment. @@ -152,5 +148,6 @@ The architectural templates, and the COACH software tools will be distributed under the GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib -IP core library) will be freely available for non commercial use. Commercial licences -will be negociated for industrial exploitation. +IP core library) will be freely available for non commercial use. For industrial exploitation +the technology providers are ready to propose commercial licenses, directly to the end user, +or through a third party. Index: /anr/section-2.1.tex =================================================================== --- /anr/section-2.1.tex (revision 96) +++ /anr/section-2.1.tex (revision 97) @@ -1,22 +1,20 @@ -Microelectronic allows the integration of complicated functions into products, increases +Microelectronic components allow the integration of complicated functions into products, increases commercial attractivity of these products and improves their competitivity. -Multimedia and communication sectors have taken advantage from microelectronics facilities -thanks to the developpment of design methodologies and tools for real time embedded -systems. -Many other sectors could benefit from microelectronics if these methologies and tools were -adapted to their features. The Non Recurring Engineering (NRE) costs involded in designing -and manufacturing an ASIC is very high. +Multimedia and tele-communication sectors have taken advantage from microelectronics facilities +thanks to the developpment of design methodologies and tools for embedded systems. +\par +Unfortunately, the Non Recurring Engineering (NRE) costs involded in designing +and manufacturing ASICs is very high. An IC foundry costs several billions of euros and the fabrication of a specific circuit costs several millions. For example a conservative estimate for a 65nm ASIC project is 10 million USD. -Consequently, it is generally unfeasible to design and fabricate ASICs in -low volumes and ICs are designed to cover a broad applications spectrum at the cost of -some performance degradation. -\\ +Consequently, it is generally unfeasible to design and fabricate ASICs for low and medium +volume markets. +\par Today, FPGAs become important actors in the computational domain that was originally dominated by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed -on a per-application basis. At the same time, for many applications, FPGAs offer significant performance benefits over -microprocessors implementation. Although these benefits are still -generally an order of magnitude less than in equivalent ASIC implementations, low costs +on a per-application basis. For many applications, FPGAs offer significant performance benefits over +microprocessors implementation. There is still a performance degradation of one order +of magnitude versus an equivalent ASIC implementations, but low cost (500 euros to 10K euros), fast time to market and flexibility of FPGAs make them an attractive choice for low-to-medium volume applications. @@ -27,7 +25,6 @@ complex systems like multi-processors platform with application dedicated coprocessors. Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years in -various application domains. The ``high end'' lines concern only FPGA with high logic capacity for complex system implementations. +various application domains. This market is in significant expansion and is estimated to 914\,M\$ in 2012. -Using FPGA limits the NRE costs to the design cost. This boosts the developpment of of automatic design tools and methodologies. \begin{table}\leavevmode\center @@ -50,52 +47,44 @@ \end{table} \par -Today, several companies (atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, -Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand -for very high performance (HPC) primes over other requirements. They tend to use the highest -performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative -architectures and algorithms. These companies show up in different "traditional" applications and market -segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC -emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers -at 214\,M\$. -This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion -of FPGA-based solutions is limited by the lack of design flow automation. Nowadays, there are neither commercial -nor academic tools covering the whole design process. -For instance, with SOPC Builder from Altera, users can select and parameterize IP components -from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor -and bus interface cores, as well as incorporate their own IP. Designers can then generate -a synthesized netlist, simulation test bench and custom software library that reflect the hardware -configuration. -Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I -(Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to -simulate the platform at a high design level (systemC). -In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation -tool to implement designs on Altera devices (Stratix, Arria, Cyclone). -PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description. -Nevertheless, they can only deal with data dominated applications and they do not handle the platform level. -The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to -Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. -Designers can design and simulate a system using MATLAB and Simulink. The tool will then -automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx -pre-optimized algorithms. -However, this tool targets only DSP based algorithms. -\\ -Consequently, designers developping an embedded system needs to master for example -SoCLib for design exploration, -SOPC Builder at the platform level, -PICO for synthesizing the data dominated coprocessors -and Quartus for design implementation. -This requires an important tools interfacing effort and makes the design process very complex -and achievable only by designers skilled in many domains. -The aim of the COACH project is to integrate all these tools in the same framework and to allow \textbf{pure software} developpers to realize embedded systems. + +This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion of FPGA-based solutions +is limited by the lack of design flow automation. Nowadays, there are neither commercial +nor academic tools covering the whole design process from the system level specification to the bit stream +generation. +%For instance, with SOPC Builder from Altera, users can select and parameterize IP components +%from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor +%and bus interface cores, as well as incorporate their own IP. Designers can then generate +%a synthesized netlist, simulation test bench and custom software library that reflect the hardware +%configuration. +%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I +(%Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to +%simulate the platform at a high design level (systemC). +%In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation +%tool to implement designs on Altera devices (Stratix, Arria, Cyclone). +%PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description. +%Nevertheless, they can only deal with data dominated applications and they do not handle the platform level. +%The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to +%Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. +%Designers can design and simulate a system using MATLAB and Simulink. The tool will then +%automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx +%pre-optimized algorithms. +%However, this tool targets only DSP based algorithms. + +Consequently, a designer developping an embedded system needs to master +four different design environment : a virtual prototyping environment such as SoCLib for system level exploration, +an architecture compiler (such as SOPC Builder from Altera, or System generator from Xilinx) to define the +hardware architecture, one or several HLS tools (such as PICO [CITATION] ou CATAPULT [CITATION]) for +coprocessor synthesis, and finally a backend synthesis tool (such as Quartus or YYYY) for the bit-stream generation. + +The aim of the COACH project is to integrate all these design steps into a single design framework. +and to allow \textbf{pure software} developpers to develop embedded systems. \par -The combination of the framework dedicated to software developpers and FPGA target, allows to gain -market share over Multi-core CPUs and GPUs HPC based solutions. -Moreover, one can expect that small and even very small companies will be able to propose embedded -system and accelerating solutions for standard software applications with acceptable prices, thanks - to the elimination of huge hardware investment in opposite to ASIC based solution. -\\ -This new market may explode in the same way as the micro-computer market in the eighties. This success was due -to the low cost of the first micro-processors (compared to main frames) and the advent of high level -programming languages which allowed a high number of programmers to launch start-ups in software -engineering. +We believe that the combination of a design environment dedicated to software developpers and the FPGA target, +allows small and even very small companies to propose embedded system and accelerating solutions +for standard software applications with acceptable prices. +This new market may explode in the same way as the micro-computer market in the eighties, +whose success was due to the low cost of the first micro-processors (compared to main frames) +and the advent of high level programming languages which allowed a high number of programmers +to launch start-ups in software engineering. + Index: /anr/section-2.2.tex =================================================================== --- /anr/section-2.2.tex (revision 96) +++ /anr/section-2.2.tex (revision 97) @@ -2,17 +2,18 @@ % Relevance of the proposal -The COACH proposal addresses directly the Embedded Systems of +The COACH proposal addresses directly the \emph{Embedded Systems} item of the ARPEGE program. It aims to propose solutions to the societal/economical challenges by -providing the industry the novel design capabilities enabling them to increase their +providing SMEs novel design capabilities enabling them to increase their design productivity with design exploration and synthesis methods that are placed on top -of the state-of-the-art methods, and thus, allowing the industry to better cope with the -complexity of designed digital systems. +of the state-of-the-art methods. +This project proposes an open-source framework for mapping multi-tasks software applications +on Field Programmable Gate Array circuits (FPGA). + \par -COACH will also contribute to the following strategic objectives of the ARPEGE program: -COACH will specifically contribute to enable the building of open development and run-time -environments for software and services, interoperable middleware and tools to support +COACH will contribute to build an open development and run-time +environment, including communication middleware and tools to support developers in the production of embedded software, through all phases of the software lifecycle, from requirements analysis until deployment and maintenance. -\\ + More specifically, COACH focuses on: \begin{itemize} @@ -25,4 +26,5 @@ environment, suitable for co-operative and distributed development. \end{itemize} + COACH outcome will contribute to strengthen Europe's competitive position by developing technologies and methodologies for product development, focusing (in compliance with the @@ -31,30 +33,61 @@ in COACH will enable new and emerging information technologies for the development, manufacturing and integration of devices and related software into end-products. -\\ -This project proposes an open-source framework for architecture synthesis targeting -Field Programmable Gate Array circuits (FPGA). + \par -% LIEN AVEC AUTRES PROJETS: LIP6/TIMA OK -To evaluate the different architectures, the project uses the prototyping platform of the SoCLIB ANR project (2006-2009). -\\ % LIEN AVEC AUTRES PROJETS: IRISA -The project will also borrow from the ROMA ANR project (2007-2009) and the ongoing -joint INRIA-STMicro Nano2012 project. In particular we will adapt existing pattern +The COACH project will benefit from a number of previous projects: +\begin{itemize} +\item SOCLIB : +The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories +and 6 industrial companies. +It supports system level virtual prototyping of shared memory, multi-processors +architectures, and provides tools to map multi-tasks software application on these +architectures, for reliable performance evaluation. +The core of this platform is a library of SystemC simulation models for +general purpose IP cores such as processors, buses, networks, memories, IO controller. +The platform provides also embedded operating systems and software/hardware +communication middleware. +The synthesisable VHDL models of IPs are not part of the SoCLib platform, and +this project enhances SoCLib by providing the synthesisable VHDL models required +for FPGA synthesis. +\item ROMA : +The ROMA ANR project (2007-2009) involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a +reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its +computing structure to computation patterns that can be speed-up and/or power efficient. +The ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable +operators to avoid traditional overhead, in reconfigurable devices, related to +the interconnection network. +The project will borrow from the ROMA ANR xxproject (2007-2009) and the ongoing +joint INRIA-STMicro Nano2012 project to adapt existing pattern extraction algorithms and datapath merging techniques to the synthesis of customized ASIP processors. -\par +\item TSAR : +The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the LIP6 targets the design of a +scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib +plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL +models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect). +\item BioWic On the HPC application side, we also hope to benefit from the experience in hardware acceleration of bioinformatic algorithms/workfows gathered by the CAIRN group in the context of the ANR BioWic project (2009-2011), so as to be able to validate the framework on real-life HPC applications. +\end{itemize} + + \par -%%% EXPERTISE DANS DES DOMAINES: LIP6/TIMA/LAB-STIC OK -Regarding the expertise in High Level Synthesis (HLS), the project -leverages on know-how acquired over 15 years with GAUT~\cite{gaut08} project -developped in Lab-STIC laboratory and UGH~\cite{ugh08} project developped -in LIP6 and TIMA laboratories. \\ -Regarding architecture synthesis skills, the project is based on a know-how -acquired over 10 years with the COSY European project (1998-2000) and the -DISYDENT~\cite{disydent05} project developped in LIP6.\\ -%%% EXPERTISE DANS DES DOMAINES: IRISA OK +The laboratories involved in the COACH project have a well estabished expertise +in the following domains: +\begin{itemize} +\item +In the field of High Level Synthesis (HLS), the project +leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project +developped by the Lab-STIC laboratory, and with the UGH~\cite{ugh08} project developped +by the LIP6 and TIMA laboratories. +\item +Regarding system level architecture, the project is based on the know-how +acquired by the LIP6 and TIMA laboratories in the framework of various projects +(COSY \cite{disydent}, or MEDEA MESA \cite{dspin}), in the field of communication +architectures for shared memory multi-processors systems. +As an example, the DSPIN network on chip, is now used by BULL in the TSAR project. +\item Regarding Application Specific Instruction Processor (ASIP) design, the CAIRN group at INRIA Bretagne Atlantique benefits from several years of @@ -62,6 +95,7 @@ (Armor/Calife\cite{CODES99} since 1996, and the Gecos compilers\cite{ASAP05} since 2002). -%%% EXPERTISE DANS DES DOMAINES: LIP OK -Compsys was founded in 2002 by several senior researchers with experience in +\item +In the field of compilers, the Compsys group was founded in 2002 +by several senior researchers with experience in high performance computing and automatic parallelization. They have been among the initiators of the polyhedral model, a theory which serve to @@ -69,51 +103,16 @@ programs. It is expected that the techniques developped by Compsys for parallelism detection, scheduling, process construction and memory management -will be very useful as a first step for a high-level synthesis tool. +will be very useful as a Rfront end for the a high-level synthesis tools. +\end{itemize} + \par -%%% DESCRIPTION DES PROJETS ANR UTILISES: SOCLIB OK -The SoCLIB ANR platform were developped by 11 laboratories and 6 companies. It allows to -describe hardware architectures with shared memory space and to deploy software -applications on them to evaluate their performance. -The heart of this platform is a library containing simulation models (in SystemC) -of hardware IP cores such as processors, buses, networks, memories, IO controller. -The platform provides also embedded operating systems and software/hardware -communication components useful to implement applications quickly. -However, the synthesisable description of IPs have to be provided by users. \\ -This project enhances SoCLib by providing synthesisable VHDL of standard IPs. -In addition, HLS tools such as UGH and GAUT allow to get automatically a synthesisable -description of an IP (coprocessor) from a sequential algorithm. -\par - -%In multimedia applications, image processing is the major challenge embedded systems -%have to face. It is computationally intensive with power requirements to meet. Image -%processing at pixel level, like image filtering, edge detection, pixel correlation or at -%bloc level such as motion estimation have to be accelerated. For that goal, - -The ROMA project involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a -reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its -computing structure to computation patterns that can be speed-up and/or power efficient. -On the contrary of previous attempts to design reconfigurable processors, which have -focused on the definition of complex interconnection network between simple operators, -the ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable -operators to avoid traditional overhead, in reconfigurable devices, related to -the interconnection network. -%%% DESCRIPTION DES PROJETS ANR UTILISES: ROMA FIXME:IRISA (~10 lignes) -%%% 2 IRISA ? -%%% 2 ASIP tool such as ... -%%% 2 ... -%%% 2 Coach uses pattern extractions from ROMA -\mustbecompleted{ROMA \\...\\...\\...\\...\\...\\...\\...\\IRISA (SD)\\} -\par % FIXME A VERIFIER L'appel d'offre -The different points proposed in this project cover priorities defined by the commission +Finally, it is worth to note that this project cover priorities defined by the commission experts in the field of Information Technolgies Society (IST) for Embedded -systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity +Systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity and allowing to apply efficiently applications and various products on embedded platforms, considering resources constraints (delais, power, memory, etc.), security and quality services$>>$. -\\ -Our team aims at covering all the steps of the design flow of architecture synthesis. -Our project overcomes the complexity of using various synthesis tools and description -languages required today to design architectures. + Index: /anr/section-2.tex =================================================================== --- /anr/section-2.tex (revision 96) +++ /anr/section-2.tex (revision 97) @@ -1,101 +1,105 @@ -The emerging complex and integrated heterogeneous embedded system platforms require -adequate design methods to efficiently model, explore, analyze and design the ever complex software -and hardware architectures. In order to rapidly meet the increasing performance requirements and a pressure -to lower development cost and shorten time-to-market, future embedded systems suppliers -will have to adopt new design methodologies and flows in order to keep pace with the increasing -complexity of design problems. Such methods, addressing these challenges starting from high levels of -abstraction, will have to perform large solution space explorations both for software and (possibly -reconfigurable) hardware, reducing the design effort and offering a high predictability of results -with respect to cost and performance objectives. -\\ -Current design methodologies provide quite low-level abstraction capabilities. However in a few years -from now, tens of programmable processors will be embedded in an IC with more than 100M -transistors, therefore adding to the complexity of the problem of designing such systems. -Taking into account that the complexity of the software part is increasing at an even -faster rate, current solutions for design space exploration, mainly manually based, by no -means do supply an adequate efficiency. -Consequently, there is an urgent need to leverage system level -exploration through the use of a high-level specification of the application and an early design -space exploration step. The first system oriented approaches are appearing, among which those -based on C/C++ and SystemC are the most popular. Such approaches can take place before and/or after -the co-design or architecture refinement steps and target the design space pruning in order to fully -exploit potential solutions that meet design and application constraints (power, latency, -throughput) within the design and market timeframe. -\\ -Thus, new system-level design flows need to be developed, enabling the exploration of an application -independently of the implementation, almost at the beginning of the design process. -A fundamental element of this evolution is the definition of abstraction layers that should allow the -performance driven re-use of software and hardware components at the system level. -In this context, COACH will combine modeling and estimation methods and compilers and -design space exploration techniques. This approach will be a radical innovation in -embedded system design methodology. -\\ -The reason is that the COACH framework is applied before high-level design tools in the embedded -systems design flow. In that way, it will make possible a real and efficiently combined -exploitation of high-level synthesis tools, parallelizing approaches and compilers, already -available on the market. These tools and approaches are not yet massively adopted, precisely -because this preliminary design step is missing. COACH will indeed permit (i) to predict and -control implementation optimizations, (ii) to target multiple implementation technologies -(and thus the associated tools) from a unique specification and (iii) to efficiently integrate high -and low-level design tools in a unique seamless design flow. -\\ -The performance estimation methods combined with the design space exploration techniques will -finally allow the design process to start from system level specification and automatically explore the -potential architectures in order to find out the optimal implementation in a shorter design time and at -a lower global cost. +The first objective of COACH is to provide SMEs (Small and Medium Enterprises) an open-source framework to +design embedded system on FPGA devices. + +Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit) +is not an option for most SMEs. Fortunately, the new FPGA (Field Programmable Gate Array) components, +such as the Virtex5 family from Xilinx, or the Stratix4 family from Altera can implement a complete +multi-processor architecture on a single chip. + +%But the design of a SoC (System on Chip) or MPSoC (Multi-Processor System on Chip) is a complex +%task, requiring adequate design methods to efficiently model, explore, and analyze the +%interactions between the software application and the hardware architectures. Moreover, most SMEs do not have +%in-home expertise in the field of hardware design or VHDL/Verilog modeling. +%In order to meet the increasing performance requirements, to decrease the development cost, and to +%shorten the time-to-market, they need new design methodologies. + +%Current design methodologies provide quite low-level abstraction capabilities, and +%there is an urgent need to leverage system level exploration through the use of a high-level +%specification of the application and design space exploration tools. + +%The first system oriented approaches are appearing, among which those +%based on C/C++ and SystemC are the most popular, but few of them are specifically targetting FPGAs. + +The COACH project will leverage on the expertise gained in the field of virtual prototyping +with the SoCLib platform, to propose a new design flow based on a small number of architectural templates. +An architectural template is a generic, parametrized architecture, relying on a predefined library +of IP cores. +Besides using a specific collection of general purpose IP cores (such as processors cores, +embedded memory controllers, system bus controllers, I/O and peripheral controllers), each architectural +template can be enriched by dedicated hardware coprocessors, obtained by high level synthesis (HLS) tools. +During this project, the COACH partners will develop three different architectural templates: + +\begin{enumerate} +\item An \altera architectural template based on the \altera IP core library and the AVALON system bus. +\item A \xilinx architectural template based on the Xlinx IP core library and the OPB system bus. +\item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP communication infrastructure. +\end{enumerate} + +The proposed design flow starts from a high level description of the application, specified as a set of +parallel tasks written in C, without any assumption on the hardware or software implementation +of these tasks. It let the system +designer in charge of expessing the coarse grain parallelism of the application, gives the designer +the possibility to explore various mapping of the application on the selected template architecture, +and offers a high predictability of results with respect to cost and performance objectives. + +When this interactive, system level, design space exploration is completed (converging to +a specific mapping on a specific version of the selected architectural template), the rest of the flow +is fully automated: The synthesisable VHDL models for the various hardware components, as well as the binary +code for the software running on the embedded processors, and the bit-stream to program the the target FPGA +will be automatically generated by the COACH tools. + \par -To get an efficient embedded system, the system designer has to take into account -application characteristics when it chooses one of the available technologies. -This choice is not easy and in most cases the designer has to try different -technologies to retain the most adapted one. -\\ -The first objective of COACH is to provide an open-source framework to -design embedded system on FPGA devices. -The COACH framework allows the designer to explore various software/hardware -partitions of the target application, to run timing and functional -simulations and to generate automatically both the software and the -synthesizable description of the hardware. -The main topics of the project are: -\begin{itemize} -\item -\textbf{Design space exploration}: It consists in analysing the application running -on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and -hardware/software partitioning of tasks depending on technology choice. -This exploration is driven basically by throughput, latency and power -consumption criteria. -\item -\textbf{Micro-architectural exploration}: When hardware components are required, the -HLS tools of the framework generate them automatically. At this stage the -framework provides various HLS tools that allow the micro-architectural space -design exploration. The exploration criteria also are throughput, latency -and power consumption. -At this stage, preliminary source-level transformations will be -required to improve the efficiency of the target component. -For instance, one may transform a loop nest to expose parallelism, -or shrink an array to promote it to a register or reduce a memory footprint. +The strength of the COACH approach is the strong integration of the high-level synthesis tools +in a plat-form based design flow supporting virtual prototyping and design space exploration. +Most building blocks already exist (resulting from previous projects): the GAUT +or UGH synthesis tools, the MutekH or DNA embedded operating systems, the ASIP technology, +the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelisation tool, +as well as the SoCLib library of systemC simulation models. They must now be integrated in +a consistent design flow. +%The five academic laboratories worked very closely during more than one year (one monthly meeting +%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating +%those various technologies, and to define the detailed architecture of the proposed design flow. +\par -\item -\textbf{Performance measurement}: For each point in the design space, -figures of merit are available such as throughput, latency, power -consumption, area, memory allocation and data locality. They are evaluated -using virtual prototyping, estimation or analyzing methodologies. -\item -\textbf{Targeted hardware technology}: The COACH description of a system is -independent of the FPGA family. Every point of the design -space can be implemented on any FPGA having the required resources. -Basically, COACH handles both Altera and Xilinx FPGA families. -\end{itemize} -As an extension of embedded system design, COACH deals also with High -Performance Computing (HPC). -In HPC, the kind of targeted application is an existing one running on a PC. -The COACH framework helps designer to accelerate it by migrating critical parts into a -SoC implemented on an FPGA plugged to the PC bus. -\par -COACH is the result of the will of several laboratories to unify their knowhow -and skills in the following domains: Operating system and hardware -communication (\tima, \upmc), SoC and MPSoC (\upmc and \tima), ASIP (\irisa) and -HLS (\upmc, \ubs) and compilation (\irisa, \lip). -The project objective is to integrate these various domains into a unique -free framework (licence ...) masking as much as possible these domains and -its different tools to the user. +In summary, the COACH project is clearly oriented toward industry, even if most technology building blocks +have been previously developed by academic laboratories. + +%Finally, the key points of the proposed design flow are : +%\begin{itemize} +%\item +%\textbf{System level exploration}: The application coarse grain parallelism +%is explicitely described as a Tasks and Communication Graph (TCG). +%A template architecture is selected, and the performances are evaluated +%on various variant of this architecture using the SoCLib virtual protyping +%environment. This result in a specific hardware/software partitioning. +%This system level exploration is fully controlled by the system designer, and is driven +%by cost, throughput, latency and power consumption criteria. +% +%\item +%\textbf{High Level Synthesis}: When dedicated hardware coprocessors have been +%identified as mandatory, they will be generated by the high level synthesis (HLS) tools. +%The Coach framework will integrate various HLS tools, supporting the micro-architectural space +%design exploration. Here again, the exploration criteria are cost, throughput, latency +%and power consumption. +%At this stage, preliminary source-level transformations and optimisations by front-end +%tools will be required to improve the efficiency of the back-end HLS tools. +% +%\item +%\textbf{Early performance evaluation}: For each point in the design space, +%figures of merit must be available such as throughput, latency, power +%consumption, area, memory allocation and data locality. They are evaluated +%by reliable estimators obtained by running the actual multi-task software +%application on the virtual prototype. +% +%\item +%\textbf{Independance from the Target FPGA}: The COACH description of the system +%(both hardware and software) should be independent of the FPGA family. +%Every point of the design space can be implemented on any FPGA component, +%as long as it contains the hardware ressources required by the selected architectural template. +%Basically, COACH will support both Altera and Xilinx FPGA families. +%\end{itemize} +% + + + Index: /anr/section-6.1.tex =================================================================== --- /anr/section-6.1.tex (revision 96) +++ /anr/section-6.1.tex (revision 97) @@ -102,8 +102,12 @@ The LIP6 is in charge of the technical coordination of the SoCLib national project, and is hosting the SoCLib WEB server. -%The LIP6 will be in charge of integrating the Coach results in the frame work of -%the SoCLib infrastructure to provide an open access to the Coach design environment. -Moreover, the LIP6 developped during the last 10 years the UGH tool for high level synthesis, -and the DSX tool for design space exploration, that will be two building blocks for the Coach design-flow. +In the SoCLin platform, the DSX tool is used for design space exploration. +It helps the system designer to describe the coarse grain parallelism of the software application +as a Task and Communication Graph, to configure the hardware architecture, and to map the +multi-task software application on the multi-processors architecture. +The DSX toll will be extended to support the FPGA target. +Moreover, the LIP6 developped during the last 10 years the UGH tool for high level synthesis +of control-dominated coprocessors. +This tool will be modified to be integrated in the Coach design flow. Even if the preferred dissemination policy for the Coach design flow will be the free software policy, (following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies Index: /anr/table_lip_full.tex =================================================================== --- /anr/table_lip_full.tex (revision 96) +++ /anr/table_lip_full.tex (revision 97) @@ -1,11 +1,0 @@ -\begin{tabular}{|c|p{3.5cm}||r|r|r||r|}\hline -number & \multicolumn{1}{c||}{title} & \multicolumn{3}{c||}{years } & total \\\cline{3-5} - & & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{2} & \multicolumn{1}{c||}{3} & \\\hline\hline -D230 & \resstablestyletitle{Specification of {\tt xcoach} format} & 9.0 & 4.5 & 0.0 & 13.5 \\\hline - & total Task-2 & 9.0 & 4.5 & 0.0 & 13.5 \\\hline -\hline D430 & \resstablestyletitle{Process generation method} & 4.5 & 0.0 & 10.5 & 15.0 \\\hline -D431 & \resstablestyletitle{Process and FIFO construction} & 4.5 & 12.0 & 15.0 & 31.5 \\\hline - & total Task-4 & 9.0 & 12.0 & 25.5 & 46.5 \\\hline -\hline - & total & 18.0 & 16.5 & 25.5 & 60.0 \\\hline -\end{tabular} Index: /anr/table_lip_short.tex =================================================================== --- /anr/table_lip_short.tex (revision 96) +++ /anr/table_lip_short.tex (revision 97) @@ -1,8 +1,0 @@ -\begin{center}\begin{small}\begin{tabular}{|c|l||r|r|r||r|}\hline - & title & \multicolumn{3}{c||}{years } & total \\\cline{3-5} - & & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{2} & \multicolumn{1}{c||}{3} & \\\hline\hline -Task-2 & Backbone infrastructure & 9.0 & 4.5 & 0.0 & 13.5 \\\hline -Task-4 & HAS front-end & 9.0 & 12.0 & 25.5 & 46.5 \\\hline -\hline - & total & 18.0 & 16.5 & 25.5 & 60.0 \\\hline -\end{tabular}\end{small}\end{center}