Index: /anr/Makefile =================================================================== --- /anr/Makefile (revision 98) +++ /anr/Makefile (revision 99) @@ -15,4 +15,6 @@ table_tima_full.tex table_tima_short.tex \ table_lip_full.tex table_lip_short.tex \ + table_ubs_full.tex table_ubs_short.tex \ + table_xilinx_full.tex table_xilinx_short.tex \ # PROGRAMS Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 98) +++ /anr/anr.tex (revision 99) @@ -1,3 +1,3 @@ -\documentclass[12pt,a4paper]{article} +\documentclass[11pt,a4paper]{article} \usepackage[french]{babel} @@ -14,5 +14,5 @@ \usepackage{geometry} \usepackage{textcomp} -\geometry{verbose,a4paper,tmargin=3cm,bmargin=2cm,lmargin=2cm,rmargin=3cm} +\geometry{verbose,a4paper,tmargin=3cm,bmargin=2cm,lmargin=2cm,rmargin=2cm} \usepackage{anr} @@ -31,12 +31,13 @@ \definecolor{rouge}{rgb}{1.0,0.2,0.2} \def\mustbecompleted#1{} +\def\parlf{\vspace*{1.0ex}\par} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \def\Sformat#1{\begin{small}\textsc{#1}\end{small}} \def\irisa{IRISA\xspace} \def\Sirisa{\Sformat{IRI}\xspace} -\def\citi{CITI\xspace} \def\Sciti{\Sformat{CITI}\xspace} +%\def\citi{CITI\xspace} \def\Sciti{\Sformat{CITI}\xspace} \def\lip{LIP\xspace} \def\Slip{\Sformat{LIP}\xspace} \def\tima{TIMA\xspace} \def\Stima{\Sformat{TIMA}\xspace} -\def\ubs{UBS\xspace} \def\Subs{\Sformat{UBS}\xspace} +\def\ubs{LAB-STICC\xspace} \def\Subs{\Sformat{UBS}\xspace} \def\upmc{LIP6\xspace} \def\Supmc{\Sformat{LIP6}\xspace} \def\altera{ALTERA\xspace} \def\Saltera{\Sformat{ALTE}\xspace} @@ -62,7 +63,7 @@ \def\anrdoc#1{\noindent\begin{scriptsize}\textcolor{red}{#1}\end{scriptsize}\ifhmode\par\fi} % Comment the next macro to suppress the pagefeed -\let\pagefeed\newpage +%\let\pagefeed\newpage % Comment the next macro to suppress it -\def\mustbecompleted#1{\textcolor{gris}{#1}} +\def\mustbecompleted#1{\textcolor{red}{#1}} % FIN CONFIG %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -191,4 +192,5 @@ % 4.3 \pagefeed\subsection{Description of the tasks} +\label{task-description} \anrdoc{(idéalement 1 ou 2 pages par tâche) Pour chaque tâche, décrire:\begin{itemize} @@ -226,4 +228,5 @@ \subsubsection{Task 8: \textit{Dissemination}} +\label{task-7} \input{task-7} Index: /anr/dependence-task-h.fig =================================================================== --- /anr/dependence-task-h.fig (revision 98) +++ /anr/dependence-task-h.fig (revision 99) @@ -14,11 +14,4 @@ 0 0 1.00 60.00 120.00 -681 690 -231 1275 -2 1 0 3 0 7 90 -1 -1 0.000 0 0 -1 1 0 2 - 0 0 1.00 60.00 120.00 - -2070 1350 -1620 1350 -2 1 0 3 0 7 100 -1 -1 0.000 0 0 -1 1 0 10 - 0 0 1.00 60.00 120.00 - 405 1350 450 1350 540 1350 585 1350 630 1350 675 1350 - 720 1350 765 1350 810 1350 855 1350 2 2 1 1 0 7 80 -1 -1 4.000 0 0 -1 0 0 5 -1665 2475 1800 2475 1800 225 -1665 225 -1665 2475 @@ -50,4 +43,11 @@ 2 2 0 1 0 7 80 -1 -1 0.000 0 0 -1 0 0 5 -2700 1125 -2070 1125 -2070 1575 -2700 1575 -2700 1125 +2 1 0 4 0 7 90 -1 -1 0.000 0 0 -1 1 0 2 + 0 0 1.00 60.00 120.00 + -2070 1350 -1620 1350 +2 1 0 4 0 7 100 -1 -1 0.000 0 0 -1 1 0 10 + 0 0 1.00 60.00 120.00 + 405 1350 450 1350 540 1350 585 1350 630 1350 675 1350 + 720 1350 765 1350 810 1350 855 1350 4 0 0 70 -1 18 16 0.0000 4 195 315 3330 90 T1\001 4 1 0 90 -1 18 16 0.0000 4 195 315 2925 945 T7\001 Index: /anr/section-1.tex =================================================================== --- /anr/section-1.tex (revision 98) +++ /anr/section-1.tex (revision 99) @@ -4,5 +4,5 @@ integration of heterogeneous technologies and requires the design of complex Multi-Processors System on Chip (MPSoC). -\par +\\ During the last decade, the design of ASICs (Application Specific Integrated Circuits) appeared to be more and more reserved to high volume markets, because @@ -20,5 +20,5 @@ major companies to design innovative devices and to enter new, low and medium volume markets. -\par +\parlf The objective of COACH is to provide an integrated design flow, based on the SoCLib infrastructure~\cite{soclib}, and optimized for the design of @@ -31,7 +31,6 @@ They can also be extension boards connected to a PC to accelerate a specific computation, as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP). -\par +\parlf %verrous scientifiques et techniques -\vspace*{.9ex}\par The COACH environment will integrate several hardware and software technologies: \begin{description} @@ -66,5 +65,5 @@ \item An \altera architectural template based on the \altera IP core library and the AVALON system bus. - \item A \xilinx architectural template based on the Xlinx IP core library and the OPB + \item A \xilinx architectural template based on the Xlinx IP core library and the PLB system bus. \end{enumerate} @@ -82,7 +81,6 @@ %independant from both the architectural template and from the selected FPGA %family. - +\parlf % le programme de travail -\vspace*{.9ex}\par %The COACH project targets fundamental issues related to design methodologies for %digital systems by providing estimation, exploration and design tools targeting both @@ -106,5 +104,5 @@ Finally it will use the \xilinx and \altera RTL tools to generate the FPGA configuration bitstreams. -\par +\parlf The COACH proposal has been prepared during one year by a technical working group involving the 5 academic partners (one monthly meeting from january 2009 to february @@ -115,5 +113,4 @@ Because the SocLib platform is the base of this project, it may be described as an extension of the SoCLib platform. - %The main development steps of the COACH project are: %\begin{enumerate} @@ -135,13 +132,12 @@ % dynamic reconfiguration of FPGA devices. %\end{enumerate} - -\par +\parlf Two major FPGA companies are involved in the project : \xilinx will contribute as a contractual partner providing documentation and manpower; \altera will contribute as a supporter, -providing documentation and development boards (\altera). These two companies are strongly motivated +providing documentation and development boards. These two companies are strongly motivated to help the COACH project to generate efficient bitsream for both FPGA families. The role of the industrial partners \bull, \thales, \navtel and \zied is to provide real use cases to benchmark the COACH design environment. -\par +\parlf Following the general policy of the SoCLib platform, the COACH project will be an open infrastructure, available in the framework of the SoCLib server. Index: /anr/section-2.1.tex =================================================================== --- /anr/section-2.1.tex (revision 98) +++ /anr/section-2.1.tex (revision 99) @@ -1,7 +1,25 @@ +\begin{table}\leavevmode\center +\begin{small}\begin{tabular}{|l|l|l|l|}\hline +Segment & 2010 & 2011 & 2012 \\\hline\hline +Communications & 1,867 & 1,946 & 2,096 \\ +High end & 467 & 511 & 550 \\\hline +Consumer & 550 & 592 & 672 \\ +High end & 53 & 62 & 75 \\\hline +Automotive & 243 & 286 & 358 \\ +High end & - & - & - \\\hline +Industrial & 1,102 & 1,228 & 1,406 \\ +High end & 177 & 188 & 207 \\\hline +Military/Aereo & 566 & 636 & 717 \\ +High end & 56 & 65 & 82 \\\hline\hline +Total FPGA/PLD & 4,659 & 5,015 & 5,583 \\ +Total High-End FPGA & 753 & 826 & 914 \\\hline +\end{tabular}\end{small} +\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)} +\end{table} +% Microelectronic components allow the integration of complicated functions into products, increases commercial attractivity of these products and improves their competitivity. Multimedia and tele-communication sectors have taken advantage from microelectronics facilities thanks to the developpment of design methodologies and tools for embedded systems. -\par Unfortunately, the Non Recurring Engineering (NRE) costs involded in designing and manufacturing ASICs is very high. @@ -11,5 +29,5 @@ Consequently, it is generally unfeasible to design and fabricate ASICs for low and medium volume markets. -\par +\parlf Today, FPGAs become important actors in the computational domain that was originally dominated by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed @@ -20,71 +38,81 @@ choice for low-to-medium volume applications. Since their introduction in the mid eighties, FPGAs evolved from a simple, -low-capacity gate array to devices (Altera STRATIX III, Xilinx Virtex V) that +low-capacity gate array to devices (\altera STRATIX III, Xilinx Virtex V) that provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement complex systems like multi-processors platform with application dedicated coprocessors. Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years in -various application domains. +various application domains. The ``high end'' lines concern only FPGA with high logic +capacity for complex system implementations. This market is in significant expansion and is estimated to 914\,M\$ in 2012. - -\begin{table}\leavevmode\center -\begin{tabular}{|l|l|l|l|}\hline -Segment & 2010 & 2011 & 2012 \\\hline\hline -Communications & 1,867 & 1,946 & 2,096 \\ -High end & 467 & 511 & 550 \\\hline -Consumer & 550 & 592 & 672 \\ -High end & 53 & 62 & 75 \\\hline -Automotive & 243 & 286 & 358 \\ -High end & - & - & - \\\hline -Industrial & 1,102 & 1,228 & 1,406 \\ -High end & 177 & 188 & 207 \\\hline -Military/Aereo & 566 & 636 & 717 \\ -High end & 56 & 65 & 82 \\\hline\hline -Total FPGA/PLD & 4,659 & 5,015 & 5,583 \\ -Total High-End FPGA & 753 & 826 & 914 \\\hline -\end{tabular} -\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)} -\end{table} -\par - -This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion of FPGA-based solutions -is limited by the lack of design flow automation. Nowadays, there are neither commercial -nor academic tools covering the whole design process from the system level specification to the bit stream -generation. -%For instance, with SOPC Builder from Altera, users can select and parameterize IP components -%from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor -%and bus interface cores, as well as incorporate their own IP. Designers can then generate -%a synthesized netlist, simulation test bench and custom software library that reflect the hardware -%configuration. -%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I -(%Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to -%simulate the platform at a high design level (systemC). -%In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation -%tool to implement designs on Altera devices (Stratix, Arria, Cyclone). -%PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description. -%Nevertheless, they can only deal with data dominated applications and they do not handle the platform level. -%The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to -%Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. -%Designers can design and simulate a system using MATLAB and Simulink. The tool will then -%automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx -%pre-optimized algorithms. -%However, this tool targets only DSP based algorithms. - -Consequently, a designer developping an embedded system needs to master -four different design environment : a virtual prototyping environment such as SoCLib for system level exploration, -an architecture compiler (such as SOPC Builder from Altera, or System generator from Xilinx) to define the -hardware architecture, one or several HLS tools (such as PICO [CITATION] ou CATAPULT [CITATION]) for -coprocessor synthesis, and finally a backend synthesis tool (such as Quartus or YYYY) for the bit-stream generation. - +The HPC market size is estimated today by FPGA providers at 214\,M\$. +Using FPGA limits the NRE costs to the design cost. +This boosts the developpment of automatic design tools and methodologies. +% +%Today, several companies (atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, +%Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand +%for very high performance (HPC) primes over other requirements. They tend to use the highest +%performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative +%architectures and algorithms. These companies show up in different "traditional" applications and market +%segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC +%emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers +%at 214\,M\$. +%%% +\parlf +This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion +of FPGA-based solutions is limited by the lack of design flow automation. +Nowadays, there are neither commercial nor academic tools covering the whole design process +from the system level specification to the bit stream generation. +\\ +% IA to Alain: J'ai remis (et ameliore un peu) ca car sinon le Consequently 20 lignes +% au dessous n'a pas de sens. +% Deplus dans les demandes ANR de la section, il est demande: analyse de la concurrence +For instance, with SOPC Builder~\cite{spoc-builder} from \altera, designers can select and +parameterize components from an extensive drop-down list of IP cores (I/O core, DSP, +processor, bus core, ...) as well as incorporate their own IP. +Designers can then generate a synthesized netlist, simulation test bench and custom +software library that reflect the hardware configuration. +%% Steven disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this. +%% IA: ces lignes ont ete verifiees et corrigée pa altera. De plus C2H est plutot limite. +Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to +simulate the platform at a high design level (systemC). +In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation +tool to implement designs on \altera devices (Stratix, Arria, Cyclone). +\\ +For instance, PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize +coprocessors from a C++ description. +Nevertheless, they can only deal with data dominated applications and they do not handle +the platform level. +\\ +Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to +Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs. +Designers can design and simulate a system using MATLAB and Simulink. The tool will then +automatically generate synthesizable Hardware Description Language (HDL) code mapped to +\xilinx pre-optimized macro-cells. +However, this tool targets only DSP based algorithms. +\\ +Consequently, a designer developping an embedded system needs to master four different +design environments: +\begin{enumerate} + \item a virtual prototyping environment such as SoCLib for system level exploration, + \item an architecture compiler (such as SOPC Builder from \altera, or System generator from Xilinx) + to define the hardware architecture, + \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for + coprocessor synthesis, + \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation. +\end{enumerate} +Furthermore, mixing these tools requires an important interfacing effort and this makes +the design process very complex and achievable only by designers skilled in many domains. +\begin{center}\begin{minipage}{.8\linewidth}\textit{ The aim of the COACH project is to integrate all these design steps into a single design framework. and to allow \textbf{pure software} developpers to develop embedded systems. -\par -We believe that the combination of a design environment dedicated to software developpers and the FPGA target, +}\end{minipage}\end{center} +\parlf +We believe that the combination of a design environment dedicated to software developpers +and the FPGA target, allows small and even very small companies to propose embedded system and accelerating solutions for standard software applications with acceptable prices. - This new market may explode in the same way as the micro-computer market in the eighties, whose success was due to the low cost of the first micro-processors (compared to main frames) and the advent of high level programming languages which allowed a high number of programmers to launch start-ups in software engineering. - Index: /anr/section-2.2.tex =================================================================== --- /anr/section-2.2.tex (revision 98) +++ /anr/section-2.2.tex (revision 99) @@ -9,11 +9,10 @@ This project proposes an open-source framework for mapping multi-tasks software applications on Field Programmable Gate Array circuits (FPGA). - -\par +%%% +\parlf COACH will contribute to build an open development and run-time environment, including communication middleware and tools to support developers in the production of embedded software, through all phases of the software lifecycle, from requirements analysis until deployment and maintenance. - More specifically, COACH focuses on: \begin{itemize} @@ -26,5 +25,6 @@ environment, suitable for co-operative and distributed development. \end{itemize} - +%%% +\parlf COACH outcome will contribute to strengthen Europe's competitive position by developing technologies and methodologies for product development, focusing (in compliance with the @@ -33,80 +33,77 @@ in COACH will enable new and emerging information technologies for the development, manufacturing and integration of devices and related software into end-products. - -\par +%%% +\parlf The COACH project will benefit from a number of previous projects: -\begin{itemize} -\item SOCLIB : -The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories -and 6 industrial companies. -It supports system level virtual prototyping of shared memory, multi-processors -architectures, and provides tools to map multi-tasks software application on these -architectures, for reliable performance evaluation. -The core of this platform is a library of SystemC simulation models for -general purpose IP cores such as processors, buses, networks, memories, IO controller. -The platform provides also embedded operating systems and software/hardware -communication middleware. -The synthesisable VHDL models of IPs are not part of the SoCLib platform, and -this project enhances SoCLib by providing the synthesisable VHDL models required -for FPGA synthesis. -\item ROMA : -The ROMA ANR project (2007-2009) involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a -reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its -computing structure to computation patterns that can be speed-up and/or power efficient. -The ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable -operators to avoid traditional overhead, in reconfigurable devices, related to -the interconnection network. -The project will borrow from the ROMA ANR xxproject (2007-2009) and the ongoing -joint INRIA-STMicro Nano2012 project to adapt existing pattern -extraction algorithms and datapath merging techniques to the synthesis of customized -ASIP processors. -\item TSAR : -The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the LIP6 targets the design of a -scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib -plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL -models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect). -\item BioWic -On the HPC application side, we also hope to benefit from the experience in -hardware acceleration of bioinformatic algorithms/workfows gathered by the -CAIRN group in the context of the ANR BioWic project (2009-2011), so as to -be able to validate the framework on real-life HPC applications. -\end{itemize} - - -\par +\begin{description} + \item[SOCLIB] + The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories + and 6 industrial companies. + It supports system level virtual prototyping of shared memory, multi-processors + architectures, and provides tools to map multi-tasks software application on these + architectures, for reliable performance evaluation. + The core of this platform is a library of SystemC simulation models for + general purpose IP cores such as processors, buses, networks, memories, IO controller. + The platform provides also embedded operating systems and software/hardware + communication middleware. + The synthesisable VHDL models of IPs are not part of the SoCLib platform, and + this project enhances SoCLib by providing the synthesisable VHDL models required + for FPGA synthesis. + \item[ROMA] + The ROMA ANR project (2007-2009) involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a + reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its + computing structure to computation patterns that can be speed-up and/or power efficient. + The ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable + operators to avoid traditional overhead, in reconfigurable devices, related to + the interconnection network. + The project will borrow from the ROMA ANR xxproject (2007-2009) and the ongoing + joint INRIA-STMicro Nano2012 project to adapt existing pattern + extraction algorithms and datapath merging techniques to the synthesis of customized + ASIP processors. + \item[TSAR] + The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the \upmc targets the design of a + scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib + plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL + models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect). + \item[BioWic] + On the HPC application side, we also hope to benefit from the experience in + hardware acceleration of bioinformatic algorithms/workfows gathered by the + CAIRN group in the context of the ANR BioWic project (2009-2011), so as to + be able to validate the framework on real-life HPC applications. +\end{description} +%%% +\parlf The laboratories involved in the COACH project have a well estabished expertise in the following domains: \begin{itemize} -\item -In the field of High Level Synthesis (HLS), the project -leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project -developped by the Lab-STIC laboratory, and with the UGH~\cite{ugh08} project developped -by the LIP6 and TIMA laboratories. + \item + In the field of High Level Synthesis (HLS), the project + leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project + developped by the \ubs laboratory, and with the UGH~\cite{ugh08} project developped + by the \upmc and \tima laboratories. + \item + Regarding system level architecture, the project is based on the know-how + acquired by the \upmc and \tima laboratories in the framework of various projects + (COSY~\cite{disydent}, or MEDEA-MESA~\cite{dspin}), in the field of communication + architectures for shared memory multi-processors systems. + As an example, the DSPIN network on chip, is now used by BULL in the TSAR project. + \item + Regarding Application Specific Instruction Processor (ASIP) design, the + CAIRN group at INRIA Bretagne Atlantique benefits from several years of + expertise in the domain of retargetable compiler + (Armor/Calife~\cite{CODES99} since 1996, and the Gecos + compilers~\cite{ASAP05} since 2002). \item -Regarding system level architecture, the project is based on the know-how -acquired by the LIP6 and TIMA laboratories in the framework of various projects -(COSY \cite{disydent}, or MEDEA MESA \cite{dspin}), in the field of communication -architectures for shared memory multi-processors systems. -As an example, the DSPIN network on chip, is now used by BULL in the TSAR project. -\item -Regarding Application Specific Instruction Processor (ASIP) design, the -CAIRN group at INRIA Bretagne Atlantique benefits from several years of -expertise in the domain of retargetable compiler -(Armor/Calife\cite{CODES99} since 1996, and the Gecos -compilers\cite{ASAP05} since 2002). -\item -In the field of compilers, the Compsys group was founded in 2002 -by several senior researchers with experience in -high performance computing and automatic parallelization. They have been -among the initiators of the polyhedral model, a theory which serve to -unify many parallelism detection and exploitation techniques for regular -programs. It is expected that the techniques developped by Compsys for -parallelism detection, scheduling, process construction and memory management -will be very useful as a Rfront end for the a high-level synthesis tools. + In the field of compilers, the Compsys group was founded in 2002 + by several senior researchers with experience in + high performance computing and automatic parallelization. They have been + among the initiators of the polyhedral model, a theory which serve to + unify many parallelism detection and exploitation techniques for regular + programs. It is expected that the techniques developped by Compsys for + parallelism detection, scheduling, process construction and memory management + will be very useful as a front-end for the a high-level synthesis tools. \end{itemize} - - -\par -% FIXME A VERIFIER L'appel d'offre +%%% +\parlf Finally, it is worth to note that this project cover priorities defined by the commission experts in the field of Information Technolgies Society (IST) for Embedded @@ -115,4 +112,2 @@ considering resources constraints (delais, power, memory, etc.), security and quality services$>>$. - - Index: /anr/section-2.tex =================================================================== --- /anr/section-2.tex (revision 98) +++ /anr/section-2.tex (revision 99) @@ -1,24 +1,22 @@ -The first objective of COACH is to provide SMEs (Small and Medium Enterprises) an open-source framework to -design embedded system on FPGA devices. - +Embedded systems (SoC and MPSoC) became an inevitable evolution in microelectronic industry. Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit) -is not an option for most SMEs. Fortunately, the new FPGA (Field Programmable Gate Array) components, -such as the Virtex5 family from Xilinx, or the Stratix4 family from Altera can implement a complete -multi-processor architecture on a single chip. - -%But the design of a SoC (System on Chip) or MPSoC (Multi-Processor System on Chip) is a complex -%task, requiring adequate design methods to efficiently model, explore, and analyze the -%interactions between the software application and the hardware architectures. Moreover, most SMEs do not have -%in-home expertise in the field of hardware design or VHDL/Verilog modeling. -%In order to meet the increasing performance requirements, to decrease the development cost, and to -%shorten the time-to-market, they need new design methodologies. - +is not an option for SMEs (Small and Medium Enterprises). +Fortunately, the new FPGA (Field Programmable Gate Array) components, +such as the Virtex5 family from \xilinx, or the Stratix4 family from \altera can implement a complete +multi-processor architecture on a single device. +But the design of embedded system is a long and complex task that requires expertise in software, +software/hardware partionning, operating system, hardware design, VHDL/Verilog modeling. +Only very few SMEs have these multiple expertises and are present on the embedded system market. +\begin{center}\begin{minipage}{.8\linewidth}\textit{ +The major objective of COACH is to provide to SMEs an open-source framework to design +embedded systems on FPGA devices. +}\end{minipage}\end{center} %Current design methodologies provide quite low-level abstraction capabilities, and %there is an urgent need to leverage system level exploration through the use of a high-level %specification of the application and design space exploration tools. - %The first system oriented approaches are appearing, among which those %based on C/C++ and SystemC are the most popular, but few of them are specifically targetting FPGAs. - +%%% +\parlf The COACH project will leverage on the expertise gained in the field of virtual prototyping with the SoCLib platform, to propose a new design flow based on a small number of architectural templates. @@ -29,18 +27,17 @@ template can be enriched by dedicated hardware coprocessors, obtained by high level synthesis (HLS) tools. During this project, the COACH partners will develop three different architectural templates: - \begin{enumerate} \item An \altera architectural template based on the \altera IP core library and the AVALON system bus. -\item A \xilinx architectural template based on the Xlinx IP core library and the OPB system bus. -\item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP communication infrastructure. +\item A \xilinx architectural template based on the \xilinx IP core library and the PLB system bus. +\item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP + communication infrastructure. \end{enumerate} - The proposed design flow starts from a high level description of the application, specified as a set of parallel tasks written in C, without any assumption on the hardware or software implementation of these tasks. It let the system -designer in charge of expessing the coarse grain parallelism of the application, gives the designer +designer in charge of expressing the coarse grain parallelism of the application, gives the designer the possibility to explore various mapping of the application on the selected template architecture, and offers a high predictability of results with respect to cost and performance objectives. - +\\ When this interactive, system level, design space exploration is completed (converging to a specific mapping on a specific version of the selected architectural template), the rest of the flow @@ -48,6 +45,6 @@ code for the software running on the embedded processors, and the bit-stream to program the the target FPGA will be automatically generated by the COACH tools. - -\par +% +\parlf The strength of the COACH approach is the strong integration of the high-level synthesis tools in a plat-form based design flow supporting virtual prototyping and design space exploration. @@ -60,6 +57,17 @@ %in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating %those various technologies, and to define the detailed architecture of the proposed design flow. -\par - +%%% +\parlf +In HPC (High Performance Computing), the kind of targeted application is an existing one +running on a PC. +The COACH framework helps designer to accelerate it by migrating critical parts into a +SoC embedded into an FPGA device plugged to the PC PCI/X bus. +\begin{center}\begin{minipage}{.8\linewidth}\textit{ +The second objective of COACH is to extend the framework to HPC. +}\end{minipage}\end{center} +This will allow SMEs to enter HPC market for the applications that are +unadapted to the current GPU based solutions. +%%% +\parlf In summary, the COACH project is clearly oriented toward industry, even if most technology building blocks have been previously developed by academic laboratories. @@ -98,5 +106,5 @@ %Every point of the design space can be implemented on any FPGA component, %as long as it contains the hardware ressources required by the selected architectural template. -%Basically, COACH will support both Altera and Xilinx FPGA families. +%Basically, COACH will support both \altera and \xilinx FPGA families. %\end{itemize} % Index: /anr/section-3.2.tex =================================================================== --- /anr/section-3.2.tex (revision 98) +++ /anr/section-3.2.tex (revision 99) @@ -18,6 +18,6 @@ and a mapping of processes on the platform components. The supported mapping are software (the process runs on a SoC processor), -XXXpeci (the process runs on a SoC processor enhanced with dedicated instructions), -and hardware (the process runs into a coprocessor generated by HLS and plugged on the SoC bus). +ASIP (the process runs on a SoC processor enhanced with dedicated instructions), +and hardware (the process runs into a coprocessor that is generated by HLS and plugged on the SoC bus). \item[Application compilation] Once the SoC description is validated, COACH generates automatically an FPGA bitstream containing the hardware platform with the SoC application software and @@ -76,14 +76,12 @@ %fin de projet. The main result is the framework. It is composed concretely of: -2 HPC communication schemes with their implementation, -5 HLS tools (control dominated HLS, data dominated HLS, Coarse grained HLS, +a communication middleware for HPC, +5 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS, Memory optimisation HLS and ASIP), -3 systemC based virtual prototyping environment extended with synthesizable -RTL IP cores (generic, ALTERA/NIOS/AVALON, XILINX/MICROBLAZE/OPB), +3 architectural templates that are synthesizable and that can be prototyped, one design space exploration tool, -2 operating system (OS). +2 operating systems (DNA/OS and MUTEK. \\ -The framework fonctionality will be demonstrated with XXX-EXAMPLE1, XXX-EXAMPLE2 -and XXX-EXAMPLE3 on 4 archictures (generic/XILINX, generic/ALTERA, -proprietary/XILINX, proprietary/ALTERA). - +The framework fonctionality will be demonstrated with the demonstrators +(see task-7 page~\pageref{task-7}) and the tutorial example (see task-8 +page~\ref{subtask-tutorial}. Index: /anr/section-4.1.tex =================================================================== --- /anr/section-4.1.tex (revision 98) +++ /anr/section-4.1.tex (revision 99) @@ -17,5 +17,5 @@ In figures, the dotted boxes are the softwares or formats that COACH has to provide and to support. -\vspace*{.75ex}\par +\parlf For the system generation presented in figure~\ref{archi-csg}, the conductor is the tool \verb!CSG! (COACH System Generator). Its inputs are a process @@ -35,9 +35,8 @@ FPGA device\footnote{Additional partial bitstreams are generated in case of dynamic partial reconfiguration}. -\\ %To proove CSG that COACH is open and CSG is really configurable, COACH will %basically support 3 architecture template (the COACH template based on a %MIPS processors and a VCI token ring, the Altera template based on the NIOS -%and AVALON bus, the Xilinx template based on the MICROBLAZE and OPB bus) +%and AVALON bus, the Xilinx template based on the MICROBLAZE and PLB bus) %and 2 operating systems (DNA/OS and MUTEK). Furthermore, thus is enforced %by the \mustbecompleted{FIXME:zied} contribution that consists in @@ -46,5 +45,5 @@ %Finally, it is important to notice that this work is a strong %enhancement of the SocLib software. -\vspace*{.75ex}\par +\parlf The software architecture for HAS is presented in figure~\ref{archi-hls}. The input is a single task of the process network. The HAS tools do not work @@ -61,5 +60,5 @@ Furthermore, the back-end tools uses a macro-cell library (functional and memory unit). -\vspace*{.75ex}\par +\parlf In addition to digital system design, HPC requires a supplementary partitioning step presented in figure~\ref{archi-hpc}. The designer @@ -70,22 +69,23 @@ simulator. Once the partitioning is validated, the design of the FPGA part is done through \verb!CSG! (figure~\ref{archi-csg}). -\vspace*{.75ex}\par \mustbecompleted{FIXME == MODIFICATION DE LA FIGURE} -The project is split into 8 tasks numbered from 0 to 7. -The first task (task 0) is the project management, the last one (task 7) is -the dissemination the other task are listed below: -\begin{enumerate} -\item\textbf{\Backbone:} This task tackles the fundamental points of the +\parlf +The project is split into 8 tasks numbered from 1 to 8. There are described +bellow and detailled in section \ref{task-description}. +\begin{description} +\item[Task-1: \textit{Project management}] + This task relies to the monitoring of the COACH project. +\item[Task-2: \textit{\Backbone}] This task tackles the fundamental points of the project such as the defintion of the COACH inputs and outputs, the internal formats (e.g. \xcoach), the architectural templates and the design flow. -\item\textbf{System generation:} This task addresses the prototyping and +\item[task-3: \textit{System generation}] This task addresses the prototyping and the generation of digital system. Apart from HAS that belong to the task 3 and 4, its components are those presented figure~\ref{archi-csg} (e.g. \verb!CSG!, operating systems). -\item\textbf{HAS front-end:} This task mainly focusses on four functionalities: +\item[Task-4: \textit{HAS front-end}] This task mainly focusses on four functionalities: optimization of the memory usage, parallelism enhancement through loop transformations, coarse grain parallelization and ASIP generation. -\item\textbf{HAS back-end:} This task groups two functionalities: +\item[Task-5: \textit{HAS back-end}] This task groups two functionalities: High-Level Synthesis of data dominated description and HLS of control dominated description. @@ -93,13 +93,21 @@ that will allow the coprocessors to respect the processor \& the bus frequency. -\item\textbf{Communication between PC \& FPGA-SoC:} +\item[Task-6: \textit{PC/FPGA communication middleware}] This task pools the features dedicated to HPC. The main are the partitioning validation (see figure~\ref{archi-hpc}), the sytem drivers for both PC and FPGA-SoC sides, the hardware communication components and support for dynamic partial reconfiguration. -\item\textbf{Demonstrators:} +\item[Task-7: \textit{Industrial demonstrators}] This task groups the demonstrators of the COACH project. - \mustbecompleted{FIXME} -\end{enumerate} + Most of them are industrial applications that will be developped with the COACH + framework. + Others consist in integrating COACH framework as a driver of industrial proprietary + design tools. +\item{Task 8: \textit{Dissemination}} + This task relies to the diffusion of the project results. + It mainly consists of the production of 4 COACH releases (\verb!T0+12!, \verb!T0+18!, + \verb!T0+24! and \verb!T0+36!) + and the publication on a WEB site of a tutorial. +\end{description} % \begin{figure}\leavevmode\center @@ -109,28 +117,28 @@ \end{figure} Figure~\ref{dependence-task} presents the tasks dependencies. -"$task-N \longrightarrow task-M$" means that $task-N$ impacts the $task-M$. +"$T_N \longrightarrow T_M$" means that $T_N$ impacts the $T_M$. The more bold is the arrow, the more important is the dependency. The graph shows: \begin{itemize} -\item Even that $T3$ and $T4$ functionalities are complementary, their +\item Even that $T4$ and $T5$ functionalities are complementary, their developments are independent (thanks to \xcoach internal format). -\item $T2$ slightly depends on $T3$ and $T4$. Indeed, $T2$ may works -without $T3$ and $T4$ if we limit to digital systems without hardware +\item $T3$ slightly depends on $T4$ and $T5$. Indeed, $T3$ may works +without $T4$ and $T5$ if we limit to digital systems without hardware accellerators. -\item $T2$ strongly impacts on $T5$ but, $T2$ does not depend at all on -$T5$. So demonstrators ($T6$) of embedded system would not be impacted if -$T5$ would fail. -\item $T1$ drives all the tasks ($T2$, $T3$, $T4$, $T5$) at the heart of +\item $T3$ strongly impacts on $T6$ but, $T3$ does not depend at all on +$T6$. So demonstrators ($T7$) of embedded system would not be impacted if +$T6$ would fail. +\item $T2$ drives all the tasks ($T3$, $T4$, $T5$, $T6$) at the heart of the COACH project. -\item The demonstrators developped in $T6$, of course, strongly depends on the achievements -of the prvious tasks ($T1$, $T2$, $T3$, $T4$, $T5$). -\item $T7$ and $T0$ respectively depends on and impacts all the other tasks. +\item The demonstrators developped in $T7$, of course, strongly depends on the achievements +of the prvious tasks ($T2$, $T3$, $T4$, $T5$, $T6$). +\item $T8$ and $T1$ respectively depends on and impacts all the other tasks. \end{itemize} This organisation offers enough robustness to insure the success of the -project except for the specification task $T1$. - -The only critical task in this chart is T1. \label{xcoach-problem} +project except for the specification task $T2$. +\\ +The only critical task in this chart is $T2$. \label{xcoach-problem} However, the partners met 10 times (a one day meeting per month) during the last year to prepare the specification and the project proposal. This gives us a degree of confidence -that T1 will be completed in time. +that $T2$ will be completed in time. Index: /anr/section-6.1.tex =================================================================== --- /anr/section-6.1.tex (revision 98) +++ /anr/section-6.1.tex (revision 99) @@ -90,13 +90,15 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{\upmc} + University Pierre et Marie Curie (UPMC) is the largest university in France (7400 employees,38000 students). The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of UPMC, hosting more than 400 researchers, under the umbrella of the CNRS (Centre National de la Recherche Scientifique). -The ï¿œ System on Chip ï¿œ Department of LIP6 consists of 80 people, including 40 PHD students. +The \og System on Chip \fg Department of LIP6 consists of 80 people, including 40 PHD students. The research focus on CAD tools and methods for VLSI and System on Chip design. -\\ +\parlf The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts. The SoC department has been involved in several european projects :IDPS, EVEREST, OMI-HIC, OMI-MACRAME, OMI-ARCHES, EUROPRO, COSY, Medea SMT, Medea MESA, Medea+ BDREAMS, Medea+ TSAR. +\parlf The public domain VLSI CAD system ALLIANCE, developped at UPMC is installed in more than 200 universities worldwide. The LIP6 is in charge of the technical coordination of the SoCLib national project, and is hosting @@ -110,4 +112,5 @@ of control-dominated coprocessors. This tool will be modified to be integrated in the Coach design flow. +\parlf Even if the preferred dissemination policy for the Coach design flow will be the free software policy, (following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies @@ -115,12 +118,57 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\altera} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{\xilinx} +\xilinx is the world leader in the domain of programmable logic circuits (FPGA). +\xilinx develops in one hand several FPGA architectures (CoolRunner, Spartan and Virtex +families) and in the other hand a software solution allowing exploiting the +characteristics of these FPGA. +\parlf +The tools proposed can allow the designer to describe his architecture from modeling +language (VHDL/Verilog) to an optimized architecture implemented to the selected +technology. +The team located at Grenoble is responsible of the logic synthesis tool development (XST) +of the software solution, which aggregates all the steps allowing proceeding from a HDL +model to a technological netlist: +\begin{itemize} + \item Compilation of HDL code and model generation at Register Transfer Level (RTL). + \item RTL model optimizations. + \item Inference and generation of optimized macro blocks (Finite states machine, counter). + \item Boolean equations generation for randomly logic. + \item Logical, mapping and timing optimizations. +\end{itemize} +\parlf +The architectures developed by \xilinx offer a collection of technological primitives +(variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory +and whether configurable processor cores (Pico and MicroBlaze families). +This kind of architecture allows, thus, the designer to validate different +hardware/software possibilities in a High Level Synthesis (HLS) framework. +\parlf +The classical optimization techniques focus, mainly, on the frequency aspects and on +available resources use. +The optimizations, taking into account the consumption criteria, become critical due to +the fact of the increase of the architecture complexity and due to the use of FPGA +component for low power applications. + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{\bull} +\bull designs and develops servers and software for an open environment, integrating the +most advanced technologies. It brings to its customers its expertise and know-how to help +them in the transformation of their information systems and to optimize their IT +infrastructure and their applications. +\parlf +\bull is particularly present in the public sector, banking, finance, telecommunication +and industry sectors. Capitalizing on its wide experience, the Group has a thorough +understanding of the business and specific processes of these sectors, thus enabling it to +efficiently advise and to accompany its customers. Its distribution network spreads to +over 100 countries worldwide. +\parlf +The team participating to the COACH project is from the Server Development Department +based in Les Clayes-sous-Bois, France. The SD Department is in charge of developing +hardware for open servers (e.g. NovaScale) and HPC solutions. Its main activities range +from architecture specification, ASIC design/verification/prototyping to board design and +include also specific EDA development to complement standard tools. + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{\thales} @@ -132,2 +180,36 @@ \subsubsection{\navtel} +\navtel was created in 1994 to develop flexible systems based on FPGAs and currently +focuses on intelligent signal mining for knowlege based signal processing systems. +The company main activity covers the following domains: satellite communication, +aeronautics, imaging and security. +\navtel dedicates about 70\% of its activity to client projects in satellite, aeronautical +and imaging systems and 30\% to its own research programmes in collaboration with French +and international partners. +\parlf +The multi disciplinary technical team comprises 6 engineers for signal processing and +hardware development and one technician. +\parlf +\navtel has its own Ph.D program which includes in the past (classification technology +and MIMO for FPGA implementation) and currently the preparation of a project for remote +sensing with signal intelligence for satellite application. The company participates in +national and European level projects contributing to a strategic alliance between academic +and industrial partners.\\ +The current research covers particle filter applications for communication and RADAR, +Cognitive Radio, Satellite communication, embedded super computing and focuses on low +power algorithms for implementation in FPGA and soft computing. +\parlf +For manufacturing and industrialization, \navtel works with ISO certified partners. +The company clients include the CNES, ThalÚs Alenia Space, ThalÚs Communication, EADS, +Eutelsat, AIRBUS, Schlumberger. \navtel participates from the R\&D phase through to the +system delivery. + +\begin{description} +\item[Recognitions:]\mbox{} +\begin{itemize} + \item EC Challenge+ programme for innovative projects (promotion 9) + \item Innovation and technology development \og Troph\'{e}es R\'{e}gion Centre \fg + \item Recognition by the French Senate for company creation during the + \og Semaine de l'entrepreneur \fg 2005. +\end{itemize} +\end{description} Index: /anr/section-7.tex =================================================================== --- /anr/section-7.tex (revision 98) +++ /anr/section-7.tex (revision 99) @@ -31,4 +31,5 @@ costs. The requested funding for non permanent personnels is 100\% of the total ANR requested funding. + \begin{center}\input{table_lip_short.tex}\end{center} \item [Subcontracting] @@ -41,5 +42,4 @@ The costs justified by internal invoicing procedures are evaluated to 4\% of the total requested ANR funding.\\ - \begin{center}\input{table_lip_short.tex}\end{center} \end{description} @@ -74,4 +74,5 @@ The requested funding for non permanent personnels is 82\% of the total ANR requested funding. +\begin{center}\input{table_tima_short.tex}\end{center} \item [Subcontracting] No subcontracting costs. @@ -83,43 +84,38 @@ The costs justified by internal invoicing procedures are evaluated to 4\% of the total requested ANR funding.\\ - \begin{center}\input{table_tima_short.tex}\end{center} -%FIXME comment on rajoute les hommes-ans sur le WP7 pour la dissemination ? \end{description} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Partner 4: \ubs} +\begin{figure}\leavevmode\center +\input{table_ubs_full.tex} +\caption{\label{ress-detail-ubs}Man power in $mm$ for the delivrables of \ubs.} +\end{figure} \begin {description} \item [Equipment] -\par In order to validate the design flow project, the LabSTICC laboratory will buy FPGA developpement boards. The cost for these FPGA boards is estimated to 3\% of the total ANR funding. \item [Personnel costs] -\par The faculty members involved in the project are associate professors (Philippe COUSSY, Cyrille CHAVET) or research ingeneers (Dominique HELLER). All non-permanent personnel costs are estimated in men*months for senior researchers (post-doc or research engineers). + The table below sumarizes the man power by task for both permanent and non-permanent -personnels. The detail by delivrables is given in figure~\ref {detail-lip6}. +personnels. The detail by delivrables is given in figure~\ref {ress-detail-ubs}. The non-permanent personnels costs represent 50\% of the personnal costs. The requested funding for non permanent personnels is about 83\% of the total ANR requested funding. +\begin{center}\input{table_ubs_short.tex}\end{center} \item [Subcontracting] -\par No subcontracting costs. \item [Travel] -\par The travel costs are associated to management and meeting as well as participation to conferences. The travel costs are estimated to 10\% of the total requested ANR funding. \item [Expenses for inward billing] -\par The costs justified by internal invoicing procedures are evaluated to 4\% of the total requested ANR funding. -\mustbecompleted{FIXME: LIP6 :: Comment peut-on modifier automatiquement le contenu du tableau (sans modifier directement le -fichier)} -\\ -%\input{table_ubs.tex} \end {description} @@ -160,25 +156,42 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 6: \altera} +\subsection{Partner 6: \xilinx} +\ressourcehelp +\begin{figure}\leavevmode\center +\input{table_xilinx_full.tex} +\caption{\label{ress-detail-xilinx}Man power in $mm$ for the delivrables of \xilinx.} +\end{figure} +\begin{description} +\item[Equipment] + No specific equipment acquisition is required for this project. +\item[Personnel costs] + \xilinx employees involved in the project are permanent Software Engineers. + The detail by delivrables is given in figure~\ref{ress-detail-xilinx} and + summarizes by task in the following table. + \begin{center}\input{table_xilinx_short.tex}\end{center} +\item[Subcontracting] + No subcontracting costs. +\item[Travel] + The travel costs are associated to project meeting as well as participation to + conferences. The travel costs are estimated to + \mustbecompleted{FIXME:\xilinx: XX\%} of the total requested ANR funding. +\item[Expenses for inward billing] none +\item[Other working costs] none +\end{description} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Partner 7: \bull} \ressourcehelp %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 7: \xilinx} +\subsection{Partner 8: \thales} \ressourcehelp %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 8: \bull} +\subsection{Partner 9: \zied} \ressourcehelp %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 9: \thales} +\subsection{Partner 10: \navtel} \ressourcehelp -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 10: \zied} -\ressourcehelp - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 11: \navtel} -\ressourcehelp - Index: /anr/task-7.tex =================================================================== --- /anr/task-7.tex (revision 98) +++ /anr/task-7.tex (revision 99) @@ -38,5 +38,7 @@ \CoutHorsD{6}{36}{\Stima}{dissemination}{0:2:2} \end{livrable} -\item This \ST consists of making a COACH tutorial and to publish it on the public WEB +\item + \label{subtask-tutorial} + This \ST consists of making a COACH tutorial and to publish it on the public WEB site. The tutorial example will also be used as reference demonstrator of the framework.