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• .project (added)
• .texlipse (added)
• anr.tex (modified) (1 diff)
• body.tex (modified) (18 diffs)
• coach_irisa.bib (added)
• flow.eps (added)
• flow.pdf (added)

/anr/anr.tex

@@ -10 +10 @@
 \usepackage{xmpmulti}
 \usepackage{graphicx}
+\usepackage{color}
+
+\definecolor{gris25}{gray}{0.75}
+\definecolor{gris75}{gray}{0.30}
 
 \title{%
 \textbf{COACH:}
 \textbf{C}onception d'\textbf{A}rchitecture par
-\textbf{C}ompilation et synt\textbf{H}èse
+\textbf{C}ompilation et synt\textbf{H}ï¿œse
 }
 

/anr/body.tex

@@ -2 +2 @@
 \hspace{2cm}\begin{scriptsize}\begin{verbatim}
 % 1.    CONTEXTE ET POSITIONNEMENT DU PROJET
-% (1 page maximum) Présentation générale du problème qu'il est proposé de traiter 
+% (1 page maximum) Prￜsentation gￜnￜrale du problￜme qu'il est proposￜ de traiter 
 % dans le projet et du cadre de travail (recherche fondamentale, industrielle ou 
-% développement expérimental).
+% dï¿œveloppement expï¿œrimental).
 \end{verbatim}
 \end{scriptsize}
@@ -19 +19 @@
 due to the design and fabrication costs.
 Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx and Stratix4 from Altera, 
-can implement a SoC with multiple processors and several coprocessors for less than 10K euros the piece.
-In addition, High Level Synthesis (HLS) becomes more mature and allows to automize design 
-and to decrease drastically its cost in terms of man power. Thus, both FPGA and HLS tends to spread over 
-HPC for small companies targeting low volume markets.
+can implement a SoC with multiple processors and several coprocessors for less than 10K euros
+per item. In addition, High Level Synthesis (HLS) becomes more mature and allows to automate 
+design and to drastically decrease its cost in terms of man power. Thus, both FPGA and HLS 
+tend to spread over HPC for small companies targeting low volume markets.
 \par
 To get an efficient embedded system, designer has to take into account application characteristics when it 
@@ -75 +75 @@
 % 1.1.  CONTEXTE ET ENJEUX ECONOMIQUES ET SOCIETAUX 
 % (2 pages maximum)
-% Décrire le contexte économique, social, réglementaire. dans lequel se situe 
-% le projet en présentant une analyse des enjeux sociaux, économiques, environnementaux, 
-% industriels. Donner si possible des arguments chiffrés, par exemple, pertinence et 
-% portée du projet par rapport à la demande économique (analyse du marché, analyse des 
-% tendances), analyse de la concurrence, indicateurs de réduction de coûts, perspectives 
-% de marchés (champs d'application, .). Indicateurs des gains environnementaux, cycle 
+% Dï¿œcrire le contexte ï¿œconomique, social, rï¿œglementaire. dans lequel se situe 
+% le projet en prï¿œsentant une analyse des enjeux sociaux, ï¿œconomiques, environnementaux, 
+% industriels. Donner si possible des arguments chiffrï¿œs, par exemple, pertinence et 
+% portￜe du projet par rapport ￜ la demande ￜconomique (analyse du marchￜ, analyse des 
+% tendances), analyse de la concurrence, indicateurs de rï¿œduction de coï¿œts, perspectives 
+% de marchï¿œs (champs d'application, .). Indicateurs des gains environnementaux, cycle 
 % de vie.
 \end{verbatim}
@@ -111 +111 @@
 various application domains. The ``high end'' lines concern only FPGA with high logic capacity able 
 to implement complex systems. 
-This market is in significant expansion and is estimated to 914 M\$ in 2012.
+This market is in significant expansion and is estimated to 914\,M\$ in 2012.
 Using FPGA limits the NRE costs to design cost. This boosts the developpment of methodologies
 and tools to automize design and reduce its cost.
@@ -140 +140 @@
 segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC 
 emulation and prototyping, Mil/aero etc. HPC market size is estimated today by FPGA providers 
-to 214 M\$. 
+to 214\,M\$. 
 This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion 
 of FPGA-based solutions is limited by the flow automation. Nowadays, there are neither commercial 
@@ -149 +149 @@
 a synthesized netlist, simulation test bench and custom software library that reflect the hardware 
 configuration.
-Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to 
+Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I
+(Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to
 simulate the platform at a high design level (system C). 
 In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation
@@ -163 +164 @@
 However, this tool targets only DSP based algorithms.
 \\
-Consequently, designer developping an embedded system needs to master for example
+Consequently, designers developping an embedded system needs to master for example
 SoCLib for design exploration,
 SOPC Builde at the platform level, 
@@ -169 +170 @@
 and Quartus for design implementation.
 This requires an important tools interfacing effort and makes the design process very complex 
-and achievable only by designers skilled in various domains.
+and achievable only by designers skilled in many domains.
 COACH project integrates all these tools in the same framework masking them to the user. 
 The objective is to allow \textbf{pure software} developpers to realize embedded systems.
@@ -188 +189 @@
 % 1.2.  POSITIONNEMENT DU PROJET
 % (2 pages maximum)
-% Préciser :
-% -     positionnement du projet par rapport au contexte développé précédemment : 
-%   vis- à-vis des projets et recherches concurrents, complémentaires ou antérieurs, 
+% Prï¿œciser :
+% -     positionnement du projet par rapport au contexte dￜveloppￜ prￜcￜdemment : 
+%   vis- ￜ-vis des projets et recherches concurrents, complￜmentaires ou antￜrieurs, 
 %   des brevets et standards.
-% - positionnement du projet par rapport aux axes thématiques de l'appel à projets.
-% - positionnement du projet aux niveaux européen et international.
+% - positionnement du projet par rapport aux axes thￜmatiques de l'appel ￜ projets.
+% - positionnement du projet aux niveaux europï¿œen et international.
 \end{verbatim}
 \end{scriptsize}
@@ -203 +204 @@
 \\% IRISA
 The project will also borrow from the ROMA ANR project (2007-2009) and the ongoing 
-joint INRIA-STMicro Nano2012 project.  In particular we will adapt 
-existing pattern extraction algorithms and datapath merging techniques to the synthesis of customized 
+joint INRIA-STMicro Nano2012 project. In particular we will adapt existing pattern 
+extraction algorithms and datapath merging techniques to the synthesis of customized 
 ASIP processors.
+\\
+\textcolor{gris75}{Steven : Je propose de rajouter un lien avec le projet BioWic~:~on the HPC
+application side, we also hope to benefit from the experience in hardware acceleration of
+bioinformatic algorithms/workfows gathered by the CAIRN group in the context of the ANR
+BioWic project (2009-2011), so as to be able to validate the framework on 
+real-life HPC applications.}
+
 \par
 %%% 1 -- POUVEZ VOUS CHACUN AJOUTER SVP (SI POSSIBLE) UNE LIGNE
 %%% 1 -- REFERANT UN PROJET ANR OU EUROPEEN
-%%% 1 -- Projets européens ou ANR réutilisés ou continués
+%%% 1 -- Projets europï¿œens ou ANR rï¿œutilisï¿œs ou continuï¿œs
 %%% 1 LIP6/TIMA/LAB-STIC OK
 Regarding the expertise in  High Level Synthesis (HLS), the project leverages on know-how acquired over 15 years
@@ -220 +228 @@
 Atlantique benefits from several years of expertise in the domain of retargetable compiler (Armor/Calife
 since 1996, and the Gecos compilers since 2002).
+
+
 % LIP FIXME:UN:PEU:LONG ET HORS:SUJET
 %CA% The source-level transformations required by the HLS tools will be
@@ -290 +300 @@
 \hspace{2cm}\begin{scriptsize}\begin{verbatim}
 % 2.    DESCRIPTION SCIENTIFIQUE ET TECHNIQUE
-% 2.1.  ÉTAT DE L'ART
+% 2.1.  ï¿œTAT DE L'ART
 % (3 pages maximum)
-% Décrire le contexte et les enjeux scientifiques dans lequel se situe le projet 
-% en présentant un état de l'art national et international dressant l'état des 
-% connaissances sur le sujet. Faire apparaître d'éventuels résultats préliminaires. 
-% Inclure les références bibliographiques nécessaires en annexe 7.1.
+% Dï¿œcrire le contexte et les enjeux scientifiques dans lequel se situe le projet 
+% en prï¿œsentant un ï¿œtat de l'art national et international dressant l'ï¿œtat des 
+% connaissances sur le sujet. Faire apparaï¿œtre d'ï¿œventuels rï¿œsultats prï¿œliminaires. 
+% Inclure les rï¿œfï¿œrences bibliographiques nï¿œcessaires en annexe 7.1.
 \end{verbatim}
 \end{scriptsize}
@@ -398 +408 @@
 
 \subsubsection{Application Specific Instruction Processors}
-ASIP (Application-Specific Instruction-Set Processor) are programmable 
-processors in which both the instruction and the micro architecture have 
-been tailored to a given application domain (eg. video processing), or 
-in some extreme cases to a specific application (eg H264 specific ASIP). 
-This processor specialization usually offers a good compromise between 
-performance (compared to a pure software implementation on a COTS 
-embeded processor) and flexibility (compared to an application specific 
+
+ASIP (Application-Specific Instruction-Set Processor) are programmable processors in 
+which both the instruction and the micro architecture have been tailored to a given
+ application domain (eg. video processing), or to a specific application. 
+This specialization usually offers a good compromise between performance (w.r.t a pure software
+implementation on an embeded CPU) and flexibility (w.r.t an application specific 
 hardware co-processor).
-\\
-As a consequence, this type of architecture is a very attractive choice 
-as a System on chip building block. In spite of their obvious 
-advantages, using/designing ASIPs remains a difficult task, since it
-involves designing both an efficient micro-architecture and implementing 
-an efficient compiler for this
-specific micro-architecture.
-\\
-Recently, the use of instruction set extensions has received a lot of 
-interest from the embedded systems design community [NIOS2,FSL,ST70], 
-since it allows to rely on a template micro-architecture in which only a 
-small fraction of the architecture has to be specialized. Even if such 
-an approach offers less flexiblity and forbids very tight coupling 
-between the extensions and the template micro-architecture, it makes the 
-design of the micro-architecture more tractable and amenable to a fully 
-automated flow.
-\\
-However, to our knowledge, there is still no available open-source 
-design flow addressing those two design challenges together, either 
-because the target architecture is proprietary, or because the compiler 
-technology is closed/commercial.
-\\
-In the context of the COACH project, we propose to add to the 
-infra-structure a design flow targeted to automatic instruction set 
-extension for the MIPS-based CPU, which will come as a complement or an 
-alternative to the other proposed approaches (hardware accelerator, 
-multi processors).
+In spite of their obvious advantages, using/designing ASIPs remains a difficult
+task, since it involves designing both a micro-architecture and a compiler for this
+architecture. Besides, to our knowledge, there is still no available open-source
+design flow\footnote{There are commercial tools such a } for ASIP design even if such a tool would
+be valuable in the context of a System Level design exploration tool.    
+
+In this context, ASIP design based on Instruction Set Extensions (ISEs) has 
+received a lot of interest [NIOSII,TENSILICA]%~\cite{NIOS2,ST70}, 
+as it makes micro architecture synthesis 
+more tractable \footnote{ISEs rely on a template micro-architecture in which 
+only a small fraction of the architecture has to be specialized}, and help ASIP
+designers to focus on compilers, for which there are still many open problems 
+[CODES04,FPGA08].
+This approach however has a strong weakness, since it also significantly reduces 
+opportunities for achieving good seedups (most speedup remain between 1.5x and 
+2.5x), since ISEs performance is generally tied down by I/O constraints as 
+they generally rely on the main CPU register file to access data.
+
+% (
+%automaticcaly extraction ISE candidates for application code \cite{CODES04}, 
+%performing efficient instruction selection and/or storage resource (register) 
+%allocation \cite{FPGA08}).  
+ 
+
+To cope with this issue, recent approaches~[DAC09,DAC08]%\cite{DAC09,DAC08} 
+advocate the use of 
+micro-architectural ISE models in which the coupling between the processor micro-architecture
+and the ISE component is thightened up so as to allow the ISE to overcome the register 
+I/O limitations, however these approaches tackle the problem for a compiler/simulation 
+point of view and not address the problem of generating synthesizable representations for 
+these models. 
+
+We therefore strongly believe that there is a need for an open-framework which
+would allow researchers and system designers to :
+\begin{itemize}
+\item Explore the various level of interactions between the original CPU micro-architecure
+and its extension (for example throught a Domain Specific Language targeted at micro-architecture
+specification and synthesis).
+\item Retarget the compiler instruction-selection (or prototype nex passes) passes so as
+to be able to take advantage of this ISEs.
+\item Provide  a complete System-level Integration for using ASIP as SoC building blocks 
+(integration with application specific blocks, MPSoc, etc.)
+\end{itemize}
+
+\hspace{2cm}
+\begin{scriptsize}\begin{verbatim} 
+
+[CODES08] Theo Kluter, Philip Brisk, Paolo Ienne, and Edoardo Charbon, Speculative DMA for
+Architecturally Visible Storage in Instruction Set Extensions
+
+[DAC09] Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon, Way Stealing: Cache-assisted
+Automatic Instruction Set Extensions.
+
+[CODES04] Pan Yu, Tulika Mitra, Scalable Custom Instructions Identification for
+Instruction Set Extensible Processors.
+
+[FPGA08] Quang Dinh, Deming Chen, Martin D. F. Wong, Efficient ASIP Design for Configurable
+Processors with Fine-Grained Resource Sharing.
+
+[NIOSII] Nios II Custom Instruction User Guide
+
+\end{verbatim}
+
+\end{scriptsize}
+%, either 
+%because the target architecture is proprietary, or because the compiler 
+%technology is closed/commercial.
+
+
+
+
+% We propose to explore how to tighten the coupling of the extensions and 
+% the underlyoing template micro-architecture.
+% *  Thightne Even if such 
+% an approach offers less flexiblity and forbids very tight coupling 
+% between the extensions and the template micro-architecture, it makes the 
+% design of the micro-architecture more tractable and amenable to a fully 
+% automated flow.
+% \\
+% \\
+% In the context of the COACH project, we propose to add to the 
+% infra-structure a design flow targeted to automatic instruction set 
+% extension for the MIPS-based CPU, which will come as a complement or an 
+% alternative to the other proposed approaches (hardware accelerator, 
+% multi processors).
+% 
 
 \subsubsection{Automatic Parallelization}
@@ -586 +654 @@
 % 2.2.  OBJECTIFS ET CARACTERE AMBITIEUX/NOVATEUR DU PROJET 
 % (2 pages maximum)
-% Décrire les objectifs scientifiques/techniques du projet.
-% Présenter l'avancée scientifique attendue. Préciser l'originalité et le caractère 
+% Dï¿œcrire les objectifs scientifiques/techniques du projet.
+% Prￜsenter l'avancￜe scientifique attendue. Prￜciser l'originalitￜ et le caractￜre 
 % ambitieux du projet.
-% Détailler les verrous scientifiques et techniques à lever par la réalisation du projet.
-% Décrire éventuellement le ou les produits finaux développés à l'issue du projet  
-% montrant le caractère innovant du projet.
-% Présenter les résultats escomptés en proposant si possible des critères de réussite 
-% et d'évaluation adaptés au type de projet, permettant d'évaluer les résultats en 
+% Dￜtailler les verrous scientifiques et techniques ￜ lever par la rￜalisation du projet.
+% Dￜcrire ￜventuellement le ou les produits finaux dￜveloppￜs ￜ l'issue du projet  
+% montrant le caractï¿œre innovant du projet.
+% Prï¿œsenter les rï¿œsultats escomptï¿œs en proposant si possible des critï¿œres de rï¿œussite 
+% et d'ï¿œvaluation adaptï¿œs au type de projet, permettant d'ï¿œvaluer les rï¿œsultats en 
 % fin de projet.
-% Le cas échéant (programmes exigeant la pluridisciplinarité), démontrer l'articulation 
+% Le cas ￜchￜant (programmes exigeant la pluridisciplinaritￜ), dￜmontrer l'articulation 
 % entre les disciplines scientifiques.
 \end{verbatim}
@@ -615 +683 @@
 \item[SoC design] In this phase, 
 The user can obtain simulators at different abstraction levels of the SoC by giving to COACH framework
-a SoC description. 
+a SoC description.  
 This description consists of a process network corresponding to the SoC application, 
 an OS, an instance of a generic hardware platform
@@ -627 +695 @@
 loading the bitstream on FPGA and running the executable on PC.
 \end{description}
-
+ 
 % l'avancee scientifique attendue. Preciser l'originalite et le caractere 
 % ambitieux du projet. 
@@ -691 +759 @@
 %% %3.1.        PROGRAMME SCIENTIFIQUE ET STRUCTURATION DU PROJET 
 %% %(2 pages maximum)
-%% %Présentez le programme scientifique et justifiez la décomposition en tâches du 
-%% %programme de travail en cohérence avec les objectifs poursuivis. 
-%% %Utilisez un diagramme pour présenter les liens entre les différentes tâches 
+%% %Prï¿œsentez le programme scientifique et justifiez la dï¿œcomposition en tï¿œches du 
+%% %programme de travail en cohï¿œrence avec les objectifs poursuivis. 
+%% %Utilisez un diagramme pour prï¿œsenter les liens entre les diffï¿œrentes tï¿œches 
 %% %(organigramme technique)
-%% %Les tâches représentent les grandes phases du projet. Elles sont en nombre limité.
-%% %N'oubliez pas les activités et actions correspondant à la dissémination et à la 
+%% %Les tￜches reprￜsentent les grandes phases du projet. Elles sont en nombre limitￜ.
+%% %N'oubliez pas les activitￜs et actions correspondant ￜ la dissￜmination et ￜ la 
 %% %valorisation.
 %% 
@@ -704 +772 @@
 %% %3.2.        MANAGEMENT DU PROJET
 %% %(2 pages maximum)
-%% %Préciser les aspects organisationnels du projet et les modalités de coordination 
-%% %(si possible individualisation d'une tâche coordination : cf. tâche 0 du document 
+%% %Prï¿œciser les aspects organisationnels du projet et les modalitï¿œs de coordination 
+%% %(si possible individualisation d'une tï¿œche coordination : cf. tï¿œche 0 du document 
 %% %de soumission A).
 %% \subsection{}
 %% %3.3.        DESCRIPTION DES TRAVAUX PAR TACHE
-%% %(idéalement 1 ou 2 pages par tâche)
-%% %Pour chaque tâche, décrire : 
-%% %-   les objectifs  de la tâche et éventuels indicateurs de succès,
-%% %-   le responsable de la tâche et les partenaires impliqués (possibilité de 
+%% %(idï¿œalement 1 ou 2 pages par tï¿œche)
+%% %Pour chaque tï¿œche, dï¿œcrire : 
+%% %-   les objectifs  de la tï¿œche et ï¿œventuels indicateurs de succï¿œs,
+%% %-   le responsable de la tￜche et les partenaires impliquￜs (possibilitￜ de 
 %% %l'indiquer sous forme graphique),
-%% %-   le programme détaillé des travaux par tâche,
-%% %-   les livrables de la tâche,
+%% %-   le programme dￜtaillￜ des travaux par tￜche,
+%% %-   les livrables de la tï¿œche,
 %% %-   les contributions des partenaires (le " qui fait quoi "),
-%% %-   la description des méthodes et des choix techniques et de la manière dont 
-%% %les solutions seront apportées,
-%% %-   les risques de la tâche et les solutions de repli envisagées.
-
-
-
-
-
-
+%% %-   la description des mï¿œthodes et des choix techniques et de la maniï¿œre dont 
+%% %les solutions seront apportï¿œes,
+%% %-   les risques de la tï¿œche et les solutions de repli envisagï¿œes.
+
+
+
+
+
+