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\mustbecompleted {FIXME == AJOUTER LES POINTS QUI SUIVENT sur les 3 axes ???}

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The COACH project answers to several of the challenges found in different axis of the call for proposals. Keywords of the call are indicated below in italic writing.

Axis 1 « Architectures des systèmes embarques » :

COACH will address new embedded systems architectures by allowing the design of  Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design constraints and objectives (real-time, low-power). It will permit to design  complex SoC  based on IP cores ((memory, peripherals, network controllers, communication processors), running Embedded Software, as well as an Operating System with associated middleware and API and using hardware accelerator automatically generated. It will also permit to use efficiently different dynamic system management techniques and re-configuration mechanisms. 

Axis 2 « Infrastructures pour l'Internet, le calcul intensif ou les services » :

COACH will address High-Performance Computing (HPC) by helping designer to accelerate an application running on a PC by migrating critical parts into a SoC implemented on an FPGA plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer effort through the development of tools that translate high level language programs to FPGA configurations. Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance as well as reducing the required area.

Axis 3 « Robotique et contrôle/commande » :
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The COACH proposal addresses directly the \emph{Embedded Systems} item of
the ARPEGE program. It aims to propose solutions to the societal/economical challenges by
providing SMEs novel design capabilities enabling them to increase their
design productivity with design exploration and synthesis methods that are placed on top 
of the state-of-the-art methods.
This project proposes an open-source framework for mapping multi-tasks software applications
on Field Programmable Gate Array circuits (FPGA).
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COACH will contribute to build an open development and run-time
environment, including communication middleware and tools to support
developers in the production of embedded software, through all phases of the software lifecycle,
from requirements analysis until deployment and maintenance.
More specifically, COACH focuses on:
\begin{itemize}
\item High level methods and concepts (esp. requirements and architectural level) for system
design, development and integration, addressing complexity aspects and modularity.
\item Open and modular development environments, enabling flexibility and extensibility by
means of new or sector-specific tools and ensuring consistency and traceability along the
development lifecycle.
\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
environment, suitable for co-operative and distributed development.
\end{itemize}
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COACH outcome will contribute to strengthen Europe's competitive position by developing
technologies and methodologies for product development, focusing (in compliance with the
scope of the above program) on technologies, engineering methodologies, novel tools,
methods which facilitate resource use efficiency. The approaches and tools to be developed 
in COACH will enable new and emerging information technologies for the development,
manufacturing and integration of devices and related software into end-products.
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The COACH project will benefit from a number of previous projects:
\begin{description}
  \item[SOCLIB]
    The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories 
    and 6 industrial companies. 
    It supports system level virtual prototyping of shared memory, multi-processors
    architectures, and provides tools to map multi-tasks software application on these
    architectures, for reliable performance evaluation.
    The core of this platform is a library of SystemC simulation models for 
    general purpose IP cores such as processors, buses, networks, memories, IO controller.
    The platform provides also embedded operating systems and software/hardware
    communication middleware.
    The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
    this project enhances SoCLib by providing the synthesisable VHDL models required
    for FPGA synthesis.
  \item[ROMA]
    The ROMA ANR project (2007-2009) involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a
    reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its
    computing structure to computation patterns that can be speed-up and/or power efficient. 
    The ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable
    operators to avoid traditional overhead, in reconfigurable devices, related to 
    the interconnection network. 
    The project will borrow from the ROMA ANR xxproject (2007-2009) and the ongoing 
    joint INRIA-STMicro Nano2012 project to adapt existing pattern
    extraction algorithms and datapath merging techniques to the synthesis of customized 
    ASIP processors.
  \item[TSAR]
    The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the \upmc targets the design of a 
    scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
    plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL 
    models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
  \item[BioWic]
    On the HPC application side, we also hope to benefit from the experience in
    hardware acceleration of bioinformatic algorithms/workfows gathered by the
    CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
    be able to validate the framework on real-life HPC applications.
\end{description}
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The laboratories involved in the COACH project have a well estabished expertise
in the following domains:
\begin{itemize}
  \item 
    In the field of High Level Synthesis (HLS), the project
    leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
    developped by the \ubs laboratory, and with the UGH~\cite{ugh08} project developped
    by the \upmc and \tima laboratories. 
  \item
    Regarding system level architecture, the project is based on the know-how
    acquired by the \upmc and \tima laboratories in the framework of various projects  
    (COSY~\cite{disydent}, or MEDEA-MESA~\cite{dspin}), in the field of communication 
    architectures for shared memory multi-processors systems.
    As an example, the DSPIN network on chip, is now used by BULL in the TSAR project.
  \item
    Regarding Application Specific Instruction Processor (ASIP) design, the
    CAIRN group at INRIA Bretagne Atlantique benefits from several years of
    expertise in the domain of retargetable compiler
    (Armor/Calife~\cite{CODES99} since 1996, and the Gecos
    compilers~\cite{ASAP05} since 2002).
\item
    In the field of compilers, the Compsys group was founded in 2002 
    by several senior researchers with experience in
    high performance computing and automatic parallelization. They have been
    among the initiators of the polyhedral model, a theory which serve to
    unify many parallelism detection and exploitation techniques for regular
    programs. It is expected that the techniques developped by Compsys for
    parallelism detection, scheduling, process construction and memory management
    will be very useful as a front-end for the a high-level synthesis tools.
\end{itemize}
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Finally, it is worth to note that this project cover priorities defined by the commission 
experts in the field of Information Technolgies Society (IST) for Embedded
Systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity
and allowing to apply efficiently applications and various products on embedded platforms,
considering resources constraints (delais, power, memory, etc.), security and quality
services$>>$.
