\begin{taskinfo}
\let\UPMC\leader
\let\IRISA\enable
\let\TIMA\enable
\let\XILINX\enable
\let\UBS\enable
\end{taskinfo}
%
\begin{objectif}
This task deals with the prototyping and the generation of FPGA-SoC digital systems.
Its is described on figure~\ref{archi-csg}.
Its objective is to allow the system designer to explore the design space by
quickly prototyping and then to automatically generate the FPGA-SoC system.
This task consists of
\begin{itemize}
\item The development of all the missing components (SytemC models and/or synthesizable VHDL models 
of the IP-cores),
\item The configuration and the development of drivers of the operating systems (Board Support Package, HAL),
\item The CSG software that generates the SystemC simulators for prototyping and the FPGA-SoC system
including its bitstream and software executable code,
\item The specification of enhanced communication schemes and their sofware and hardware implementations.
\end{itemize}
This task being based on the SoCLib platform, a first release will be delivered at $T0+12$
to allow the demonstrators to start working.
This release will include the standard communication schemes (base on SoCLib MWMR component)
and support the neutral architectural template for prototyping and hardware generation.
\end{objectif}
%
\begin{workpackage}
\subtask This \ST corresponds to the COACH System Generator (CSG) software.
    \begin{livrable}
    \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
        The first software release of the CSG tool that will allow demonstrators to start
        working by using the neutral architectural template.
    \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
        The second release of CSG supports the \xilinx and \altera architectural
        templates and the enhanced communication system, but only for SystemC prototyping.
        This release integrates a first integration of HLS tools.
    \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
        This milestone extends CSG (\csgPrototypingOnly) to
        FPGA-SoC generation for the \xilinx and \altera architectural template.
    \itemL{24}{36}{x}{\Supmc}{CSG}{6:5.5:5.5}
        Final release of CSG.
    \end{livrable}
\subtask This \ST deals with the components of the architectural templates.
    \\
    For the neutral architectural template, it consists of the development of the VHDL
    synthesizable description of the missing communication components (MWMR)
	in order to support the process network communication model. 
    Notice that the SystemC models
    comes from the SocLib ANR project, the processor with its cache comes from the TSAR
    ANR project.
    \\
    For the \xilinx and \altera architectural templates, we use the \xilinx and \altera IPs (NIOS, Microblaze, memories, busses...).
    \begin{livrable}
    \itemL{0}{12}{h}{\Supmc}{neutral architecture}{1:0:0}
        \setMacroInAuxFile{csgCoachArchTempl}
        The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
    \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0}
       This deliverable consists in optimizing the VHDL descriptions of the components of
       the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the
       \xilinx RTL synthesis tools.
       \upmc will provide the VHDL descriptions, \xilinx will provide back a documentation
       listing that proposes VHDL generation enhancements.
    \itemV{6}{18}{x}{\Stima}{\xilinx architecture}
        \setMacroInAuxFile{csgXilinxSystemC}
        The SystemC simulation module of the MWMR component with a PLB bus interface plus
        the SystemC modules of the components of the \xilinx architectural template
        currently not available in the SocLib component library.
    \itemL{18}{24}{h}{\Stima}{\xilinx architecture}{9:9:0}
        The synthesizable VHDL description of the MWMR component corresponding to the
        SystemC module of the former deliverable (\csgXilinxSystemC).
    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:1.5}
       This deliverable consists in optimizing the MWMR VHDL description (deliverable
       \novers{\csgXilinxSystemC}) of the \xilinx architectural template.
       \tima will provide MWMR VHDL description, \xilinx will provide back a documentation
       listing that proposes VHDL generation enhancements.
    \itemV{6}{18}{x}{\Sirisa}{\altera architecture}
        \setMacroInAuxFile{csgAlteraSystemC}
        The SystemC simulation module of the MWMR component with an AVALON bus interface plus
        the SystemC modules of the components of the \altera architectural template
        currently not available in the SocLib component library.
    \itemL{18}{24}{h}{\Sirisa}{\altera architecture}{6:6:0}
        The synthesizable VHDL description of the MWMR component corresponding to the
        SystemC module of the former deliverable (\csgAlteraSystemC);
    \itemV{6}{12}{d}{\Subs}{UBS communication adapter}{1:0:0}
       \setMacroInAuxFile{gautCOMMoptimization}
       Specification of an optimized communication adapter (space and time) component to handle data interleaving.
       This evolution aims to solve out of order communication weakness of the classical MWMR. 
    \itemV{12}{24}{x}{\Subs}{UBS communication adapter}{0:6:0}
       First release of the tool that generates the VHDL description of the optimized communication adapter
       and its corresponding SystemC module. 
    \itemL{24}{30}{x}{\Subs}{UBS communication adapter}{0:0:2}
       Final release of the tool that generates the VHDL description of the optimized
       communication adapter and its corresponding SystemC module (\gautCOMMoptimization).
    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:1.5}
       This deliverable consists in optimizing the communication adapter VHDL description (deliverable
       \novers{\gautCOMMoptimization}).
       \ubs will provide communication adapter VHDL description, \xilinx will provide back a documentation
       listing that proposes VHDL generation enhancements.
    \end{livrable}
\subtask This \ST consists of the configuration of the SocLib MUTEKH and DNA operating
    system and the development of drivers for the hardware architectural templates
    and enhanced communication schemes defined in \novers{\specCsgManual} deliverable.
    For the \altera and \xilinx architectural templates, the OSs must also be ported on
    the NIOS2 and MICROBLAZE processors.
    \begin{livrable}
    \itemV{6}{8}{x}{\Supmc}{MUTEKH OS}
        The drivers required for the first CSG milestone (deliverable \csgCoachArch).
    \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S}
        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
    \itemL{18}{33}{x}{\Supmc}{MUTEKH OS}{1:1:2}
        Final release of the MUTEKH OS drivers.
    \itemL{6}{18}{x}{\Supmc}{Port of MUTEKH OS}{1.0:1:0}
        Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors.
    \itemV{6}{8}{x}{\Stima}{DNA OS}
        The drivers required for the first CSG milestone (deliverable \csgCoachArch).
    \itemV{8}{18}{x}{\Stima}{DNA 0S}
        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
    \itemL{18}{33}{x}{\Stima}{DNA OS}{6:3:2}
        Final release of the DNA OS drivers.
    \itemL{6}{18}{x}{\Stima}{Port of DNA OS}{3:1:0}
        Porting of DNA OS on the NIOS2 and MICROBLAZE processors.
    \end{livrable}
\end{workpackage}
