An embedded system is an application integrated into one or several chips
in order to accelerate it or to embedd it into a small device such as a personal 
digital assistant (PDA).
This topic is investigated since 80s using Applications Specific Integrated
Circuits (ASIC), Digital Signal Processing (DSP) and parallel computing on
multiprocessor machines or networks.
More recently, since end of 90s, other technologies appeared like Very
Large Instruction Word (VLIW), Application Specific Instruction Processors
(ASIP), System on Chip (SoC), Multi-Processors SoC (MPSoC).
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During these last decades embedded system was reserved to major industrial
companies targeting high volume market due to the design and fabrication
costs.
Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx
and Stratix4 from Altera, can implement a SoC with multiple processors and
several coprocessors for less than 10K euros per item. In addition, High
Level Synthesis (HLS) becomes more mature and allows to automate design and
to drastically decrease its cost in terms of man power. Thus, both FPGA and
HLS tend to spread over HPC for small companies targeting low volume
markets.
\par
To get an efficient embedded system, designer has to take into account
application characteristics when it chooses one of the former technologies.
This choice is not easy and in most cases designer has to try different
technologies to retain the most adapted one.
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The first objective of COACH is to provide an open-source framework to
design embedded system on FPGA device.
COACH framework allows designer to explore various software/hardware
partitions of the target application, to run timing and functional
simulations and to generate automatically both the software and the
synthesizable description of the hardware.
The main topics of the project are:
\begin{itemize} 
\item
Design space exploration: It consists in analysing the application runnig
on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and
hardware/software partitioning of tasks depending on technology choice.
This exploration is driven basically by throughput, latency and power
consumption criteria.
\item
Micro-architectural exploration: When hardware components are required, the
HLS tools of the framework generate them automatically. At this stage the
framework provides various HLS tools allowing the micro-architectural space
design exploration. The exploration criteria are also throughput, latency
and power consumption.
%FIXME:CA
%FIXME:CA At this stage, preliminary source-level transformations will be
%FIXME:CA required to improve the efficiency of the target component.
%FIXME:CA COACH will also provide such facilities, such as automatic parallelization
%FIXME:CA and memory optimisation.
\item
Performance measurement: For each point of design space exploration,
metrics of criteria are available such as throughput, latency, power
consumption, area, memory allocation and data locality. They are evaluated
using virtual prototyping, estimation or analysing methodologies.
\item
Targeted hardware technology: The COACH description of system is
independent of the FPGA family.  Every point of the design exploration
space can be implemented on any FPGA having the required resources.
Basically, COACH handles both Altera and Xilinx FPGA families.
\end{itemize}
As an extension of embedded system design, COACH deals also with High
Performance Computing (HPC).
In HPC, the kind of targeted application is an existing one running on PC.
COACH helps designer to accelerate it by migrating critical parts into a
SoC implemented on a FPGA plugged to the PC bus.
\par
COACH is the result of the will of several laboratory to unify their know
how and skills in the following domains: Operating system and hardware
communication (TIMA, SITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
HLS (LIP6, Lab-STIC and LIP).
The project objective is to integrate these various domains into a unique
free framework (licence ...) masking as much as possible these domains and
its different tools to the user.

