\begin{taskinfo}
\let\UPMC\leader
\let\IRISA\enable
\let\TIMA\ensable
\end{taskinfo}
%
\begin{objectif}
This task relies to the prototyping and the generation of FPGA-SoC digital systems.
Its is described on figure~\ref{arci-csg} and it consists of
Its objective is to allows the system designer to explore the system space design by quickly prototyping and then to generate automatically the FPGA-SoC system.
This task consists of
\begin{itemize}
\item the development of all the missing components (SytemC model and/or synthesizable VHDL description),
\item the configuration and the development of drivers of the operating systems,
\item the CSG software that generates the simulators for prototiping and the FPGA-SoC system,
\item the specification of enhanced communication schem and their sofware and hardware implementation.
\end{itemize}
This task being based on the SocLib platform, a first release will be delivrable at $T0+12$
to allow the demonstrators to start working.
This release will include the standard communication schems (base on SocLib MWMR component)
and support the COACH architectural template for prototyping and hardware generation.
\end{objectif}
%
\begin{workpackage}{T2}
\item This \ST corresponds to the Coach System Generator (DSG) software.
    \begin{livrable}
    \item{-V1}{0}{12}{x}{\upmc}{DSG} The first milestone that will allow demonstrators to
        start working using the COACH hardware architecture template.
    \item{-V2}{0}{24}{x}{\upmc}{DSG} This milestone adds to DSG the support to the Xilinx
        and Altera architectural templates and to the enhanced communication system.
    \item{-VF}{0}{36}{x}{\upmc}{DSG} The final release.
    \end{livrable}
\item This \ST relies to the components of the Coach architectural template.
    \begin{livrable}
    \item{-VF}{0}{12}{x}{\upmc}{COACH architecture} The VHDL synthesizable description
        of the SocLib MWMR, TokenRing.
    \end{livrable}
\item This \ST consists of the configuration of the SocLib Mutek operating system and the
    development of drivers for the hardware architectural template and enhanced
    communication schems.
    \begin{livrable}
    \item{-V1}{0}{12}{x}{\upmc}{Mutek OS} The first milestone required by \ST T2-1-V1.
    \item{-V2}{0}{24}{x}{\upmc}{Mutek 0S} This milestone required by \ST T2-1-V2.
    \item{-VF}{0}{36}{x}{\upmc}{Mutek OS} The final release.
    \end{livrable}
\item This \ST consists of the configuration of the SocLib DNA operating system and the
    development of drivers for the hardware architectural template and enhanced
    communication schems.
    \begin{livrable}
    \item{-V1}{0}{12}{x}{\tima}{DNA OS} The first milestone required by \ST T2-1-V1.
    \item{-V2}{0}{24}{x}{\tima}{DNA 0S} This milestone required by \ST T2-1-V2.
    \item{-VF}{0}{36}{x}{\tima}{DNA OS} The final release.
    \end{livrable}
\item This \ST relies to definition and implementation of the enhanced communication
    schems usable in the definition of communicante task graph.
    \begin{livrable}
    \item{-VF}{0}{6}{d}{\tima}{CSG user manual} A document that describes the CSG task
        graph inputs (task graph, task description, communication schems). 
    \end{livrable}
\item This \ST relies to implementation of the MWMR component for the Xilinx and Altera
    architectural template.
    \begin{livrable}
    \item{-1-VF}{0}{18}{x}{\tima}{MWMR Altera} The VHDL synthesizable description and
        SystemC model of the MWMR with a PLB bus interface.
    \item{-2-VF}{0}{18}{x}{\irisa}{MWMR Altera} The VHDL synthesizable description and
        SystemC model of the MWMR with an AVALON bus interface.
    \end{livrable}
% FIXME:CITI
\end{workpackage}
