\begin{taskinfo}
\let\UBS\leader
\let\UPMC\enable
\let\TIMA\enable
\end{taskinfo}
%
\begin{objectif}
This objectives of this task are to provides the 2 HAS back-ends of the COACH project and
a tool that adapt the coprocessor frequency to the FPGA-SoC frequency. This later is given
by the processors and the BUS.
\\
The HAS back-ends as shown figure~\ref{archi-hls} reads \xcoach data and provides
\xcoachplus data that is \xcoach format annotated with hardware information such as
variable binded on register, operation binded on cell and sheduled. The \xcoach format
being generated by {\specXcoachToC} deliverable and \xcoachplus being treated by
\novers{\specXcoachToSystemC} and \novers{\specXcoachToVhdl} deliverables,
this task is very dependent of the task~1.
\par
For the two HAS front-end, this task is based on the already existing HLS tools GAUT and
tools. These tools are complementary and not competitor because they cover irespectively
data and control dominated orthogonal domain.
The organization of the task is firstly to integrate quickly the existing HLS to the COACH
framework. Secondly these tools will be improved to allows to treat data dominated application
with a few control for GAUT and control dominated application with a few data treatment
for UGH. This will enlarge the domain the HLS can cover.
\end{objectif}
%
\begin{workpackage}{D4}
\item The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It
    consists of suppressing the C commpiler and the SystemC and VHDL drivers and replacing
    them by \xcoach and \xcoachplus drivers.
    \begin{livrable}
    \item{V1}{6}{12}{x}{\Stima}{UGH integration} The UGH software that is able to read
        \xcoach format.
    \item{V2}{12}{18}{x}{\Supmc}{UGH integration} The UGH software that is able to read
        \xcoach format and to write \xcoachplus format.
    \item{VF}{18}{33}{x}{\Supmc}{UGH integration} Maintenance work of the UGH software.
    \end{livrable}
\item The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It
    consists of suppressing the C commpiler and the SystemC and VHDL drivers and replacing
    them by \xcoach and \xcoachplus drivers.
    \begin{livrable}
    \item{V1}{6}{12}{x}{\Stima}{GAUT integration} The GAUT software that is able to read
        \xcoach format.
    \item{VF}{12}{18}{x}{\Stima}{GAUT integration} The GAUT software that is able to read
        \xcoach format and to write \xcoachplus format.
    \end{livrable}
\item The goal of this \ST is to improve the UGH and GAUT HLS tools.
    UGH and GAUT experimentations have shown respectively 2 and \mustbecompleted{FIXME:2}
    usefull enhancements
    \begin{livrable}
    \item{}{18}{24}{x}{\Stima}{UGH enhancement 1} The UGH software whith support for treating
        automatically data dominated sections included into a control dominated application.
    \item{}{21}{27}{x}{\Stima}{UGH enhancement 2} The UGH software that is able to
        generate an micro-architecture without the variable binding currently done by the
        designer.
    \item{}{18}{24}{x}{\Subs}{GAUT enhancement 1} A GAUT excutable that is able to
        \mustbecompleted{FIXME:UBS: ........}.
    \item{}{21}{27}{x}{\Subs}{GAUT enhancement 2} A GAUT excutable that is able to
        \mustbecompleted{FIXME:UBS: ........}.
    \item{}{21}{27}{x}{\Subs}{GAUT enhancement 2} A GAUT excutable that is able to
        \mustbecompleted{FIXME:UBS: ........}.
    \end{livrable}
\item In FPGA-SoC, the frequency is given by the processors and the BUS. The coprocessors
    generated by HLS synthesis must respect this frequency. However, the HLS tools can not
    guarantee that the micro-architectures they generate, respect accurately this
    frequency. This is especially the case when the target is a FPGA device, because the
    delays are really known only after the RTL synthesis and that estimated delays used
    by the HLS are very imprecis. The goal of this \ST is to provide a feature to adapt
    the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL
    synthesis.
    \begin{livrable}
    \item{V1}{0}{6}{d}{\Supmc}{frequency calibration} A document describing the set up of
        the coprocessor frequency calibration.
    \item{V2}{6}{12}{x}{\Supmc}{frequency calibration} A VHDL description of hardware
        added to the coprocessor to enable the calibration.
    \item{VF}{12}{24}{x}{\Supmc}{frequency calibration} The frequency calibration software
        consists of a driver in the FPGA-SoC operating system and of a control software on
        a PC.
    \end{livrable}
\end{workpackage}
