Embedded systems (SoC and MPSoC) have become an inevitable evolution in the microelectronic industry.
The ASIC technology (Application Specific Integrated Circuits) 
is not an option for markets with small series of products due to ROI. % ROI? Return On Investment? Qu'est-ce que ça vien faire? Paul
Fortunately, the new FPGA (Field Programmable Gate Array) components,
such as the Virtex6 family from \xilinx, or the Stratix4 family from \altera can implement a complete
multi-processor architecture on a single device.
But the design of embedded system is a long and complex task that requires expertise in software,
software/hardware portioning, operating system, hardware design, VHDL/Verilog modeling.
Only very few SMEs have these multiple expertises and are present on the embedded system market.
The corresponding development cost is high and it is not compliant with
specification or standard evolution (problem of flexibility).
Furthermore, even small design shops in big companies are facing the same issue.
\begin{center}\begin{minipage}{.8\linewidth}\textit{
The major objective of COACH is to provide to system designers, an affordable
open-source framework to design embedded systems on FPGA devices.
}\end{minipage}\end{center}
%Current design methodologies provide quite low-level abstraction capabilities, and 
%there is an urgent need to leverage system level exploration through the use of a high-level 
%specification of the application and  design space exploration tools.
%The first system oriented approaches are appearing, among which those
%based on C/C++ and SystemC are the most popular, but few of them are specifically targetting FPGAs.
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The COACH project will propose a new design flow based on a small number of architectural templates.
An architectural template is a generic, parameterized architecture, relying on a predefined library 
of IP cores. 
Besides using a specific collection of general purpose IP cores (such as processors cores,
embedded memory controllers, system bus controllers, I/O and peripheral controllers), each architectural
template can be enriched by dedicated hardware coprocessors, obtained by high level synthesis (HLS) tools.
During this project, the COACH partners will develop three different architectural templates:
\begin{enumerate}
\item An \altera architectural template based on the \altera IP core library,
    the AVALON system bus and the NIOS processor.
\item A \xilinx architectural template based on the \xilinx IP core library, the
    \xilinxbus system bus and the \xilinxcpu processor.
\item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP
    communication infrastructure.
\end{enumerate}
%The proposed design flow starts from a high level description of the application, specified as a set of 
%parallel tasks written in C, without any assumption on the hardware or software implementation
%of these tasks. It lets the system
%designer in charge of expressing the coarse grain parallelism of the application, gives the designer
%the possibility to explore various mapping of the application on the selected template architecture,
%and offers a high predictability of results with respect to cost and performance objectives.
%\\
%When this interactive, system level, design space exploration is completed (converging to
%a specific mapping on a specific version of the selected architectural template), the rest of the flow 
%is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary
%code for the software running on the embedded processors, and the bit-stream to program the target FPGA 
%will be automatically generated by the COACH tools.
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%\parlf
%The strength of the COACH approach is the strong integration of the high-level synthesis tools 
%in a platform based design flow supporting virtual prototyping and design space exploration.
%Most building blocks already exist (resulting from previous projects): the GAUT 
%or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology,
%the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool,
%as well as the SoCLib library of SystemC simulation models.
%They must now be enhanced and integrated in a consistent design flow: this will
%be done in Magillem framework thanks to the IP-XACT standard.
%%The five academic laboratories worked very closely during more than one year (one monthly meeting
%%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
%%those various technologies, and to define the detailed architecture of the proposed design flow.
%%%%
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In HPC (High Performance Computing), the targeted application is an existing one
running on a PC.
The COACH framework helps designers to accelerate it by migrating critical parts into a
SoC embedded into an FPGA device plugged to the PC PCI/X bus 
%paul On ne sait jamais, ça pourrait être Hyper Transport
(or to any other communication fabric).
\begin{center}\begin{minipage}{.8\linewidth}\label{HPC:definition}\textit{
The second objective of COACH is to extend the framework for HPC applications.
}\end{minipage}\end{center}
This will allow SMEs to enter the HPC market for applications that are
unadapted to the current GPU based solutions.
\parlf
COACH generates SoCs which are part of larger systems. Thus it is important to take
into account the existing industrial design flow. For this reason COACH will use the 
IP-XACT IEEE 1685 standard for packaging these generated SoCs.
\begin{center}\begin{minipage}{.8\linewidth}\textit{
The third objective of COACH is to facilitate the integration of generated SoC in global system design flow.
}\end{minipage}\end{center}
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