The emerging complex and integrated heterogeneous embedded system platforms require
adequate design methods  to efficiently model, explore, analyze and design the ever complex software
and hardware architectures. Future Embedded Systems suppliers, in order to meet rapidly increasing
performance requirements and a pressure to lower development cost and shorten time-to-market,
will have to adopt new design methods and flows in order to keep pace with the increasing
complexity of design problems. Such methods, addressing these challenges starting from high levels of
abstraction, will have to perform large solution space explorations both for software and (possibly
reconfigurable) hardware, reducing the design effort and offering a high predictability of results
with respect to cost and performance objectives.
Current design methodologies provide quite low-level abstraction capabilities. However in a few years
from now tens of programmable processors will be embedded in an IC with more than 100M
transistors, therefore adding to the complexity of the problem of designing such systems.
Taking into account that the complexity of the software part is increasing at an even
faster rate, current solutions for design space exploration, mainly manually based, by no
means do supply an adequate efficiency.
Consequently, there is an urgent need to leverage system level
exploration through the use of a high level specification of the application and an early design
space exploration step. The first system oriented approaches are appearing, among which those
based on C/C++ and SystemC are the most popular. Such approaches can take place before and/or after
the co-design or architecture refinement steps and target the design space pruning in order to fully
exploit potential solutions that meet design and application constraints (power, latency,
throughput) within the design and market timeframe.
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Thus, new system-level design flows need to be developed, enabling the exploration of an application
independently of the implementation, almost at the beginning of the design process.
A fundamental element of this evolution is the definition of abstraction layers that should allow the
performance driven re-use of software and hardware components at the system level.
In this context, COACH will combine modeling and estimation methods and compilers and
design space exploration techniques. This approach will be a radical innovation in
embedded system design methodology.
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The reason is that the COACH framework is applied before high-level design tools in the embedded
systems design flow. In that way, it will make possible a real and efficiently combined
exploitation of high-level synthesis tools, parallelizing approaches and compilers, already
available on the market. These tools and approaches are not yet massively adopted, precisely
because this preliminary design step is missing. COACH will indeed permit (i) to predict and
control implementation optimizations, (ii) to target multiple implementation technologies
(and thus the associated tools) from a unique specification and (iii) to efficiently integrate high
and low-level design tools in a unique seamless design flow.
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The performance estimation methods combined with the design space exploration techniques will
finally allow the design process to start from system level specification and automatically explore the
potential architectures in order to find out the optimal implementation in a shorter design time and at
a lower global cost.
\par
To get an efficient embedded system, the system designer has to take into account
application characteristics when it chooses one of the available technologies.
This choice is not easy and in most cases the designer has to try different
technologies to retain the most adapted one.
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The first objective of COACH is to provide an open-source framework to
design embedded system on FPGA devices.
The COACH framework allows the designer to explore various software/hardware
partitions of the target application, to run timing and functional
simulations and to generate automatically both the software and the
synthesizable description of the hardware.
The main topics of the project are:
\begin{itemize} 
\item
Design space exploration: It consists in analysing the application runnig
on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and
hardware/software partitioning of tasks depending on technology choice.
This exploration is driven basically by throughput, latency and power
consumption criteria.
\item
Micro-architectural exploration: When hardware components are required, the
HLS tools of the framework generate them automatically. At this stage the
framework provides various HLS tools that allow the micro-architectural space
design exploration. The exploration criteria also are throughput, latency
and power consumption.
At this stage, preliminary source-level transformations will be
required to improve the efficiency of the target component.
For instance, one may transform a loop nest to expose parallelism,
or shrink an array to promote it to a register or reduce a memory footprint.

\item
Performance measurement: For each point in the design space,
figures of merit are available such as throughput, latency, power
consumption, area, memory allocation and data locality. They are evaluated
using virtual prototyping, estimation or analyzing methodologies.
\item
Targeted hardware technology: The COACH description of a system is
independent of the FPGA family.  Every point of the design
space can be implemented on any FPGA having the required resources.
Basically, COACH handles both Altera and Xilinx FPGA families.
\end{itemize}
As an extension of embedded system design, COACH deals also with High
Performance Computing (HPC).
In HPC, the kind of targeted application is an existing one running on a PC.
The COACH framework helps designer to accelerate it by migrating critical parts into a
SoC implemented on an FPGA plugged to the PC bus.
\par
COACH is the result of the will of several laboratories to unify their knowhow
and skills in the following domains: Operating system and hardware
communication (\tima, \citi), SoC and MPSoC (\upmc and \tima), ASIP (\irisa) and
HLS (\upmc, \ubs) and compilation (\irisa, \lip).
The project objective is to integrate these various domains into a unique
free framework (licence ...) masking as much as possible these domains and
its different tools to the user.

