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\subsubsection{\irisa}

The CAIRN group is an INRIA - Bretagne Atlantique project and a part of IRISA, UMR
6074. CAIRN members are affiliated from University of Rennes\~1 or Ecole Normale 
Supérieure de Cachan. the goal of CAIRN is to study reconfigurable system-on-chip, 
i.e. hardware systems whose configuration may change before or even during execution. 
To this end, CAIRN intends to approach reconfigurable architectures from three angles: 
the invention of new reconfigurable platforms, the development of associated 
transformation, compilation and synthesis tools, and the exploration of the interaction 
between algorithms and architectures.

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\subsubsection{\lip}
The Compsys group of Ecole Normale Sup\'erieure de Lyon is a project-team
of INRIA Rh\^one-Alpes and a part of Laboratoire de l'Informatique du
Parall\'elisme (LIP), UMR 5668 of CNRS. It has four permanent researchers
and a variable number of PhD students and post-docs. Its field of
expertise is compilation for embedded system, optimizing compilers
and automatic parallelization. It  has authored or contributed to
several well known libraries for linear programming, polyhedra manipulation
and optimization in general. It has strong industrial cooperations, notably
with ST Microelectonics and Thales.


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\subsubsection{\tima}
The TIMA laboratory ("Techniques of Informatics and Microelectronics
for integrated systems Architecture") is a public research laboratory
sponsored by Centre National de la Recherche Scientifique (CNRS, UMR5159),
Grenoble Institute of Technology (Grenoble-INP) and Universit� Joseph Fourier
(UJF).
The research topics cover the specification, design, verification, test,
CAD tools and design methods for integrated systems, from analog and
digital components on one end of the spectrum, to multiprocessor
Systems-on-Chip together with their basic operating system on the other end.

Currently, the lab contains 124 persons among whom 60 PhD candidates, and runs
32 ongoing French/European funded projects.
Since its creation in 1984, TIMA funded 7 start ups, patented 36 inventions
and had 243 PhD thesis defended.

The System Level Synthesis Group (25 people including PhDs) is
involved in several FP6, FP7, CATRENE and ANR projects.
Its field of expertise is in CAD and architecture for Multiprocessor
SoC and Hardware/Software interface.

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\subsubsection{\ubs}

The Lab-STICC (Laboratoire des Sciences et Techniques de l'Information, 
de la Communication, et de la Connaissance), is a French CNRS laboratory 
(UMR 3192) that gathers 4 research centers in the west and south 
Brittany; from the Universit� de Bretagne-Sud (UBS), the Universit� de 
Bretagne Occidentale (UBO), and Telecom Bretagne (ENSTB). 
\\
The Lab-STICC is composed of three departments: Microwave and equipments (MOM), 
Digital communications, Architectures and circuits (CACS) and Knowledge, 
information and decision (CID). The Lab-STICC represents a staff of 279 
people, including 115 researchers and 113 PhD students. 
The scientific production during the last 4 years represents 20 
books, 200 journal publications, 500 conference publications, 22 
patents, 69 PhDs diploma. 
\par
The UBS/Lab-STICC laboratory is involved in several national research 
projects (e.g. RNTL : SystemC'Mantic, EPICURE - RNRT : MILPAT, ALIPTA, 
A3S - ANR : MoPCoM, SoCLib, Famous, RaaR, AFANA, Open-PEOPLE, ICTER ...), 
CMCU project (COSIP) and regional projects (e.g. ITR projects PALMYRE 
...). It is also involved in European Project (e.g. ITEA/SPICES, 
IST/AETHER ...). These projects are conducted through tight cooperation 
with national and international companies and organizations (e.g. France 
Telecom CNET, MATRA, CEA, ASTRIUM, THALES Com., THALES Avionics, AIRBUS, 
BarCo, STMicroelectronics, Alcatel-Lucent ...). Results of those or former 
projects are for example the high-level synthesis tool GAUT, the UHLS 
syntax and semantics-oriented editor, the DSP power estimation tool 
Soft-explorer or the co-design framework Design Trotter.
\\
\par
The CACS department of the Lab-STICC (also referred as UBS/Lab-STICC), 
located in Lorient, is involved in COACH. 
The UBS/Lab-STICC is working on the design of complex electronic systems 
and circuits, especially but not exclusively focussing on real-time 
embedded systems, power and energy consumption optimization, high-level 
synthesis and IP design, digital communications, hardware/software 
co-design and ESL methodologies. The application targeted by the 
UBS/Lab-STICC are mainly from telecommunication and multimedia domains 
which enclose signal, image, video, vision, and communication processing.


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\subsubsection{\upmc}
University Pierre et Marie Curie (UPMC)  is the largest university in France (7400 employees,38000 students). 
The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of UPMC, hosting
more than 400 researchers, under the umbrella of the CNRS (Centre National de la Recherche Scientifique). 
The � System on Chip � Department of LIP6 consists of  80 people, including 40 PHD students. 
The research focus on CAD tools and methods for VLSI and System on Chip design. 
\\
The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts. 
The SoC department has been involved in several european projects :IDPS, EVEREST, OMI-HIC, OMI-MACRAME, 
OMI-ARCHES, EUROPRO, COSY, Medea SMT, Medea MESA, Medea+ BDREAMS, Medea+ TSAR. 
The public domain VLSI CAD system ALLIANCE, developped at UPMC is installed in more than 200 universities worldwide.
The LIP6 is in charge of the technical coordination of the SoCLib national project, and is hosting
the SoCLib WEB server.
In the SoCLin platform, the DSX tool is used for design space exploration.
It helps the system designer to describe the coarse grain parallelism of the software application
as a Task and Communication Graph, to configure the hardware architecture, and to map the 
multi-task software application on the multi-processors architecture.
The DSX toll will be extended to support the FPGA target.
Moreover, the LIP6 developped during the last 10 years the UGH tool for high level synthesis
of control-dominated coprocessors.
This tool will be modified to be integrated in the Coach design flow.
Even if the preferred dissemination policy for the Coach design flow will be the free software policy,
(following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies 
(including FLEXRAS) have been created by former researchers from  the SoC department of LIP6 between 1997 and 2002.

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\subsubsection{\altera}

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\subsubsection{\xilinx}

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\subsubsection{\bull}

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\subsubsection{\thales}

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\subsubsection{\zied}

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\subsubsection{\navtel}

