.. _concept-platform:

=================
Hardware Platform
=================

SoCLib
======

`SoCLib <http://www.soclib.fr/>`_ is the library with built-in support in
DSX.  This library offers a virtual prototyping environment for
hardware MP\ :sup:`2`\ -SoC platforms.  As a codesign tool, DSX needs an hardware
component library for the hardware part of the design.

Openness and good tools support of the SoCLib library makes it a good
candidate for DSX usage.  DSX uses SoCLib as an hardware platform
basic-block provider, and a benchmark environment.

DSX has its own high-level platform representation, made of SoCLib
IP-cores. Users can assemble a platform with the provided API and
then:

* use it as a mapping target for an application,

* generate a SystemC netlist of matching SoCLib components,

* call the SoCLib build-system to obtain a simulator from the
  generated netlist.

Architecture definition
=======================

An architecture definition is made of:

* an :py:class:`~soclib.Architecture` object.

* some :py:class:`~soclib.Architecture.create` calls, corresponding to
  some IP core in SoCLib, with its implementation and Metadata.
  Metadata defines ports of the component, and associated signals
  types.

* connection directives between ports.

.. note::

   As connections are directly done between ports, DSX high-level
   soclib netlists create signals implicitly. This leverages most
   tedious part of the netlisting.