Waits at least n cycles pass. Calling task may be unscheduled meanwhile.
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Waits n cycles pass in the hardware.
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When using a software implementation of a task for hardware coprocessor evaluation, some timing accuracy tweaks may be useful.
Purpose of this call is to simulate the latency of an hardware coprocessor latency from the software task’s code. When running as a SyntheticTask, all computation is done with no latency.
Sometimes, tasks have to poll from an hardware register until it has some defined condition satisfied. Here are some calls to implement such polling. When using these calls, tasks may be unscheduled until the condition is satisfied.
This function exists with different values of COMP and ENDIANNESS.
COMP is in eq (==), ne (!=), le (<=), gt (>), lt (<), or ge (>=).
ENDIANNESS is in be (big endian), le (little endian), or cpu (natural CPU endianness).
This waits until *addr COMP val is true, fetching addr with the given endianness.
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Example: srl_sched_wait_lt_be(addr, val) waits unitl the big-endian value pointed by addr is less than the constant passed in val.
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This waits until callback returns true.
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When dealing with SoC memory system, which is sometimes non-coherent, a cache control API may be useful. Here are the calls:
Removes the pointed data from the processor’s cache, if present.
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Removes all the lines matching the memory zone from processor’s cache.
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