soclib package API

Architecture

class soclib.Architecture

A soclib-based platform description.

__init__(abstraction_level, **default_args)

Creates a new platform.

Parameters:

• abstraction_level (str) – The main abstraction level of the platform, adds some default signals for “caba”.
• default_args – A key/value mapping of parameter values to implicitly add for any create() call.

create(module, name, **args)

Creates a new component in this platform.

Parameters:

• module (str) – Module name in Module Index.
• name (str) – Instance name
• args – A key/value mapping of components parameters. default_args passed at Architecture creation are used as defaults values here.

Returns:

a soclib.Component object.

Raises :

Any error if instantiation is invalid.

Underlying class is soclib.platform.Architecture.

Component

class soclib.Component

A component spawned by soclib.Architecture.create().

A component object is fully defined, it has an actual corresponding component implementation, it is fully parameterized. Ports are accessed as attributes (see Ports).

addSegment(name, address, size, cacheable = None, mt = None)

Adds a memory segment to the segment list targeting this component.

Parameters:

• name (str) – Name of segment
• address (int) – Base address of segment
• size (int) – Size in bytes of segment
• cacheable (bool) – Whether this segment should be cacheable
• mt (Component) – a component corresponding to a common:mapping_table soclib module

Raises :

ValueError if address or size is invalid.

Underlying class is soclib.component.Component.

Ports

In a Component, ports are available through their names, and the “p_” prefix is skipped, if present in metadata.

For instance, a module defined with the following .sd file format:

Module("caba:my_super_module",
       classname = "MySuperModule",
       ports = [
          Port('caba:bit_out','p_irq'),
          Port('caba:bit_in','p_irq_in', 10),
          ],
       )

Instantiated through the following code:

import soclib

arch = soclib.Architecture("caba")

inst0 = arch.create("caba:my_super_module", "inst0")

exports the ports as:

# simple ports as a Port object
inst0.irq

# port arrays an array of Port objects
inst0.irq_in[0]
inst0.irq_in[1]
inst0.irq_in[2]
...
inst0.irq_in[9]

class soclib.Port

A port attached to a Component. Ports are implicitly created by component creation.

// other

__floordiv__(other)

This corresponds to the following syntax:

inst0 = arch.create(...)
inst1 = arch.create(...)

new_signal = inst0.portA // inst1.portB

Spawns a signal compatible with both ports and connect them to it.

Parameters:other (Port) – another port Returns:spawned Signal object

setExternal(port_desc, name)

Exports the port to the boundary of the architecture. This permits to build hierarchical netlists.

Parameters:

• port_desc (str) – A port type in Module Index.
• name (str) – External port name.

Underlying class is soclib.component.Port.

class soclib.Signal

A signal. Signals are created by the connection of two ports together (See Port // operator). Reference is here for the two following methods:

// port

__floordiv__(port)

The // operator.

This corresponds to the following syntax:

inst0 = arch.create(...)
inst1 = arch.create(...)
inst2 = arch.create(...)

new_signal = inst0.portA // inst1.portB
new_signal // inst2.portB

# Equivalent to:

inst0.portA // inst1.portB // inst2.portB

Connects the signal to the given port.

Parameters:port (Port) – a compatible port Returns:the signal itself (so that you can use the return value for another connection).

setExternal(port_desc, name)

Exports the signal to the boundary of the architecture. This permits to build hierarchical netlists.

Parameters:

• port_desc (str) – A port type in Module Index.
• name (str) – External port name.

Underlying class is soclib.component.Signal.

Coprocessors

Coprocessors can be instantiated from their matching dsx.application.TaskModel object. This is done the following way:

1. Retrieve a model by its type, and get an implementation by its class:

   import dsx.application
   import soclib
   
   arch = soclib.Architecture(...)
   
   model = dsx.application.TaskModel.getByName("task_model_name")
   impl = model.getImpl(soclib.HwTask)
   

   See dsx.application.taskmodel.TaskModel.getByName() and dsx.application.taskmodel.TaskModel.getImpl().

2. Instantiate the coprocessor component and its interface controller:

   ctrl, coproc = model.instanciate(arch,
                                    "coproc_instance_name",
                                    "controller_instance_name")
   

   See soclib.hwtask.HwTask.instanciate().

3. Assign a segment to the controller:

   ctrl.addSegment("ctrl_seg", 0x42000000, 0x200, False)
   

   See soclib.Component.addSegment().

4. Connect the controller to the NoC:

   ctrl.vci_initiator // noc.to_initiator.new()
   ctrl.vci_target // noc.to_target.new()
   

   See Ports.

   Note

   Connections between the coprocessor and its controller are automatically done on instantiation.