| 1 | = Generic Architectures = |
| 2 | |
| 3 | == The concept == |
| 4 | |
| 5 | `Generic Architecture` means we will define some SoC hardware architecture with few variable parameters. |
| 6 | The main goal is to change number of Cpus or memory banks, but not main architecture like interconnect choice. |
| 7 | |
| 8 | == Implementation == |
| 9 | |
| 10 | An architecture is defined in a python class inherited from `Architecture` (defined in `soclib`). |
| 11 | Method `architecture` will create contents of the SoC: components creation, connections, utilities (like MappingTable). |
| 12 | |
| 13 | You'll have to tell the architecture framework where is the lowest-level component, most probably the base interconnect. This must be archieved by calling `self.setBase(component)`. |
| 14 | |
| 15 | == Parameters == |
| 16 | |
| 17 | Anywhere in `architecture` method, you may call `self.getParam(name, [default value])` to get an architecture instance parameter. |
| 18 | * name is the parameter name |
| 19 | * default value is optionnal |
| 20 | * user-specified value overrides default value |
| 21 | * if default value is not given when calling `getParam`, user-specified argument becomes mandatory. |
| 22 | |
| 23 | == Examples == |
| 24 | |
| 25 | === Basic example == |
| 26 | |
| 27 | We may define a basic architecture with no parameters: |
| 28 | |
| 29 | {{{ |
| 30 | class OneLevel(GenericArchitecture): |
| 31 | def architecture(self): |
| 32 | vgmn = Vgmn( ’vgmn’ ) |
| 33 | |
| 34 | mips0 = Mips( ’mips0’ ) |
| 35 | cache0 = Xcache( ’cache0’ ) |
| 36 | |
| 37 | # Cache ports connexion |
| 38 | cache0.cache( mips0.cache ) |
| 39 | vgmn.getTarget()( cache0.vci ) |
| 40 | |
| 41 | reset = Segment( ’reset’, |
| 42 | address = 0xbfc00000, |
| 43 | type = Cached ) |
| 44 | code = Segment( ’code’, type = Cached ) |
| 45 | data = Segment( ’data’, type = Uncached ) |
| 46 | ram = MultiRam( ’ram’, reset, code, data ) |
| 47 | |
| 48 | # Connections |
| 49 | vgmn.getInit()( ram.vci ) |
| 50 | |
| 51 | # Declare base component |
| 52 | self.setBase( vgmn ) |
| 53 | |
| 54 | # Add configuration utilities |
| 55 | self.setTimeBase() |
| 56 | self.setConfig(’mapping_table’, MappingTable()) |
| 57 | }}} |
| 58 | |
| 59 | As you may want to refer to some objects later on, you may set attributes to self: |
| 60 | |
| 61 | {{{ |
| 62 | ... |
| 63 | self.ram = MultiRam( ’ram’, reset, code, data ) |
| 64 | }}} |
| 65 | |
| 66 | === Parametrized example === |
| 67 | |
| 68 | We will define a one-level architecture using a Vgmn, with two parameters: number of Cpus (`ncpu`) and number of Ram components (`nram`). |
| 69 | By default, we will set `nram` to 1. |
| 70 | |
| 71 | We'll add in ram0 (which always exists) two more segments. |
| 72 | |
| 73 | We'll set those attributes: |
| 74 | * `vgmn`: the interconnect |
| 75 | * `cpu`: an array of all the cpus |
| 76 | * `ram`: an array of all the ram chips |
| 77 | * `cram`: an array of all the cached ram segments |
| 78 | * `uram`: an array of all the uncached ram segments |
| 79 | |
| 80 | This way, we'll be able to refer to `platform.ram[2]` or `platform.cpu[0]`. |
| 81 | |
| 82 | {{{ |
| 83 | class Parametrized(GenericArchitecture): |
| 84 | def architecture(self): |
| 85 | self.vgmn = Vgmn( ’vgmn’ ) |
| 86 | |
| 87 | self.cpu = [] |
| 88 | for i in range(self.getParam('ncpu')): |
| 89 | cpu = Mips( ’mips%d’%i ) |
| 90 | cache = Xcache( ’cache%d’%i ) |
| 91 | |
| 92 | # Cache ports connexion |
| 93 | cache.cache( cpu.cache ) |
| 94 | vgmn.getTarget()( cache.vci ) |
| 95 | self.cpu.append( cpu ) |
| 96 | |
| 97 | self.ram = [] |
| 98 | self.cram = [] |
| 99 | self.uram = [] |
| 100 | for i in range(self.getParam('nram', 1)): |
| 101 | cram = Segment( ’cram%d’%i, type = Cached ) |
| 102 | uram = Segment( ’uram%d’%i, type = Uncached ) |
| 103 | ram = MultiRam( ’ram%d’%i, cram, uram) |
| 104 | |
| 105 | vgmn.getInit()( ram.vci ) |
| 106 | self.ram.append( ram ) |
| 107 | self.cram.append( cram ) |
| 108 | self.uram.append( uram ) |
| 109 | |
| 110 | self.reset = Segment( ’reset', type = Cached ) |
| 111 | self.excep = Segment( ’excep', type = Cached ) |
| 112 | self.ram[0].addSegment( self.reset, self.excep ) |
| 113 | |
| 114 | self.setBase( self.vgmn ) |
| 115 | |
| 116 | self.setTimeBase() |
| 117 | self.setConfig(’mapping_table’, MappingTable()) |
| 118 | }}} |