Changes between Version 5 and Version 6 of DsxArchitectureCreation


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Timestamp:
Mar 3, 2007, 12:59:39 AM (18 years ago)
Author:
Nicolas Pouillon
Comment:

Split up

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  • DsxArchitectureCreation

    v5 v6  
    1 = Generic Architectures =
    2 
    31[[PageOutline]]
    42
    5 == The concept ==
     3= The concept =
    64
    75`Generic Architecture` means we will define some SoC hardware architecture with few variable parameters.
    86The main goal is to change number of Cpus or memory banks, but not main architecture like interconnect choice.
    97
    10 == Implementation ==
     8= Implementation =
    119
    12 An architecture is defined in a python class inherited from `Architecture` (defined in `soclib`).
     10An architecture is defined in a python class inherited from `GenericArchitecture` (defined in `dsx`).
    1311Method `architecture` will create contents of the SoC: components creation, connections, utilities (like MappingTable).
    1412
    1513You'll have to tell the architecture framework where is the lowest-level component, most probably the base interconnect. This must be archieved by calling `self.setBase(component)`.
    1614
    17 == Parameters ==
     15= Parameters =
    1816
    1917Anywhere in `architecture` method, you may call `self.getParam(name)` to get an architecture instance parameter.
    … …  
    2422 * default value must be specified in class-global dictionnary 'defaults'
    2523
    26 == Examples ==
     24= Other specific architecture definitions =
    2725
    28 === Basic example ===
     26You may also use SoclibGenericArchitecture, a specialization of GenericArchitecture for VCI-based platforms.
    2927
    30 We may define a basic architecture with no parameters:
    31 
    32 {{{
    33 class OneLevel(GenericArchitecture):
    34     def architecture(self):
    35         vgmn = Vgmn( ’vgmn’ )
    36 
    37         mips0 = Mips( ’mips0’ )
    38         cache0 = Xcache( ’cache0’ )
    39 
    40         # Cache ports connexion
    41         cache0.cache // mips0.cache
    42         vgmn.getTarget() // cache0.vci
    43 
    44         reset = Segment( ’reset’,
    45                          address = 0xbfc00000,
    46                          type = Cached )
    47         excep = Segment( ’excep’,
    48                          address = 0x80000080,
    49                          type = Cached )
    50         code = Segment( ’code’, type = Cached )
    51         data = Segment( ’data’, type = Uncached )
    52         ram = MultiRam( ’ram’, reset, excep, code, data )
    53 
    54         # Connections
    55         vgmn.getInit() // ram.vci
    56 
    57         # Declare base component
    58         self.setBase(vgmn)
    59 
    60         # Add configuration utilities
    61         self.setTimeBase()
    62         self.setConfig(’mapping_table’, MappingTable())
    63 }}}
    64 
    65 As you may want to refer to some objects later on, you may set attributes to self:
    66 
    67 {{{
    68         ...
    69         self.ram = MultiRam( ’ram’, reset, code, data )
    70 }}}
    71 
    72 === Parametrized example ===
    73 
    74 We will define a one-level architecture using a Vgmn, with two parameters: number of Cpus (`ncpu`) and number of Ram components (`nram`).
    75 We will set `nram` default value to 1.
    76 
    77 We'll add in `ram0` (which always exists) two more segments: `excep` and `reset`.
    78 
    79 We'll those attributes in instance objet (accessible through `object.name`):
    80  * `vgmn`: the interconnect
    81  * `cpu`: a list of all the cpus
    82  * `ram`: a list of all the ram chips
    83  * `cram`: a list of all the cached ram segments
    84  * `uram`: a list of all the uncached ram segments
    85 
    86 This way, we'll be able to refer to `platform.ram[2]` or `platform.cpu[0]`.
    87 
    88 {{{
    89 class Parametrized(GenericArchitecture):
    90     defaults = {
    91         'nram': 1,
    92     }
    93     def architecture(self):
    94         self.vgmn = Vgmn( ’vgmn’ )
    95 
    96         self.cpu = []
    97         for i in range(self.getParam('ncpu')):
    98             cpu = Mips( ’mips%d’%i )
    99             cache = Xcache( ’cache%d’%i )
    100 
    101             # Cache ports connexion
    102             cache.cache // cpu.cache
    103             vgmn.getTarget() // cache.vci
    104             self.cpu.append( cpu )
    105 
    106         self.ram = []
    107         self.cram = []
    108         self.uram = []
    109         for i in range(self.getParam('nram')):
    110             cram = Segment( ’cram%d’%i, type = Cached )
    111             uram = Segment( ’uram%d’%i, type = Uncached )
    112             ram = MultiRam( ’ram%d’%i, cram, uram)
    113 
    114             vgmn.getInit() // ram.vci
    115             self.ram.append( ram )
    116             self.cram.append( cram )
    117             self.uram.append( uram )
    118 
    119         self.reset = Segment( ’reset', type = Cached )
    120         self.excep = Segment( ’excep', type = Cached )
    121         self.ram[0].addSegment( self.reset, self.excep )
    122 
    123         self.setBase( self.vgmn )
    124 
    125         self.setTimeBase()
    126         self.setConfig(’mapping_table’, MappingTable())
    127 }}}
    128 
    129 In this platform
    130  * argument `nram` is optional with default value being 1
    131  * arguments `ncpu` is mandatory
     28In your design, there may be some [MacroComponent MacroComponent]s you would like to define on their own.