Changes between Version 9 and Version 10 of DsxDocumentation

Timestamp:

Jan 28, 2008, 1:07:04 PM (18 years ago)

Author:

alain

Comment:

--

DsxDocumentation

@@ -202 +202 @@
 
 In the present version of DSX, each hardware component must be described by a PYTHON
-class that defines the component interface, and the component parameters. The instance
-name is mandatory, but all other parameters have default values and can be skipped: 
+class that defines the component interface, and the component parameters. 
+The list of available components can be found in SoclibComponents.
+For all components, the instance name is mandatory, but all other parameters have default values and can be skipped: 
 {{{
 # creation of a MIPS R3000 processor core
-MY_proc0 = Mips( 'proc0' )
-
-# creation of a generic cache
+My_Proc = Mips( 'proc' )
+
+# creation of a cache controler
+My_Cache = Xcache( 'cache',
+                        dcache_lines = 32,
+                        dcache_words = 8,
+                        dcache_lines = 32,
+                        dcache_words = 8)
 }}}
 
 === D2) Connecting the components ===
 
+Hardware components have input/output ports, and are connected through signals, 
+but those signals are implicit in the DSX/L description. To connect the port a of component c1 to the port b of component c2, DSX/L define the // operator : 
+{{{
+c1.a // c2.b
+}}}
+Depending on the component type, the port designation can vary:
+ * When the number of ports is fixed, the ports are attributs : My_Proc0.cache define the cache port of the MIPS processor.
+ * When the number of port is not fixed (typivally for interconnect component, the ports are accessed through a dedicated method : the getTarget() method of the !LocalCrossbar component returns a VCI target port.
+The following example describes asimple system with two processor and on e embedded memory:
+{{{
+# components instanciacion
+My_Proc0 = Mips( 'proc0' )
+My_Cache0 = Xcache( 'cache0' )
+My_Proc1 = Mips( 'proc1' )
+My_Cache1 = Xcache( 'cache1' )
+My_Ram = MultiRam( 'ram' )
+My_Crossbar = LocalCrossbar( 'crossbar' )
+                     
+# components connexion
+My_Proc0.cache // My_Cache0.cache
+My_Proc1.cache // My_Cache1.cache
+My_Crossbar.getTarget() // My_cache0.vci
+My_Crossbar.getTarget() // My_cache1.vci
+My_Crossbar.getInitiator() // My_cache0.vci
+
+
+}}}
+}}}
+
 === D3) Address space segmentation ===