Changes between Version 11 and Version 12 of DsxDocumentation


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Timestamp:
Jan 28, 2008, 7:25:53 PM (17 years ago)
Author:
alain
Comment:

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  • DsxDocumentation

    v11 v12  
    282282}}}
    283283 
    284 
    285 === D4) Hardware architecture definition ===
    286 
    287 
    288 === D5) Mapping table ===
    289 
    290 === D6) Generic platforms ===
    291 
     284=== D4) Generic platforms ===
     285
     286As DSX/L is based on PYTHON, it is possible to define generic, parametrized architectutes, that can
     287be reused for various applications. Those reusable architectures are derived classes
     288from the basic '''Architecture''' class. The implementation is defined in the architecture() method.
     289
     290As an example we define a parameterized multi-processors architecture, called MultiProc, and containing
     291 a variable number of processors. The parameter(s) must be named, and the actual parameter value is defined when the architecture is instanciated. The parameter is referenced with the ''getParam()'' method:
     292{{{
     293##########################
     294# generic architecture definition
     295class MultiProc(Architecture) :
     296    defaults = { ’nbcpu’ : 2 }
     297    def architecture(self):
     298
     299    # segments definition
     300    self.reset = Segment( ’reset’, address = 0xbfc00000, type = Cached )
     301    self.code = Segment( ’code’, type = Cached )
     302    self.data = Segment( ’data’, type = Uncached )
     303
     304    # components instanciation and connexion
     305    self.vgmn = Vgmn( ’vgmn’ )
     306    self.ram = MultiRam( ’ram’, self.reset, self.code, self.data )
     307    # processors and caches
     308    self.cpus = []
     309    for i in self.getParam( ’nbcpu’ ):
     310        m = Mips( ’mips%d’%i )
     311        self.cpus.append( m )
     312        c = Xcache( ’cache%d’%i )
     313        g:c.cache // m.cache )
     314        c.vci // self.vgmn.getTarget() )
     315    self.vgmn.getTarget() // self.c1
     316    self.vgmn.getTarget() // self.c2
     317    self.vgmn.getInit() // self.ram
     318
     319    # base definition
     320    self.setBase( self.vgmn )
     321
     322    # segment table initialization
     323    self.setConfig(’mapping_table’, MappingTable() )
     324
     325############################
     326# generic architecture instanciation
     327my_board = MultiProc( nbcpu = 4 ) 
     328}}}
     329 
    292330== E)  Mapping the software on the hardware ==
    293331