| 36 | | An hardware implementation is in fact a corpocessor (which must be implemented in simulator/synthesis context and declared in DSX) doing the same thing as the task. |
| 37 | | |
| 38 | | The following restrictions apply: |
| 39 | | * Task must only use MwMr fifos for data exchange |
| 40 | | * Task must not be RealTime |
| | 36 | An hardware implementation is in fact a dedicated hardware coprocessor (which must be declared |
| | 37 | in DSX) doing the same thing as the task. |
| | 38 | Constraint : The Task must only use MwMr channels for data exchange, as the coprocessor must use |
| | 39 | an hardware MWMR controller to interface the VCI interconnect. |
| 59 | | If a task follows constraints for having an hardware implementation, it may be virtually implemented in hardware, which means it will be run in simulator's context as if it were a coprocessor, actually using C implementation. |
| 60 | | |
| 61 | | This kind if virtualization is only available for SystemC simulation (ie not VHDL), and you must have defined a software implementation. |
| 62 | | If your task has a SyntheticTask() declaration and an HwTask at the same time, the implementation chosen by DSX for simulation purposes will be unpredictable, you should avoid such situations. |
| | 58 | If a designer wants to use an hardware implementation, but the hardware coprocessor |
| | 59 | does not exist yet, the task may be virtually implemented in hardware, which means it will |
| | 60 | use the MWMR controller to interface the VCI interconnect, and the C implementation |
| | 61 | will be used to emulate an hardware coprocessor. |
