| | 68 | from dsx.hard.hard import * |
| | 69 | |
| | 70 | |
| | 71 | def AlmoArch(nb_proc = 4, nb_tty = 2, timer_pbase = 0x91000000, icu_pbase = 0x9F000000): |
| | 72 | |
| | 73 | cluster_x = 1 |
| | 74 | cluster_y = 1 |
| | 75 | nb_clusters = cluster_x * cluster_y |
| | 76 | hd = Hardware(cluster_x, cluster_y, nb_proc) |
| | 77 | |
| | 78 | ####### peripherals ######## |
| | 79 | hd.add(Tty('tty', pbase = 0x90000000, channel_size = 16, nb_channel = nb_tty)) |
| | 80 | |
| | 81 | for cl in range(nb_clusters): |
| | 82 | hd.add(Timer('timer%d'%cl, pbase = timer_pbase + (cl * hd.cluster_span), channel_size = 16, nb_channel = nb_proc)) |
| | 83 | hd.add(Icu ('icu%d'%cl , pbase = icu_pbase + (cl * hd.cluster_span) , channel_size = 32, nb_channel = nb_proc)) |
| | 84 | |
| | 85 | |
| | 86 | ######## irqs ######## |
| | 87 | for i in xrange(nb_proc): |
| | 88 | hd.add(Irq(proc_id = i , cluster_id = 0, icu_irq_id = i, peri = Timer , channel_id = i )) |
| | 89 | |
| | 90 | |
| | 91 | ##### mwmr_coproc ###### |
| | 92 | hd.add(MwmrCoprocTaskWrapper("tg_coproc" , pbase = 0x94000000, channel_size = 32, sc_name = 'TgCoproc')) |
| | 93 | hd.add(MwmrCoprocTaskWrapper("ramdac_coproc", pbase = 0x95000000, channel_size = 32, sc_name = 'RamdacCoproc')) |
| | 94 | |
| | 95 | ######## Mems ######## |
| | 96 | hd.add(ROM("PSEG_ROM", pbase = 0xbfc00000, size = 0x00010000)) |
| | 97 | hd.add(RAM("PSEG_RAU", pbase = 0x00000000, size = 0x01000000)) |
| | 98 | hd.add(RAM("PSEG_RAK", pbase = 0x80000000, size = 0x00100000)) |
| | 99 | |
| | 100 | return hd |
| | 101 | |
| | 102 | }}} |
| | 104 | {{{ |
| | 105 | #!/usr/bin/env python |
| | 106 | |
| | 107 | from dsx.hard.hard import * |
| | 108 | |
| | 109 | |
| | 110 | def ClusteredArch(cluster_x = 2, cluster_y = 2, nb_tty = 2, wcoproc = False): |
| | 111 | |
| | 112 | nb_proc = 1 |
| | 113 | nb_cluster = cluster_x * cluster_y |
| | 114 | ram_pbase = 0x00000000 |
| | 115 | icu_pbase = 0x00100000 |
| | 116 | dma_pbase = 0x00200000 |
| | 117 | timer_pbase = 0x00300000 |
| | 118 | tty_pbase = 0xFFD00000 |
| | 119 | |
| | 120 | hd = Hardware(cluster_x = cluster_x , cluster_y = cluster_y, nb_proc = nb_proc) #nb_proc : proc by cluster |
| | 121 | |
| | 122 | ######### peripherals ########## |
| | 123 | hd.add(Tty('tty', pbase = tty_pbase, channel_size = 16, nb_channel = nb_tty)) |
| | 124 | |
| | 125 | for cl in range(nb_cluster): |
| | 126 | hd.add(Timer('timer%d'%cl, pbase = timer_pbase + (cl * hd.cluster_span), channel_size = 16, nb_channel = nb_proc)) |
| | 127 | hd.add(Icu ('icu%d'%cl, pbase = icu_pbase + (cl * hd.cluster_span), channel_size = 32, nb_channel = nb_proc)) |
| | 128 | |
| | 129 | ######### mwmr_coproc ######### |
| | 130 | hd.add(MwmrCoprocTaskWrapper("tg_coproc", pbase = 0xFFE00000, channel_size = 32, sc_name = 'TgCoproc')) |
| | 131 | hd.add(MwmrCoprocTaskWrapper("ramdac_coproc", pbase = 0xFFF00000, channel_size = 32, sc_name = 'RamdacCoproc')) |
| | 132 | |
| | 133 | ############## IRQ ############ |
| | 134 | for j in xrange(nb_cluster): |
| | 135 | for i in xrange(nb_proc): |
| | 136 | hd.add(Irq(cluster_id = j, proc_id = i, icu_irq_id = i, peri = Timer, channel_id = i)) |
| | 137 | |
| | 138 | ############# MEMS ############ |
| | 139 | hd.add(ROM("SEG_ROM", pbase = 0xbfc00000, size = 0x000F0000)) |
| | 140 | |
| | 141 | for cl in xrange(nb_cluster): |
| | 142 | hd.add(RAM("SEG_RAM_%d"%cl, pbase = ram_pbase + (cl * hd.cluster_span), size = 0x00100000)) |
| | 143 | |
| | 144 | |
| | 145 | return hd |
| | 146 | |
| | 147 | }}} |