| 1 | [[Image(vgmn_noirq_mono.png, align=right)]] |
| 2 | |
| 3 | {{{ |
| 4 | from dsx.hardware import * |
| 5 | from soclib import * |
| 6 | |
| 7 | class VgmnNoirqMono(SoclibGenericArchitecture): |
| 8 | def architecture(self): |
| 9 | |
| 10 | # Définition des segments |
| 11 | |
| 12 | cram0 = Segment("cram0", Cached) |
| 13 | uram0 = Segment("uram0", Uncached) |
| 14 | cram1 = Segment("cram1", __remplir__) |
| 15 | uram1 = Segment("uram1", __remplir__) |
| 16 | reset = Segment("reset", Cached, addr = 0xbfc00000) |
| 17 | excep = Segment("excep", Cached, addr = __remplir__) |
| 18 | |
| 19 | # Instanciation des composants matériels |
| 20 | |
| 21 | vgmn = Vgmn("vgmn",__remplir__) |
| 22 | xcache = Xcache("xcache", __remplir__) |
| 23 | processor = Mips("processor") |
| 24 | tty = MultiTty("tty", __remplir__) |
| 25 | ram0 = MultiRam("ram0", cram0, uram0, excep) |
| 26 | ram1 = MultiRam("ram0", __remplir__) |
| 27 | locks = Locks("locks") |
| 28 | |
| 29 | # Définition de la net-list (connexions) |
| 30 | |
| 31 | processor.cache // xcache.cache |
| 32 | xcache.vci // vgmn.getTarget() |
| 33 | tty.vci // vgmn.getInit() |
| 34 | ram0.vci // __remplir__ |
| 35 | ram1.vci // __remplir__ |
| 36 | locks.vci // __remplir__ |
| 37 | tty.irq[0] // processor.irq[0] |
| 38 | |
| 39 | # Construction architecture et creation mapping table |
| 40 | |
| 41 | self.setBase(vgmn) |
| 42 | |
| 43 | # Exportation des variables locales |
| 44 | |
| 45 | self.cram0 = cram0 |
| 46 | self.uram0 = uram0 |
| 47 | self.cram1 = cram1 |
| 48 | self.uram1 = uram1 |
| 49 | self.reset = reset |
| 50 | self.excep = excep |
| 51 | |
| 52 | self.vgmn = vgmn |
| 53 | self.xcache = xcache |
| 54 | self.processor = processor |
| 55 | self.tty = tty |
| 56 | self.locks = locks |
| 57 | self.ram0 = ram0 |
| 58 | self.ram1 = ram1 |
| 59 | |
| 60 | }}} |