| | 1 | SocLib is an open IP-core library, with at least 4 implementations: |
| | 2 | * CABA (Bit cycle accurate) in [SystemC] |
| | 3 | * Tlm (Transaction level modeling) in SystemC |
| | 4 | * Tlm/T (Transaction level modeling with time) in SystemC |
| | 5 | * RTL (Register transfer layer) in Vhdl or Verilog |
| | 6 | |
| | 7 | Many IPs are defined, in which: |
| | 8 | * CPUs (PPC, !OpenRisc, Mips, ...) |
| | 9 | * Rams, Roms, ... |
| | 10 | * Interconnection components (Micro-networks on chip (NoC) and Buses) |
| | 11 | * VCI |
| | 12 | * PI-Bus |
| | 13 | * Dedicated components for application support |
| | 14 | * SpinLock oriented rams |
| | 15 | * MwMr controllers |
| | 16 | |
| | 17 | It may be obtained on https://www-asim.lip6.fr/trac/soclib |
