[160] | 1 | /********************************************************************************/ |
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| 2 | /* File : reset.S */ |
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| 3 | /* Author : Alain Greiner & Mohamed karaoui */ |
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| 4 | /* Date : 03/06/2012 */ |
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| 5 | /********************************************************************************/ |
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| 6 | /* This boot code is for a multi-cluster, multi-processor architecture, */ |
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| 7 | /* running one or several multi-tasks software application(s) defined in the */ |
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| 8 | /* the mapping_info data-structure. */ |
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| 9 | /* It uses the mapping_info data structure to build the page tables. */ |
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| 10 | /* Processor 0 is in charge of building all pages tables. */ |
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| 11 | /* Other processors are waiting until the mapping_info signature has been */ |
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| 12 | /* modified by processor 0 (done while executing kernel_init code). */ |
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| 13 | /* The entry point is 0xbfc00000, but the actual boot code starts at address */ |
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| 14 | /* 0xbfc00500, and a minimal boot exception handler is implemented at address */ |
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| 15 | /* 0xbfc0380. */ |
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| 16 | /********************************************************************************/ |
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| 17 | |
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| 18 | #include <giet_config.h> |
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| 19 | #include <mips32_registers.h> |
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| 20 | |
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| 21 | #define EXCEP_ORG 0x380 |
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| 22 | #define START_ORG 0x500 |
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| 23 | |
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| 24 | #define OUT_MAPPING_SIGNATURE 0xBABEF00D |
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| 25 | |
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| 26 | .section .boot,"ax",@progbits |
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| 27 | .align 2 |
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| 28 | .set noreorder |
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| 29 | |
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| 30 | /********************************************************/ |
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| 31 | /* reset entry point */ |
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| 32 | /* (address 0xBFC00000 imposed by the hardware) */ |
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| 33 | /********************************************************/ |
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| 34 | boot_reset: |
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| 35 | j boot_start |
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| 36 | nop |
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| 37 | |
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| 38 | /*******************************************************/ |
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| 39 | /* handling exceptions in the boot phase */ |
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| 40 | /* (address 0xBFC00380 imposed by the hardware */ |
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| 41 | /*******************************************************/ |
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| 42 | .align 2 |
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| 43 | .org EXCEP_ORG |
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| 44 | boot_excep: |
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| 45 | la a0, boot_error_string |
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| 46 | jal boot_tty_puts |
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| 47 | nop |
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| 48 | mfc0 a0, CP0_TIME |
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| 49 | jal boot_tty_putw |
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| 50 | nop |
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| 51 | la a0, boot_lf_string |
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| 52 | jal boot_tty_puts |
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| 53 | nop |
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| 54 | |
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| 55 | la a0, boot_epc_string |
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| 56 | jal boot_tty_puts |
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| 57 | nop |
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| 58 | mfc0 a0, CP0_EPC |
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| 59 | |
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| 60 | jal boot_tty_putw |
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| 61 | nop |
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| 62 | la a0, boot_lf_string |
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| 63 | jal boot_tty_puts |
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| 64 | nop |
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| 65 | |
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| 66 | la a0, boot_cr_string |
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| 67 | jal boot_tty_puts |
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| 68 | nop |
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| 69 | mfc0 a0, CP0_CR |
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| 70 | jal boot_tty_putw |
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| 71 | nop |
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| 72 | la a0, boot_lf_string |
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| 73 | jal boot_tty_puts |
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| 74 | nop |
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| 75 | |
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| 76 | la a0, boot_sr_string |
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| 77 | jal boot_tty_puts |
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| 78 | nop |
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| 79 | mfc0 a0, CP0_SR |
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| 80 | jal boot_tty_putw |
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| 81 | nop |
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| 82 | la a0, boot_lf_string |
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| 83 | jal boot_tty_puts |
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| 84 | nop |
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| 85 | |
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| 86 | la a0, boot_bar_string |
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| 87 | jal boot_tty_puts |
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| 88 | nop |
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| 89 | mfc0 a0, CP0_BAR |
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| 90 | jal boot_tty_putw |
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| 91 | nop |
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| 92 | la a0, boot_lf_string |
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| 93 | jal boot_tty_puts |
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| 94 | nop |
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| 95 | |
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| 96 | j boot_exit |
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| 97 | nop |
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| 98 | |
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| 99 | /*******************************************/ |
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| 100 | /* actual starting point for the boot code */ |
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| 101 | /*******************************************/ |
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| 102 | .align 2 |
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| 103 | .org START_ORG |
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| 104 | |
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| 105 | boot_start: |
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| 106 | /* get the procid */ |
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| 107 | mfc0 k0, CP0_PROCID |
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| 108 | andi k0, k0, 0x3FF /* no more than 1024 processors... */ |
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| 109 | |
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| 110 | /* Only processor 0 does init */ |
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| 111 | bne k0, zero, boot_wait_signature |
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| 112 | nop |
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| 113 | |
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| 114 | /* temporary stack for procesor 0 : 16K */ |
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| 115 | la sp, seg_boot_stack_base |
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| 116 | addiu sp, sp, 0x4000 |
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| 117 | |
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| 118 | /* plat-form initialisation */ |
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| 119 | jal boot_init |
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| 120 | nop |
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[162] | 121 | j to_kinit |
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[160] | 122 | nop |
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| 123 | |
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| 124 | boot_wait_signature: |
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| 125 | la k0, seg_mapping_base |
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| 126 | cache 0x11, 0(k0) /* invalidate local cache copy */ |
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| 127 | lw k0, 0(k0) /* k0 <= mapping_info[0] */ |
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| 128 | li k1, OUT_MAPPING_SIGNATURE |
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| 129 | bne k1, k0, boot_wait_signature |
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| 130 | nop |
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| 131 | |
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[162] | 132 | to_kinit: |
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[160] | 133 | /* All processors initialize PTPR / MODE */ |
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| 134 | /* and jump to kernel_init code. */ |
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| 135 | |
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| 136 | /* get the procid */ |
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| 137 | mfc0 s0, CP0_PROCID |
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| 138 | andi s0, s0, 0x3FF /* no more than 1024 processors... TOFIX*/ |
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| 139 | |
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| 140 | /* load a PTPR */ |
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| 141 | la k1, _ptabs |
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| 142 | lw k1, 0(k1) |
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| 143 | srl k1, k1, 13 |
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| 144 | mtc2 k1, CP2_PTPR /* ptpr <= _ptabs[0] */ |
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| 145 | |
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| 146 | /* activates MMU */ |
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| 147 | li k1, 0xF |
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| 148 | mtc2 k1, CP2_MODE /* load MODE register */ |
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| 149 | |
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| 150 | /* jump to kernel_init */ |
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| 151 | la k0, seg_kernel_init_base |
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| 152 | j k0 |
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| 153 | nop |
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| 154 | |
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| 155 | |
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| 156 | boot_error_string: .asciiz "\n[BOOT] Fatal Error at cycle" |
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| 157 | boot_sr_string: .asciiz " SR = " |
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| 158 | boot_cr_string: .asciiz " CR = " |
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| 159 | boot_epc_string: .asciiz " EPC = " |
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| 160 | boot_bar_string: .asciiz " BAR = " |
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| 161 | boot_lf_string: .asciiz "\n" |
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| 162 | |
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| 163 | .set reorder |
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| 164 | |
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| 165 | |
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