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reset.S @ 222

Last change on this file since 222 was 207, checked in by alain, 12 years ago
Several bugs have been fixed to support TSAR multi-cluster architecture such as the "tsarv4-generic_mmu" platform.
File size: 5.6 KB

Line
1	/********************************************************************************/
2	/* File : reset.S */
3	/* Author : Alain Greiner & Mohamed karaoui */
4	/* Date : 03/06/2012 */
5	/********************************************************************************/
6	/* This boot code is for a multi-cluster, multi-processor architecture, */
7	/* running one or several multi-tasks software application(s) defined in */
8	/* the mapping_info data-structure. */
9	/* Procesor 0 uses the mapping_info data structure to statically initialize */
10	/* the kernel structures: */
11	/* - build page tables for all vspaces */
12	/* - initializes the vobjs not initialized by GCC */
13	/* - initialize the schedulers and task contexts for all processeurs */
14	/* - initialize the peripherals */
15	/* Other processors are waiting until the mapping_info signature has been */
16	/* modified by processor 0. */
17	/* */
18	/* Implementation note: */
19	/* The entry point is 0xbfc00000, but the actual boot code starts at address */
20	/* 0xbfc00500, and a minimal boot exception handler is implemented at address */
21	/* 0xbfc0380. */
22	/********************************************************************************/
23
24	#include <giet_config.h>
25	#include "../sys/mips32_registers.h"
26
27	#define EXCEP_ORG 0x380
28	#define START_ORG 0x500
29
30	#define OUT_MAPPING_SIGNATURE 0xBABEF00D
31
32	.section .boot,"ax",@progbits
33	.align 2
34	.set noreorder
35
36	/********************************************************/
37	/* reset entry point */
38	/* (address 0xBFC00000 imposed by the hardware) */
39	/********************************************************/
40	boot_reset:
41	j boot_start
42	nop
43
44	/*******************************************************/
45	/* handling exceptions in the boot phase */
46	/* (address 0xBFC00380 imposed by the hardware */
47	/*******************************************************/
48	.align 2
49	.org EXCEP_ORG
50
51	boot_excep:
52
53	# get the lock protecting TTY0
54	la k0, boot_tty0_lock
55	ll k1, 0(k0)
56	bnez k1, boot_excep
57	li k1, 1
58	sc k1, 0(k0)
59	beqz k1, boot_excep
60	nop
61
62	# display error messages on TTY0
63	la a0, boot_error_string
64	jal boot_puts
65	nop
66	mfc0 a0, CP0_TIME
67	jal boot_putd
68	nop
69	la a0, boot_lf_string
70	jal boot_puts
71	nop
72
73	la a0, boot_pid_string
74	jal boot_puts
75	nop
76	mfc0 k0, CP0_PROCID
77	andi a0, k0, 0xFFF
78	jal boot_putd
79	nop
80	la a0, boot_lf_string
81	jal boot_puts
82	nop
83
84	la a0, boot_epc_string
85	jal boot_puts
86	nop
87	mfc0 a0, CP0_EPC
88	jal boot_putx
89	nop
90	la a0, boot_lf_string
91	jal boot_puts
92	nop
93
94	la a0, boot_cr_string
95	jal boot_puts
96	nop
97	mfc0 a0, CP0_CR
98	jal boot_putx
99	nop
100	la a0, boot_lf_string
101	jal boot_puts
102	nop
103
104	la a0, boot_sr_string
105	jal boot_puts
106	nop
107	mfc0 a0, CP0_SR
108	jal boot_putx
109	nop
110	la a0, boot_lf_string
111	jal boot_puts
112	nop
113
114	la a0, boot_bar_string
115	jal boot_puts
116	nop
117	mfc0 a0, CP0_BVAR
118	jal boot_putx
119	nop
120	la a0, boot_lf_string
121	jal boot_puts
122	nop
123
124	# release the lock
125	la k0, boot_tty0_lock
126	li k1, 0
127	sw k1, 0(k0)
128
129	# exit
130	j boot_exit
131	nop
132
133	/*******************************************/
134	/* actual starting point for the boot code */
135	/*******************************************/
136	.align 2
137	.org START_ORG
138
139	boot_start:
140
141	# get the procid
142	mfc0 k0, CP0_PROCID
143	andi k0, k0, 0xFFF # no more than 4096 processors
144
145	# Only processor 0 does init
146	bne k0, zero, boot_wait_signature
147	nop
148
149	# Processor 0 get a temporary stack
150	la sp, seg_boot_stack_base
151	addiu sp, sp, 0x3000 # SP <= seg_boot_stack + 12K
152
153	# Processor 0 initialises all kernel structures
154	jal boot_init
155	nop
156
157	# jump to kernel_init
158	j boot_to_kernel_init
159	nop
160
161	boot_wait_signature:
162
163	# all other processors are waiting signature change
164	la k0, seg_mapping_base
165	cache 0x11, 0(k0) # invalidate local cache copy
166	lw k0, 0(k0) # k0 <= mapping_info[0]
167	li k1, OUT_MAPPING_SIGNATURE
168	bne k1, k0, boot_wait_signature
169	nop
170
171	# all other processors initialise SP register: temporary stack of 256 bytes
172	la sp, seg_boot_stack_base
173	addiu sp, sp, 0x3100
174	mfc0 k0, CP0_PROCID
175	andi k0, k0, 0xFFF
176	sll k0, k0, 8
177	addu sp, sp, k0 # SP <= seg_boot_stack_base + 12K + (pid+1)*256
178
179	boot_to_kernel_init:
180
181	# all processors initialise SCHED register with boot_schedulers_paddr[pid]
182	mfc0 k0, CP0_PROCID
183	andi k0, k0, 0xFFF
184	sll k0, k0, 2 # k0 <= 4*pid
185	la k1, boot_schedulers_paddr
186	addu k1, k1, k0 # k1 <= &boot_scheduler_paddr[pid]
187	lw k1, 0(k1)
188	mtc0 k1, CP0_SCHED
189
190	# all processors initialize PTPR register with boot_ptabs_paddr[0]
191	la k1, boot_ptabs_paddr
192	lw k1, 0(k1)
193	srl k1, k1, 13
194	mtc2 k1, CP2_PTPR
195
196	# all processors activate MMU
197	li k1, 0xF
198	mtc2 k1, CP2_MODE
199
200	# all processors jump to kernel_init
201	la k0, seg_kernel_init_base
202	j k0
203	nop
204
205	boot_error_string: .asciiz "\n[BOOT] Fatal Error at cycle "
206	boot_pid_string: .asciiz " PID = "
207	boot_sr_string: .asciiz " SR = "
208	boot_cr_string: .asciiz " CR = "
209	boot_epc_string: .asciiz " EPC = "
210	boot_bar_string: .asciiz " BAR = "
211	boot_lf_string: .asciiz "\n"
212
213	boot_tty0_lock: .word 0
214
215	.set reorder
216
217

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