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reset.S @ 255

Last change on this file since 255 was 249, checked in by alain, 11 years ago
Various modifications to support IO Bridge, and MEMC configuration interface.
File size: 6.0 KB

Line
1	/********************************************************************************/
2	/* File : reset.S */
3	/* Author : Alain Greiner & Mohamed karaoui */
4	/* Date : 03/06/2012 */
5	/********************************************************************************/
6	/* This boot code is for a multi-cluster, multi-processor architecture, */
7	/* running one or several multi-tasks software application(s) defined in */
8	/* the mapping_info data-structure. */
9	/* Procesor 0 uses the mapping_info data structure to statically initialize */
10	/* the kernel structures: */
11	/* - build page tables for all vspaces */
12	/* - initializes the vobjs not initialized by GCC */
13	/* - initialize the schedulers and task contexts for all processeurs */
14	/* - initialize the peripherals */
15	/* Other processors are waiting until the mapping_info signature has been */
16	/* modified by processor 0. */
17	/* */
18	/* Implementation note: */
19	/* The entry point is 0xbfc00000, but the actual boot code starts at address */
20	/* 0xbfc00500, and a minimal boot exception handler is implemented at address */
21	/* 0xbfc0380. */
22	/********************************************************************************/
23
24	#include <giet_config.h>
25	#include "../sys/mips32_registers.h"
26
27	#define EXCEP_ORG 0x380
28	#define START_ORG 0x500
29
30	#define OUT_MAPPING_SIGNATURE 0xBABEF00D
31
32	.section .boot,"ax",@progbits
33	.align 2
34	.set noreorder
35
36	/********************************************************/
37	/* reset entry point */
38	/* (address 0xBFC00000 imposed by the hardware) */
39	/********************************************************/
40	boot_reset:
41	j boot_start
42	nop
43
44	/*******************************************************/
45	/* handling exceptions in the boot phase */
46	/* (address 0xBFC00380 imposed by the hardware */
47	/*******************************************************/
48	.align 2
49	.org EXCEP_ORG
50
51	boot_excep:
52
53	# get the lock protecting TTY0
54	#la k0, boot_tty0_lock
55	#ll k1, 0(k0)
56	#bnez k1, boot_excep
57	#li k1, 1
58	#sc k1, 0(k0)
59	#beqz k1, boot_excep
60	#nop
61
62	# display error messages on TTY0
63	la a0, boot_error_string
64	jal boot_puts
65	nop
66	mfc0 a0, CP0_TIME
67	jal boot_putd
68	nop
69	la a0, boot_lf_string
70	jal boot_puts
71	nop
72
73	la a0, boot_pid_string
74	jal boot_puts
75	nop
76	mfc0 k0, CP0_PROCID
77	andi a0, k0, 0xFFF
78	jal boot_putd
79	nop
80	la a0, boot_lf_string
81	jal boot_puts
82	nop
83
84	la a0, boot_epc_string
85	jal boot_puts
86	nop
87	mfc0 a0, CP0_EPC
88	jal boot_putx
89	nop
90	la a0, boot_lf_string
91	jal boot_puts
92	nop
93
94	la a0, boot_cr_string
95	jal boot_puts
96	nop
97	mfc0 a0, CP0_CR
98	jal boot_putx
99	nop
100	la a0, boot_lf_string
101	jal boot_puts
102	nop
103
104	la a0, boot_sr_string
105	jal boot_puts
106	nop
107	mfc0 a0, CP0_SR
108	jal boot_putx
109	nop
110	la a0, boot_lf_string
111	jal boot_puts
112	nop
113
114	la a0, boot_bar_string
115	jal boot_puts
116	nop
117	mfc0 a0, CP0_BVAR
118	jal boot_putx
119	nop
120	la a0, boot_lf_string
121	jal boot_puts
122	nop
123
124	# release the lock
125	la k0, boot_tty0_lock
126	li k1, 0
127	sw k1, 0(k0)
128
129	# exit
130	j boot_exit
131	nop
132
133	/*******************************************/
134	/* actual starting point for the boot code */
135	/*******************************************/
136	.align 2
137	.org START_ORG
138
139	boot_start:
140
141	# initialize the proc_time to zero
142	mtc0 $0, CP0_TIME
143
144	# get the procid
145	mfc0 k0, CP0_PROCID
146	andi k0, k0, 0xFFF # no more than 4096 processors
147
148	# Only processor 0 does init
149	bne k0, zero, boot_wait_signature
150	nop
151
152	# Processor 0 get a temporary stack
153	la sp, seg_boot_stack_base
154	addiu sp, sp, 0x3000 # SP <= seg_boot_stack + 12K
155
156	# Processor 0 initialises all kernel structures
157	jal boot_init
158	nop
159
160	# jump to kernel_init
161	j boot_to_kernel_init
162	nop
163
164	boot_wait_signature:
165
166	# all other processors are waiting signature change
167	la k0, seg_mapping_base
168	cache 0x11, 0(k0) # invalidate local cache copy
169	lw k0, 0(k0) # k0 <= mapping_info[0]
170	li k1, OUT_MAPPING_SIGNATURE
171	bne k1, k0, boot_wait_signature
172	nop
173
174	# all other processors initialise SP register: temporary stack of 256 bytes
175	la sp, seg_boot_stack_base
176	addiu sp, sp, 0x3100
177	mfc0 k0, CP0_PROCID
178	andi k0, k0, 0xFFF
179	sll k0, k0, 8
180	addu sp, sp, k0 # SP <= seg_boot_stack_base + 12K + (pid+1)*256
181
182	boot_to_kernel_init:
183
184	# all processors initialise the CP0 SCHED register
185	# SCHED contains the scheduler virtual base address
186	mfc0 k0, CP0_PROCID
187	andi k0, k0, 0xFFF
188	sll k0, k0, 2 # k0 <= 4*pid
189	la k1, boot_schedulers
190	addu k1, k1, k0 # k1 <= &boot_schedulers[pid]
191	lw k0, 0(k1)
192	mtc0 k0, CP0_SCHED
193
194	# all processors initialize the CP2 PTPR register
195	# At this stage, all PTPR registers contain the physical base
196	# address (13 bits right shifted) of the page table for vspace[0]
197	la k1, boot_ptabs_paddr
198	lw k0, 0(k1) # k0 <= paddr_lsb
199	lw k1, 4(k1) # k1 <= paddr_msb
200	srl k0, k0, 13 # k0 <= paddr_lsb shifted
201	sll k1, k1, 19 # k1 <= paddr_msb shifted
202	or k0, k0, k1
203	mtc2 k0, CP2_PTPR
204
205	# all processors activate MMU (already done for processor 0)
206	li k1, 0xF
207	mtc2 k1, CP2_MODE
208
209	# all processors jump to kernel_init
210	la k0, seg_kernel_init_base
211	j k0
212	nop
213
214	boot_error_string: .asciiz "\n[BOOT] Fatal Error at cycle "
215	boot_pid_string: .asciiz " PID = "
216	boot_sr_string: .asciiz " SR = "
217	boot_cr_string: .asciiz " CR = "
218	boot_epc_string: .asciiz " EPC = "
219	boot_bar_string: .asciiz " BAR = "
220	boot_lf_string: .asciiz "\n"
221
222	.set reorder
223
224

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