| 1 | /********************************************************************************/ |
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| 2 | /* File : reset.S */ |
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| 3 | /* Author : Alain Greiner & Mohamed karaoui */ |
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| 4 | /* Date : 03/06/2012 */ |
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| 5 | /********************************************************************************/ |
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| 6 | /* This boot code is for a multi-cluster, multi-processor architecture, */ |
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| 7 | /* running one or several multi-tasks software application(s) defined in */ |
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| 8 | /* the mapping_info data-structure. */ |
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| 9 | /* Procesor 0 uses the mapping_info data structure to build all page tables */ |
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| 10 | /* before jumping to the kernel_init code. */ |
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| 11 | /* Other processors are waiting until the mapping_info signature has been */ |
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| 12 | /* modified by processor 0 (done while executing kernel_init code). */ |
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| 13 | /* Implementation note: */ |
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| 14 | /* The entry point is 0xbfc00000, but the actual boot code starts at address */ |
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| 15 | /* 0xbfc00500, and a minimal boot exception handler is implemented at address */ |
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| 16 | /* 0xbfc0380. */ |
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| 17 | /********************************************************************************/ |
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| 18 | |
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| 19 | #include <giet_config.h> |
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| 20 | #include "../sys/mips32_registers.h" |
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| 21 | |
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| 22 | #define EXCEP_ORG 0x380 |
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| 23 | #define START_ORG 0x500 |
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| 24 | |
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| 25 | #define OUT_MAPPING_SIGNATURE 0xBABEF00D |
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| 26 | |
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| 27 | .section .boot,"ax",@progbits |
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| 28 | .align 2 |
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| 29 | .set noreorder |
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| 30 | |
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| 31 | /********************************************************/ |
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| 32 | /* reset entry point */ |
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| 33 | /* (address 0xBFC00000 imposed by the hardware) */ |
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| 34 | /********************************************************/ |
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| 35 | boot_reset: |
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| 36 | j boot_start |
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| 37 | nop |
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| 38 | |
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| 39 | /*******************************************************/ |
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| 40 | /* handling exceptions in the boot phase */ |
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| 41 | /* (address 0xBFC00380 imposed by the hardware */ |
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| 42 | /*******************************************************/ |
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| 43 | .align 2 |
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| 44 | .org EXCEP_ORG |
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| 45 | boot_excep: |
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| 46 | la a0, boot_error_string |
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| 47 | jal boot_puts |
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| 48 | nop |
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| 49 | mfc0 a0, CP0_TIME |
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| 50 | jal boot_putw |
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| 51 | nop |
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| 52 | la a0, boot_lf_string |
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| 53 | jal boot_puts |
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| 54 | nop |
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| 55 | |
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| 56 | la a0, boot_pid_string |
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| 57 | jal boot_puts |
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| 58 | nop |
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| 59 | mfc0 k0, CP0_PROCID |
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| 60 | andi a0, k0, 0xFFF |
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| 61 | jal boot_putw |
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| 62 | nop |
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| 63 | la a0, boot_lf_string |
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| 64 | jal boot_puts |
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| 65 | nop |
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| 66 | |
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| 67 | la a0, boot_epc_string |
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| 68 | jal boot_puts |
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| 69 | nop |
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| 70 | mfc0 a0, CP0_EPC |
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| 71 | jal boot_putw |
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| 72 | nop |
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| 73 | la a0, boot_lf_string |
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| 74 | jal boot_puts |
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| 75 | nop |
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| 76 | |
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| 77 | la a0, boot_cr_string |
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| 78 | jal boot_puts |
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| 79 | nop |
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| 80 | mfc0 a0, CP0_CR |
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| 81 | jal boot_putw |
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| 82 | nop |
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| 83 | la a0, boot_lf_string |
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| 84 | jal boot_puts |
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| 85 | nop |
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| 86 | |
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| 87 | la a0, boot_sr_string |
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| 88 | jal boot_puts |
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| 89 | nop |
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| 90 | mfc0 a0, CP0_SR |
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| 91 | jal boot_putw |
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| 92 | nop |
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| 93 | la a0, boot_lf_string |
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| 94 | jal boot_puts |
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| 95 | nop |
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| 96 | |
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| 97 | la a0, boot_bar_string |
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| 98 | jal boot_puts |
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| 99 | nop |
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| 100 | mfc0 a0, CP0_BAR |
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| 101 | jal boot_putw |
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| 102 | nop |
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| 103 | la a0, boot_lf_string |
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| 104 | jal boot_puts |
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| 105 | nop |
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| 106 | |
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| 107 | j boot_exit |
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| 108 | nop |
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| 109 | |
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| 110 | /*******************************************/ |
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| 111 | /* actual starting point for the boot code */ |
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| 112 | /*******************************************/ |
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| 113 | .align 2 |
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| 114 | .org START_ORG |
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| 115 | |
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| 116 | boot_start: |
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| 117 | /* get the procid */ |
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| 118 | mfc0 k0, CP0_PROCID |
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| 119 | andi k0, k0, 0xFFF /* no more than 4096 processors... */ |
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| 120 | |
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| 121 | /* Only processor 0 does init */ |
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| 122 | bne k0, zero, boot_wait_signature |
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| 123 | nop |
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| 124 | |
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| 125 | /* Processor 0 get a temporary stack */ |
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| 126 | la sp, seg_boot_stack_base |
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| 127 | addiu sp, sp, 0x3000 /* SP <= seg_boot_stack + 12K */ |
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| 128 | |
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| 129 | /* Processor 0 initialises all Page Tables */ |
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| 130 | jal boot_pt_init |
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| 131 | nop |
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| 132 | |
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| 133 | /* jump to kernel_init */ |
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| 134 | j boot_to_kernel_init |
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| 135 | nop |
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| 136 | |
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| 137 | boot_wait_signature: |
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| 138 | |
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| 139 | /* all other processors are waiting signature change */ |
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| 140 | la k0, seg_mapping_base |
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| 141 | cache 0x11, 0(k0) /* invalidate local cache copy */ |
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| 142 | lw k0, 0(k0) /* k0 <= mapping_info[0] */ |
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| 143 | li k1, OUT_MAPPING_SIGNATURE |
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| 144 | bne k1, k0, boot_wait_signature |
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| 145 | nop |
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| 146 | |
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| 147 | /* all other processors get a temporary stack of 256 bytes */ |
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| 148 | la sp, seg_boot_stack_base |
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| 149 | addiu sp, sp, 0x3100 |
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| 150 | mfc0 k0, CP0_PROCID |
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| 151 | andi k0, k0, 0xFFF |
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| 152 | sll k0, k0, 8 |
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| 153 | addu sp, sp, k0 /* SP <= seg_boot_stack_base + 12K + (pid+1)*256 */ |
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| 154 | |
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| 155 | boot_to_kernel_init: |
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| 156 | |
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| 157 | /* all processors initialize PTPR with PTAB[0] */ |
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| 158 | la k1, _ptabs |
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| 159 | lw k1, 0(k1) |
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| 160 | srl k1, k1, 13 |
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| 161 | mtc2 k1, CP2_PTPR /* PTPR <= _ptabs[0] */ |
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| 162 | |
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| 163 | /* all processors activate MMU */ |
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| 164 | li k1, 0xF |
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| 165 | mtc2 k1, CP2_MODE /* MODE register */ |
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| 166 | |
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| 167 | /* jump to kernel_init */ |
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| 168 | la k0, seg_kernel_init_base |
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| 169 | j k0 |
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| 170 | nop |
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| 171 | |
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| 172 | boot_error_string: .asciiz "\n[BOOT] Fatal Error in reset.S at cycle " |
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| 173 | boot_pid_string: .asciiz " PID = " |
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| 174 | boot_sr_string: .asciiz " SR = " |
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| 175 | boot_cr_string: .asciiz " CR = " |
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| 176 | boot_epc_string: .asciiz " EPC = " |
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| 177 | boot_bar_string: .asciiz " BAR = " |
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| 178 | boot_lf_string: .asciiz "\n" |
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| 179 | |
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| 180 | .set reorder |
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| 181 | |
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| 182 | |
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