source: soft/giet_vm/giet_drivers/iob_driver.h @ 315

///////////////////////////////////////////////////////////////////////////////////
// File     : iob_driver.h
// Date     : 01/11/2013
// Author   : alain greiner
// Copyright (c) UPMC-LIP6
///////////////////////////////////////////////////////////////////////////////////

#ifndef _GIET_IOB_DRIVER_H_
#define _GIET_IOB_DRIVER_H_

///////////////////////////////////////////////////////////////////////////////////
// vci_io_bridge : registers offsets and iommu error codes
///////////////////////////////////////////////////////////////////////////////////

enum IOB_registers 
{
    IOB_IOMMU_PTPR       = 0,      // R/W : Page Table Pointer Register
    IOB_IOMMU_ACTIVE     = 1,      // R/W : IOMMU activated if not 0
    IOB_IOMMU_BVAR       = 2,      // R   : Bad Virtual Address (unmapped) 
    IOB_IOMMU_ETR        = 3,      // R   : Error Type 
    IOB_IOMMU_BAD_ID     = 4,      // R   : Faulty Peripheral Index (SRCID)
    IOB_INVAL_PTE        = 5,      // W   : Invalidate a PTE (virtual address)
    IOB_WTI_ENABLE       = 6,      // R/W : Enable WTIs (both IOMMU and peripherals)
    IOB_WTI_ADDR_LO      = 7,      // W/R : 32 LSB bits for IOMMU WTI
    IOB_WTI_ADDR_HI      = 8,      // W/R : 32 MSB bits for IOMMU WTI
    IOB_XICU_BASE        = 9,      // R/W : XICU pbase address in cluster 0
    IOB_XICU_SIZE        = 10,     // R/W : XICU segment size 
};

enum mmu_error_type_e 
{
    MMU_NONE                      = 0x0000, // None
    MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write access to a non writable page 
    MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write Bus Error accessing Table 1       
    MMU_READ_PT1_UNMAPPED             = 0x1001, // Read  Page fault on Page Table 1     
    MMU_READ_PT2_UNMAPPED             = 0x1002, // Read  Page fault on Page Table 2  
    MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read  Bus Error in Table1 access      
    MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read  Bus Error in Table2 access         
    MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read  Bus Error in cache access 
};


///////////////////////////////////////////////////////////////////////////////////
// TSAR IOB access functions
///////////////////////////////////////////////////////////////////////////////////

extern void _iob_inval_tlb_entry( unsigned int cluster_xy,
                                  unsigned int vaddr );

extern void _iob_set_iommu_ptpr(  unsigned int cluster_xy,
                                  unsigned int value );

extern void _iob_set_xicu_base(   unsigned int cluster_xy,
                                  unsigned int value );

extern void _iob_set_xicu_size(   unsigned int cluster_xy,
                                  unsigned int value );

///////////////////////////////////////////////////////////////////////////////////

#endif

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