1 | /////////////////////////////////////////////////////////////////////////////////// |
---|
2 | // File : kernel_init.c |
---|
3 | // Date : 26/05/2012 |
---|
4 | // Authors : alain greiner & mohamed karaoui |
---|
5 | // Copyright (c) UPMC-LIP6 |
---|
6 | //////////////////////////////////////////////////////////////////////////////////// |
---|
7 | // The kernel_init.c file is part of the GIET-VM nano-kernel. |
---|
8 | // |
---|
9 | // This nano-kernel has been written for the MIPS32 processor. |
---|
10 | // The virtual adresses are on 32 bits and use the (unsigned int) type, but the |
---|
11 | // physicals addresses can have up to 40 bits, and use the (unsigned long long) type. |
---|
12 | // It natively supports clusterised shared mmemory multi-processors architectures, |
---|
13 | // where each processor is identified by a composite index [x,y,lpid], |
---|
14 | // and where there is one physical memory bank per cluster. |
---|
15 | // |
---|
16 | // The kernel_init() function is executed in parallel by all procesors, |
---|
17 | // and completes the system initialisation that has been started by processor[0,0,0] |
---|
18 | // in the boot_init() function. It makes the following assuptions, regarding the work |
---|
19 | // bone by the boot code: |
---|
20 | // |
---|
21 | // 1) The page tables associated to the various vspaces have been build |
---|
22 | // in physical memory, and can be used by the kernel code. |
---|
23 | // |
---|
24 | // 2) All schedulers (this include all task contexts) have been initialised, |
---|
25 | // Both the virtual and the physical base addresses of the page tables |
---|
26 | // are available in the CTX_PTAB and CTX_PTPR slots. |
---|
27 | // |
---|
28 | // 3) The CP0_SCHED register of each processor contains a pointer on its |
---|
29 | // private scheduler (virtual address). |
---|
30 | // |
---|
31 | // 4) The CP2_PTPR register of each processor contains a pointer on |
---|
32 | // the vspace_0 page table (physical address>>13). |
---|
33 | // |
---|
34 | // 5) For all processors, the MMU is activated (CP2_MODE contains 0xF). |
---|
35 | // |
---|
36 | // This code must be loaded in .kinit section, in order to control seg_kinit_base, |
---|
37 | // as this address is used by the boot code to jump into kernel code. |
---|
38 | // |
---|
39 | // Each processor performs the following actions: |
---|
40 | // 1/ contribute to _schedulers_paddr[] array initialisation. |
---|
41 | // 2/ contribute to _ptabs_paddr[] and _ptabs_vaddr arrays initialisation |
---|
42 | // 3/ completes task context initialisation for ech allocated task |
---|
43 | // 4/ compute and set the ICU mask for its private ICU channel |
---|
44 | // 5/ initialise its private TICK timer (if tasks > 0) |
---|
45 | // 6/ initialise the "idle" task context in its private scheduler |
---|
46 | // 7/ initialise SP, SR, PTPR, EPC registers and jump to user code with an eret. |
---|
47 | //////////////////////////////////////////////////////////////////////////////////// |
---|
48 | |
---|
49 | #include <giet_config.h> |
---|
50 | |
---|
51 | // kernel libraries |
---|
52 | #include <utils.h> |
---|
53 | #include <fat32.h> |
---|
54 | |
---|
55 | //for peripheral initialisation |
---|
56 | #include <dma_driver.h> |
---|
57 | #include <fbf_driver.h> |
---|
58 | #include <tty_driver.h> |
---|
59 | #include <icu_driver.h> |
---|
60 | #include <xcu_driver.h> |
---|
61 | #include <ioc_driver.h> |
---|
62 | #include <mmc_driver.h> |
---|
63 | #include <mwr_driver.h> |
---|
64 | #include <nic_driver.h> |
---|
65 | #include <tim_driver.h> |
---|
66 | |
---|
67 | #include <ctx_handler.h> |
---|
68 | #include <irq_handler.h> |
---|
69 | |
---|
70 | #include <mapping_info.h> |
---|
71 | #include <mips32_registers.h> |
---|
72 | |
---|
73 | /////////////////////////////////////////////////////////////////////////////////// |
---|
74 | // array of pointers on the page tables (virtual addresses) |
---|
75 | /////////////////////////////////////////////////////////////////////////////////// |
---|
76 | |
---|
77 | __attribute__((section (".kdata"))) |
---|
78 | unsigned int _ptabs_vaddr[GIET_NB_VSPACE_MAX]; // virtual addresses |
---|
79 | |
---|
80 | __attribute__((section (".kdata"))) |
---|
81 | unsigned int _ptabs_ptprs[GIET_NB_VSPACE_MAX]; // physical addresses >> 13 |
---|
82 | |
---|
83 | /////////////////////////////////////////////////////////////////////////////////// |
---|
84 | // array of pointers on the schedulers (physical addresses) |
---|
85 | /////////////////////////////////////////////////////////////////////////////////// |
---|
86 | |
---|
87 | __attribute__((section (".kdata"))) |
---|
88 | static_scheduler_t* _schedulers[NB_PROCS_MAX<<(X_WIDTH+Y_WIDTH)]; // virtual addresses |
---|
89 | |
---|
90 | //////////////////////////////////////////////////////////////////////////////////// |
---|
91 | // staks for the "idle" tasks (512 bytes for each processor) |
---|
92 | //////////////////////////////////////////////////////////////////////////////////// |
---|
93 | |
---|
94 | __attribute__((section (".kdata"))) |
---|
95 | unsigned int _idle_stack[X_SIZE * Y_SIZE * NB_PROCS_MAX * 128 ]; |
---|
96 | |
---|
97 | //////////////////////////////////////////////////////////////////////////////////// |
---|
98 | // Synchonisation Barrier before jumping to user code |
---|
99 | //////////////////////////////////////////////////////////////////////////////////// |
---|
100 | |
---|
101 | __attribute__((section (".kdata"))) |
---|
102 | unsigned int _init_barrier = 0; |
---|
103 | |
---|
104 | /////////////////////////////////////////////////////////////////////////////////// |
---|
105 | __attribute__((section (".kinit"))) void kernel_init() |
---|
106 | { |
---|
107 | unsigned int global_pid = _get_procid(); |
---|
108 | unsigned int cluster_xy = global_pid / NB_PROCS_MAX; |
---|
109 | unsigned int x = cluster_xy >> Y_WIDTH; |
---|
110 | unsigned int y = cluster_xy & ((1<<Y_WIDTH)-1); |
---|
111 | unsigned int lpid = global_pid % NB_PROCS_MAX; |
---|
112 | unsigned int nprocs = TOTAL_PROCS; |
---|
113 | unsigned int pid = ((( x * Y_SIZE) + y) * NB_PROCS_MAX) + lpid; |
---|
114 | // unsigned int pid = _get_id(i n_procs ); |
---|
115 | |
---|
116 | // This last initialisation phase is done sequencially: |
---|
117 | while( pid != _init_barrier ) asm volatile ( "nop" ); |
---|
118 | |
---|
119 | // Step 1 : each processor get its scheduler virtual address |
---|
120 | // and contribute to initialise the _schedulers[] array |
---|
121 | |
---|
122 | static_scheduler_t* psched = (static_scheduler_t*)_get_sched(); |
---|
123 | unsigned int tasks = psched->tasks; |
---|
124 | |
---|
125 | _schedulers[global_pid] = psched; |
---|
126 | |
---|
127 | #if GIET_DEBUG_INIT |
---|
128 | _printf("\n[GIET DEBUG INIT] Processor[%d,%d,%d] starts kernel init\n" |
---|
129 | " - scheduler vbase = %x\n" |
---|
130 | " - tasks = %d\n", |
---|
131 | x, y, lpid, (unsigned int)psched, tasks ); |
---|
132 | #endif |
---|
133 | |
---|
134 | // step 2 : each processor that is allocated at least one task loops |
---|
135 | // on all allocated tasks: |
---|
136 | // - contributes to _ptabs_vaddr[] & _ptabs_ptprs[] initialisation. |
---|
137 | // - set CTX_RA slot with the kernel _ctx_eret() virtual address. |
---|
138 | // - set CTX_EPC slot that must contain the task entry point, |
---|
139 | // and contain only at this point the virtual address of the memory |
---|
140 | // location containing this entry point. We must switch the PTPR |
---|
141 | // to use the page table corresponding to the task. |
---|
142 | |
---|
143 | unsigned int ltid; |
---|
144 | |
---|
145 | for (ltid = 0; ltid < tasks; ltid++) |
---|
146 | { |
---|
147 | unsigned int vsid = _get_task_slot( global_pid, ltid , CTX_VSID_ID ); |
---|
148 | unsigned int ptab = _get_task_slot( global_pid, ltid , CTX_PTAB_ID ); |
---|
149 | unsigned int ptpr = _get_task_slot( global_pid, ltid , CTX_PTPR_ID ); |
---|
150 | |
---|
151 | // initialize PTABS arrays |
---|
152 | _ptabs_vaddr[vsid] = ptab; |
---|
153 | _ptabs_ptprs[vsid] = ptpr; |
---|
154 | |
---|
155 | #if GIET_DEBUG_INIT |
---|
156 | _printf("\n[GIET DEBUG INIT] Processor[%d,%d,%d] contributes to PTABS arrays\n" |
---|
157 | " - ptabs_vaddr[%d] = %x / ptpr_paddr[%d] = %l\n", |
---|
158 | x, y, lpid, |
---|
159 | vsid, ptab, vsid, ((unsigned long long)ptpr)<<13 ); |
---|
160 | #endif |
---|
161 | |
---|
162 | // set the ptpr to use the task page table |
---|
163 | asm volatile( "mtc2 %0, $0 \n" |
---|
164 | : : "r" (ptpr) ); |
---|
165 | |
---|
166 | // compute ctx_ra |
---|
167 | unsigned int ctx_ra = (unsigned int)(&_ctx_eret); |
---|
168 | _set_task_slot( global_pid, ltid, CTX_RA_ID, ctx_ra ); |
---|
169 | |
---|
170 | // compute ctx_epc |
---|
171 | unsigned int* ptr = (unsigned int*)_get_task_slot( global_pid, ltid, CTX_EPC_ID ); |
---|
172 | _set_task_slot( global_pid, ltid, CTX_EPC_ID, *ptr ); |
---|
173 | |
---|
174 | #if GIET_DEBUG_INIT |
---|
175 | _printf("\n[GIET DEBUG INIT] Processor[%d,%d,%d] updates context for task %d\n" |
---|
176 | " - ctx_epc = %x\n" |
---|
177 | " - ctx_ra = %x\n", |
---|
178 | x, y, lpid, ltid, |
---|
179 | _get_task_slot( global_pid, ltid, CTX_EPC_ID ), |
---|
180 | _get_task_slot( global_pid, ltid, CTX_RA_ID ) ); |
---|
181 | #endif |
---|
182 | |
---|
183 | } // end for tasks |
---|
184 | |
---|
185 | // step 4 : compute and set ICU or XCU masks |
---|
186 | |
---|
187 | unsigned int isr_switch_index = 0xFFFFFFFF; |
---|
188 | unsigned int hwi_mask = 0; |
---|
189 | unsigned int pti_mask = 0; |
---|
190 | unsigned int wti_mask = 0; |
---|
191 | unsigned int irq_id; // IN_IRQ index |
---|
192 | unsigned int entry; // interrupt vector entry |
---|
193 | |
---|
194 | for (irq_id = 0; irq_id < 32; irq_id++) |
---|
195 | { |
---|
196 | entry = psched->hwi_vector[irq_id]; |
---|
197 | if ( entry & 0x80000000 ) hwi_mask = hwi_mask | (1<<irq_id); |
---|
198 | if ( (entry & 0x0000FFFF) == ISR_TICK ) isr_switch_index = irq_id; |
---|
199 | |
---|
200 | entry = psched->pti_vector[irq_id]; |
---|
201 | if ( entry & 0x80000000 ) pti_mask = pti_mask | (1<<irq_id); |
---|
202 | if ( (entry & 0x0000FFFF) == ISR_TICK ) isr_switch_index = irq_id; |
---|
203 | |
---|
204 | entry = psched->wti_vector[irq_id]; |
---|
205 | if ( entry & 0x80000000 ) wti_mask = wti_mask | (1<<irq_id); |
---|
206 | if ( (entry & 0x0000FFFF) == ISR_TICK ) isr_switch_index = irq_id; |
---|
207 | } |
---|
208 | |
---|
209 | #if GIET_DEBUG_INIT |
---|
210 | _printf("\n[GIET DEBUG INIT] Processor[%d,%d,%d] sets XCU masks\n" |
---|
211 | " - ICU HWI_MASK = %x\n" |
---|
212 | " - ICU WTI_MASK = %x\n" |
---|
213 | " - ICU PTI_MASK = %x\n", |
---|
214 | x, y, lpid, hwi_mask, wti_mask, pti_mask ); |
---|
215 | #endif |
---|
216 | |
---|
217 | unsigned int channel = lpid * IRQ_PER_PROCESSOR; |
---|
218 | |
---|
219 | #if USE_XICU |
---|
220 | _xcu_set_mask( cluster_xy, channel, hwi_mask, IRQ_TYPE_HWI ); |
---|
221 | _xcu_set_mask( cluster_xy, channel, wti_mask, IRQ_TYPE_WTI ); |
---|
222 | _xcu_set_mask( cluster_xy, channel, pti_mask, IRQ_TYPE_PTI ); |
---|
223 | #else |
---|
224 | _icu_set_mask( cluster_xy, channel, hwi_mask ); |
---|
225 | #endif |
---|
226 | |
---|
227 | // step 5 : start TICK timer if at least one task |
---|
228 | if (tasks > 0) |
---|
229 | { |
---|
230 | // one ISR_TICK must be defined for each proc |
---|
231 | if (isr_switch_index == 0xFFFFFFFF) |
---|
232 | { |
---|
233 | _printf("\n[GIET ERROR] ISR_TICK not found for processor[%d,%d,%d]\n", |
---|
234 | x, y, lpid ); |
---|
235 | _exit(); |
---|
236 | } |
---|
237 | |
---|
238 | // start system timer |
---|
239 | |
---|
240 | #if USE_XICU |
---|
241 | _xcu_timer_start( cluster_xy, isr_switch_index, GIET_TICK_VALUE ); |
---|
242 | #else |
---|
243 | _timer_start( cluster_xy, isr_switch_index, GIET_TICK_VALUE ); |
---|
244 | #endif |
---|
245 | |
---|
246 | } |
---|
247 | |
---|
248 | #if GIET_DEBUG_INIT |
---|
249 | _printf("\n[GIET DEBUG INIT] Processor[%d,%d,%d] starts TICK timer\n", |
---|
250 | x, y, lpid ); |
---|
251 | #endif |
---|
252 | |
---|
253 | // step 6 : each processor updates the idle_task context: |
---|
254 | // (only CTX_SP, CTX_RA, CTX_EPC). |
---|
255 | // The stack size is 512 bytes, reserved in seg_kdata. |
---|
256 | // The PTPR register, the CTX_PTPR and CTX_PTAB slots |
---|
257 | // have been initialised in boot code. |
---|
258 | |
---|
259 | unsigned int p = ((x * Y_SIZE) + y) * NB_PROCS_MAX + lpid; |
---|
260 | |
---|
261 | unsigned int stack = (unsigned int)_idle_stack + ((p + 1)<<9); |
---|
262 | |
---|
263 | _set_task_slot( global_pid, IDLE_TASK_INDEX, CTX_SP_ID, stack); |
---|
264 | _set_task_slot( global_pid, IDLE_TASK_INDEX, CTX_RA_ID, (unsigned int) &_ctx_eret); |
---|
265 | _set_task_slot( global_pid, IDLE_TASK_INDEX, CTX_EPC_ID, (unsigned int) &_idle_task); |
---|
266 | |
---|
267 | #if GIET_DEBUG_INIT |
---|
268 | _printf("\n[GIET DEBUG INIT] Processor[%d,%d,%d] initializes IDLE task\n", |
---|
269 | x, y, lpid ); |
---|
270 | #endif |
---|
271 | |
---|
272 | // step 7 : when all processors reach the synchronisation barrier, |
---|
273 | // each processor set registers SP, SR, PTPR, EPC, |
---|
274 | // with the values corresponding to the first allocated task, |
---|
275 | // or to the idle_task if there is no task allocated, |
---|
276 | // and jump to user code |
---|
277 | |
---|
278 | if (tasks == 0) |
---|
279 | { |
---|
280 | ltid = IDLE_TASK_INDEX; |
---|
281 | |
---|
282 | _printf("\n[GIET WARNING] No task allocated to processor[%d,%d,%d]\n", |
---|
283 | x, y, lpid ); |
---|
284 | } |
---|
285 | else |
---|
286 | { |
---|
287 | ltid = 0; |
---|
288 | } |
---|
289 | |
---|
290 | unsigned int sp_value = _get_task_slot(global_pid, ltid, CTX_SP_ID); |
---|
291 | unsigned int sr_value = _get_task_slot(global_pid, ltid, CTX_SR_ID); |
---|
292 | unsigned int ptpr_value = _get_task_slot(global_pid, ltid, CTX_PTPR_ID); |
---|
293 | unsigned int epc_value = _get_task_slot(global_pid, ltid, CTX_EPC_ID); |
---|
294 | |
---|
295 | _printf("\n[GIET DEBUG INIT] Processor[%d,%d,%d] reach barrier at cycle %d\n", |
---|
296 | x, y, lpid, _get_proctime() ); |
---|
297 | |
---|
298 | /* |
---|
299 | unsigned int* pcount = &_init_barrier; |
---|
300 | unsigned int count; |
---|
301 | |
---|
302 | // increment barrier counter with atomic LL/SC |
---|
303 | asm volatile ( "_init_barrier_loop: \n" |
---|
304 | "ll %0, 0(%1) \n" |
---|
305 | "addi $3, %0, 1 \n" |
---|
306 | "sc $3, 0(%1) \n" |
---|
307 | "beqz $3, _init_barrier_loop \n" |
---|
308 | "nop \n" |
---|
309 | : "=&r"(count) |
---|
310 | : "r"(pcount) |
---|
311 | : "$3" ); |
---|
312 | |
---|
313 | // busy waiting until all processors synchronized |
---|
314 | while ( *pcount != nprocs ) asm volatile ("nop"); |
---|
315 | */ |
---|
316 | |
---|
317 | // increment barrier counter |
---|
318 | _init_barrier++; |
---|
319 | |
---|
320 | // busy waiting until all processors synchronized |
---|
321 | while ( _init_barrier != nprocs ) asm volatile ("nop"); |
---|
322 | |
---|
323 | /* |
---|
324 | _printf("\n[GIET] Processor[%d,%d,%d] jumps to user code at cycle %d\n", |
---|
325 | x, y, lpid, _get_proctime() ); |
---|
326 | */ |
---|
327 | |
---|
328 | // set registers and jump to user code |
---|
329 | asm volatile ( "move $29, %0 \n" /* SP <= ctx[CTX_SP_ID] */ |
---|
330 | "mtc0 %1, $12 \n" /* SR <= ctx[CTX_SR_ID] */ |
---|
331 | "mtc2 %2, $0 \n" /* PTPR <= ctx[CTX_PTPR] */ |
---|
332 | "mtc0 %3, $14 \n" /* EPC <= ctx[CTX_EPC] */ |
---|
333 | "eret \n" /* jump to user code */ |
---|
334 | "nop \n" |
---|
335 | : |
---|
336 | : "r"(sp_value), "r"(sr_value), "r"(ptpr_value), "r"(epc_value) |
---|
337 | : "$29" ); |
---|
338 | |
---|
339 | } // end kernel_init() |
---|
340 | |
---|
341 | |
---|
342 | // Local Variables: |
---|
343 | // tab-width: 4 |
---|
344 | // c-basic-offset: 4 |
---|
345 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
346 | // indent-tabs-mode: nil |
---|
347 | // End: |
---|
348 | // vim: filetype=c:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
349 | |
---|