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source: soft/giet_vm/giet_python/mapping.py @ 541

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1	#!/usr/bin/env python
2
3	import sys
4
5	###################################################################################
6	# file : giet_mapping.py
7	# date : april 2014
8	# author : Alain Greiner
9	###################################################################################
10	# This file contains the classes required to define a mapping for the GIET_VM.
11	# - A 'Mapping' contains a set of 'Cluster' (hardware architecture)
12	# a set of 'Vseg' (kernel glogals virtual segments)
13	# a set of 'Vspace' (one or several user applications)
14	# - A 'Cluster' contains a set of 'Pseg' (physical segments in cluster)
15	# a set of 'Proc' (processors in cluster)
16	# a set of 'Periph' (peripherals in cluster)
17	# - A 'Vspace' contains a set of 'Vseg' (user virtual segments)
18	# a set of 'Task' (user parallel tasks)
19	# - A 'Periph' contains a set of 'Irq' (only for XCU and PIC types )
20	###################################################################################
21	# Implementation Note
22	# The objects used to describe a mapping are distributed in the PYTHON structure:
23	# For example the psegs set is split in several subsets (one subset per cluster),
24	# or the tasks set is split in several subsets (one subset per vspace), etc...
25	# In the C binary data structure used by the giet_vm, all objects of same type
26	# are stored in a linear array (one single array for all psegs for example).
27	# For all objects, we compute and store in the PYTHON object a "global index"
28	# corresponding to the index in this global array, and this index can be used as
29	# a pseudo-pointer to identify a specific object of a given type.
30	###################################################################################
31
32	###################################################################################
33	# Various constants
34	###################################################################################
35
36	PADDR_WIDTH = 40 # number of bits for physical address
37	X_WIDTH = 4 # number of bits encoding x coordinate
38	Y_WIDTH = 4 # number of bits encoding y coordinate
39	P_WIDTH = 4 # number of bits encoding local proc_id
40	VPN_ANTI_MASK = 0x00000FFF # mask vaddr to get offset in small page
41	BPN_MASK = 0xFFE00000 # mask vaddr to get the BPN in big page
42	PERI_INCREMENT = 0x10000 # virtual address increment for replicated vsegs
43	RESET_ADDRESS = 0xBFC00000 # Processor wired boot_address
44	MAPPING_SIGNATURE = 0xDACE2014 # Magic number indicating a valid C BLOB
45
46	###################################################################################
47	# These lists must be consistent with values defined in
48	# mapping_info.h / xml_driver.c /xml_parser.c
49	###################################################################################
50	PERIPHTYPES = [
51	'CMA',
52	'DMA',
53	'FBF',
54	'IOB',
55	'IOC',
56	'MMC',
57	'MWR',
58	'NIC',
59	'ROM',
60	'SIM',
61	'TIM',
62	'TTY',
63	'XCU',
64	'PIC',
65	'DROM',
66	]
67
68	IOCSUBTYPES = [
69	'BDV',
70	'HBA',
71	'SPI',
72	'NONE',
73	]
74
75	MWRSUBTYPES = [
76	'GCD',
77	'DCT',
78	]
79
80	###################################################################################
81	# These lists must be consistent with values defined in
82	# irq_handler.c / irq_handler.h / xml_driver.c / xml_parser.c
83	###################################################################################
84	IRQTYPES = [
85	'HWI',
86	'WTI',
87	'PTI',
88	]
89
90	ISRTYPES = [
91	'ISR_DEFAULT',
92	'ISR_TICK',
93	'ISR_TTY_RX',
94	'ISR_TTY_TX',
95	'ISR_BDV',
96	'ISR_TIMER',
97	'ISR_WAKUP',
98	'ISR_NIC_RX',
99	'ISR_NIC_TX',
100	'ISR_CMA',
101	'ISR_MMC',
102	'ISR_DMA',
103	'ISR_SPI',
104	'ISR_MWR',
105	'ISR_HBA',
106	]
107
108	VSEGTYPES = [
109	'ELF',
110	'BLOB',
111	'PTAB',
112	'PERI',
113	'MWMR', # deprecated
114	'LOCK', # deprecated
115	'BUFFER',
116	'BARRIER', # deprecated
117	'CONST', # deprecated
118	'MEMSPACE', # deprecated
119	'SCHED',
120	'HEAP',
121	]
122
123	VSEGMODES = [
124	'____',
125	'___U',
126	'__W_',
127	'__WU',
128	'_X__',
129	'_X_U',
130	'_XW_',
131	'_XWU',
132	'C___',
133	'C__U',
134	'C_W_',
135	'C_WU',
136	'CX__',
137	'CX_U',
138	'CXW_',
139	'CXWU',
140	]
141
142	PSEGTYPES = [
143	'RAM',
144	'PERI',
145	]
146
147	###################################################################################
148	class Mapping( object ):
149	###################################################################################
150	def __init__( self,
151	name, # mapping name
152	x_size, # number of clusters in a row
153	y_size, # number of clusters in a column
154	nprocs, # max number of processors per cluster
155	x_width = X_WIDTH, # number of bits encoding x coordinate
156	y_width = Y_WIDTH, # number of bits encoding y coordinate
157	p_width = P_WIDTH, # number of bits encoding lpid
158	paddr_width = PADDR_WIDTH, # number of bits for physical address
159	coherence = 1, # hardware cache coherence if non-zero
160	irq_per_proc = 1, # number or IRQs from XCU to processor
161	use_ramdisk = False, # use ramdisk when true
162	x_io = 0, # cluster_io x coordinate
163	y_io = 0, # cluster_io y coordinate
164	peri_increment = PERI_INCREMENT, # address increment for globals
165	reset_address = RESET_ADDRESS, # Processor wired boot_address
166	ram_base = 0, # RAM physical base in cluster[0,0]
167	ram_size = 0 ): # RAM size per cluster (bytes)
168
169	assert ( x_size <= (1<<X_WIDTH) )
170	assert ( y_size <= (1<<Y_WIDTH) )
171	assert ( nprocs <= (1<<P_WIDTH) )
172
173	self.signature = MAPPING_SIGNATURE
174	self.name = name
175	self.name = name
176	self.paddr_width = paddr_width
177	self.coherence = coherence
178	self.x_size = x_size
179	self.y_size = y_size
180	self.nprocs = nprocs
181	self.x_width = x_width
182	self.y_width = y_width
183	self.p_width = p_width
184	self.irq_per_proc = irq_per_proc
185	self.use_ramdisk = use_ramdisk
186	self.x_io = x_io
187	self.y_io = y_io
188	self.peri_increment = peri_increment
189	self.reset_address = reset_address
190	self.ram_base = ram_base
191	self.ram_size = ram_size
192
193	self.total_vspaces = 0
194	self.total_globals = 0
195	self.total_psegs = 0
196	self.total_vsegs = 0
197	self.total_tasks = 0
198	self.total_procs = 0
199	self.total_irqs = 0
200	self.total_periphs = 0
201
202	self.clusters = []
203	self.globs = []
204	self.vspaces = []
205
206	for x in xrange( self.x_size ):
207	for y in xrange( self.y_size ):
208	cluster = Cluster( x , y )
209	cluster.index = (x * self.y_size) + y
210	self.clusters.append( cluster )
211
212	return
213
214	########################## add a ram pseg in a cluster
215	def addRam( self,
216	name, # pseg name
217	base, # pseg base address
218	size ): # pseg length (bytes)
219
220	# computes cluster index and coordinates from the base address
221	paddr_lsb_width = self.paddr_width - self.x_width - self.y_width
222	cluster_xy = base >> paddr_lsb_width
223	x = cluster_xy >> (self.y_width);
224	y = cluster_xy & ((1 << self.y_width) - 1)
225	cluster_id = (x * self.y_size) + y
226
227	assert (base & VPN_ANTI_MASK) == 0
228
229	assert (x < self.x_size) and (y < self.y_size)
230
231	assert ( (base & ((1<<paddr_lsb_width)-1)) == self.ram_base )
232
233	assert ( size == self.ram_size )
234
235	# add one pseg in the mapping
236	pseg = Pseg( name, base, size, x, y, 'RAM' )
237	self.clusters[cluster_id].psegs.append( pseg )
238	pseg.index = self.total_psegs
239	self.total_psegs += 1
240
241	return pseg
242
243	########################## add a peripheral and the associated pseg in a cluster
244	def addPeriph( self,
245	name, # associated pseg name
246	base, # associated pseg base address
247	size, # associated pseg length (bytes)
248	ptype, # peripheral type
249	subtype = 'NONE', # peripheral subtype
250	channels = 1, # number of channels
251	arg0 = 0, # optional argument (semantic depends on ptype)
252	arg1 = 0, # optional argument (semantic depends on ptype)
253	arg2 = 0, # optional argument (semantic depends on ptype)
254	arg3 = 0 ): # optional argument (semantic depends on ptype)
255
256	# computes cluster index and coordinates from the base address
257	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
258	x = cluster_xy >> (self.y_width);
259	y = cluster_xy & ((1 << self.y_width) - 1)
260	cluster_id = (x * self.y_size) + y
261
262	assert (x < self.x_size) and (y < self.y_size)
263
264	assert (base & VPN_ANTI_MASK) == 0
265
266	assert ptype in PERIPHTYPES
267
268	if (ptype == 'IOC'): assert subtype in IOCSUBTYPES
269	if (ptype == 'MWR'): assert subtype in MWRSUBTYPES
270
271	# add one pseg into mapping
272	pseg = Pseg( name, base, size, x, y, 'PERI' )
273	self.clusters[cluster_id].psegs.append( pseg )
274	pseg.index = self.total_psegs
275	self.total_psegs += 1
276
277	# add one periph into mapping
278	periph = Periph( pseg, ptype, subtype, channels, arg0, arg1, arg2, arg3 )
279	self.clusters[cluster_id].periphs.append( periph )
280	periph.index = self.total_periphs
281	self.total_periphs += 1
282
283	return periph
284
285	################################ add an IRQ in a peripheral
286	def addIrq( self,
287	periph, # peripheral containing IRQ (PIC or XCU)
288	index, # peripheral input port index
289	isrtype, # ISR type
290	channel = 0 ): # channel for multi-channels ISR
291
292	assert isrtype in ISRTYPES
293
294	assert index < 32
295
296	# add one irq into mapping
297	irq = Irq( 'HWI', index , isrtype, channel )
298	periph.irqs.append( irq )
299	irq.index = self.total_irqs
300	self.total_irqs += 1
301
302	return irq
303
304	########################## add a processor in a cluster
305	def addProc( self,
306	x, # cluster x coordinate
307	y, # cluster y coordinate
308	lpid ): # processor local index
309
310	assert (x < self.x_size) and (y < self.y_size)
311
312	cluster_id = (x * self.y_size) + y
313
314	# add one proc into mapping
315	proc = Processor( x, y, lpid )
316	self.clusters[cluster_id].procs.append( proc )
317	proc.index = self.total_procs
318	self.total_procs += 1
319
320	return proc
321
322	############################ add one global vseg into mapping
323	def addGlobal( self,
324	name, # vseg name
325	vbase, # virtual base address
326	length, # vseg length (bytes)
327	mode, # CXWU flags
328	vtype, # vseg type
329	x, # destination x coordinate
330	y, # destination y coordinate
331	pseg, # destination pseg name
332	identity = False, # identity mapping required if true
333	local = False, # only mapped in local PTAB if true
334	big = False, # to be mapped in a big physical page
335	binpath = '' ): # pathname for binary code if required
336
337	# two global vsegs must not overlap if they have different names
338	for prev in self.globs:
339	if ( ((prev.vbase + prev.length) > vbase ) and
340	((vbase + length) > prev.vbase) and
341	(prev.name != name) ):
342	print '[genmap error] in addGlobal()'
343	print ' global vseg %s overlap %s' % (name, prev.name)
344	print ' %s : base = %x / size = %x' %( name, vbase, size )
345	print ' %s : base = %x / size = %x' %( prev.name, prev.vbase, prev.size )
346	sys.exit(1)
347
348	# add one vseg into mapping
349	vseg = Vseg( name, vbase, length, mode, vtype, x, y, pseg,
350	identity = identity, local = local, big = big, binpath = binpath )
351
352	self.globs.append( vseg )
353	self.total_globals += 1
354	vseg.index = self.total_vsegs
355	self.total_vsegs += 1
356
357	return
358
359	################################ add a vspace into mapping
360	def addVspace( self,
361	name, # vspace name
362	startname ): # name of vseg containing start_vector
363
364	# add one vspace into mapping
365	vspace = Vspace( name, startname )
366	self.vspaces.append( vspace )
367	vspace.index = self.total_vspaces
368	self.total_vspaces += 1
369
370	return vspace
371
372	################################# add a private vseg in a vspace
373	def addVseg( self,
374	vspace, # vspace containing the vseg
375	name, # vseg name
376	vbase, # virtual base address
377	length, # vseg length (bytes)
378	mode, # CXWU flags
379	vtype, # vseg type
380	x, # destination x coordinate
381	y, # destination y coordinate
382	pseg, # destination pseg name
383	local = False, # only mapped in local PTAB if true
384	big = False, # to be mapped in a big physical page
385	binpath = '' ): # pathname for binary code
386
387	assert mode in VSEGMODES
388
389	assert vtype in VSEGTYPES
390
391	assert (x < self.x_size) and (y < self.y_size)
392
393	# add one vseg into mapping
394	vseg = Vseg( name, vbase, length, mode, vtype, x, y, pseg,
395	identity = False, local = local, big = big, binpath = binpath )
396	vspace.vsegs.append( vseg )
397	vseg.index = self.total_vsegs
398	self.total_vsegs += 1
399
400	return vseg
401
402	################################ add a task in a vspace
403	def addTask( self,
404	vspace, # vspace containing task
405	name, # task name
406	trdid, # task index in vspace
407	x, # destination x coordinate
408	y, # destination y coordinate
409	lpid, # destination processor local index
410	stackname, # name of vseg containing stack
411	heapname, # name of vseg containing heap
412	startid ): # index in start_vector
413
414	assert (x < self.x_size) and (y < self.y_size)
415	assert lpid < self.nprocs
416
417	# add one task into mapping
418	task = Task( name, trdid, x, y, lpid, stackname, heapname, startid )
419	vspace.tasks.append( task )
420	task.index = self.total_tasks
421	self.total_tasks += 1
422
423	return task
424
425	#################################
426	def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array
427
428	byte_stream = bytearray()
429	length = len( s )
430	if length < (nbytes - 1):
431	for b in s:
432	byte_stream.append( b )
433	for x in xrange(nbytes-length):
434	byte_stream.append( '\0' )
435	else:
436	print '[genmap error] in str2bytes()'
437	print ' string %s too long' % s
438	sys.exit(1)
439
440	return byte_stream
441
442	###################################
443	def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array
444
445	byte_stream = bytearray()
446	for n in xrange( nbytes ):
447	byte_stream.append( (val >> (n<<3)) & 0xFF )
448
449	return byte_stream
450
451	################
452	def xml( self ): # compute string for map.xml file generation
453
454	s = '<?xml version="1.0"?>\n\n'
455	s += '<mapping_info signature = "0x%x"\n' % (self.signature)
456	s += ' name = "%s"\n' % (self.name)
457	s += ' x_size = "%d"\n' % (self.x_size)
458	s += ' y_size = "%d"\n' % (self.y_size)
459	s += ' x_width = "%d"\n' % (self.x_width)
460	s += ' y_width = "%d"\n' % (self.y_width)
461	s += ' irq_per_proc = "%d"\n' % (self.irq_per_proc)
462	s += ' use_ramdisk = "%d"\n' % (self.use_ramdisk)
463	s += ' x_io = "%d"\n' % (self.x_io)
464	s += ' y_io = "%d" >\n' % (self.y_io)
465	s += '\n'
466
467	s += ' <clusterset>\n'
468	for x in xrange ( self.x_size ):
469	for y in xrange ( self.y_size ):
470	cluster_id = (x * self.y_size) + y
471	s += self.clusters[cluster_id].xml()
472	s += ' </clusterset>\n'
473	s += '\n'
474
475	s += ' <globalset>\n'
476	for vseg in self.globs: s += vseg.xml()
477	s += ' </globalset>\n'
478	s += '\n'
479
480	s += ' <vspaceset>\n'
481	for vspace in self.vspaces: s += vspace.xml()
482	s += ' </vspaceset>\n'
483
484	s += '</mapping_info>\n'
485	return s
486
487	##########################
488	def cbin( self, verbose ): # C binary structure for map.bin file generation
489
490	byte_stream = bytearray()
491
492	# header
493	byte_stream += self.int2bytes(4, self.signature)
494	byte_stream += self.int2bytes(4, self.x_size)
495	byte_stream += self.int2bytes(4, self.y_size)
496	byte_stream += self.int2bytes(4, self.x_width)
497	byte_stream += self.int2bytes(4, self.y_width)
498	byte_stream += self.int2bytes(4, self.x_io)
499	byte_stream += self.int2bytes(4, self.y_io)
500	byte_stream += self.int2bytes(4, self.irq_per_proc)
501	byte_stream += self.int2bytes(4, self.use_ramdisk)
502	byte_stream += self.int2bytes(4, self.total_globals)
503	byte_stream += self.int2bytes(4, self.total_vspaces)
504	byte_stream += self.int2bytes(4, self.total_psegs)
505	byte_stream += self.int2bytes(4, self.total_vsegs)
506	byte_stream += self.int2bytes(4, self.total_tasks)
507	byte_stream += self.int2bytes(4, self.total_procs)
508	byte_stream += self.int2bytes(4, self.total_irqs)
509	byte_stream += self.int2bytes(4, self.total_periphs)
510	byte_stream += self.str2bytes(32, self.name)
511
512	if ( verbose ):
513	print '\n'
514	print 'name = %s' % self.name
515	print 'signature = %x' % self.signature
516	print 'x_size = %d' % self.x_size
517	print 'y_size = %d' % self.y_size
518	print 'x_width = %d' % self.x_width
519	print 'y_width = %d' % self.y_width
520	print 'x_io = %d' % self.x_io
521	print 'y_io = %d' % self.y_io
522	print 'irq_per_proc = %d' % self.irq_per_proc
523	print 'use_ramdisk = %d' % self.use_ramdisk
524	print 'total_globals = %d' % self.total_globals
525	print 'total_psegs = %d' % self.total_psegs
526	print 'total_vsegs = %d' % self.total_vsegs
527	print 'total_tasks = %d' % self.total_tasks
528	print 'total_procs = %d' % self.total_procs
529	print 'total_irqs = %d' % self.total_irqs
530	print 'total_periphs = %d' % self.total_periphs
531	print '\n'
532
533	# clusters array
534	index = 0
535	for cluster in self.clusters:
536	byte_stream += cluster.cbin( self, verbose, index )
537	index += 1
538
539	if ( verbose ): print '\n'
540
541	# psegs array
542	index = 0
543	for cluster in self.clusters:
544	for pseg in cluster.psegs:
545	byte_stream += pseg.cbin( self, verbose, index, cluster )
546	index += 1
547
548	if ( verbose ): print '\n'
549
550	# vspaces array
551	index = 0
552	for vspace in self.vspaces:
553	byte_stream += vspace.cbin( self, verbose, index )
554	index += 1
555
556	if ( verbose ): print '\n'
557
558	# vsegs array
559	index = 0
560	for vseg in self.globs:
561	byte_stream += vseg.cbin( self, verbose, index )
562	index += 1
563	for vspace in self.vspaces:
564	for vseg in vspace.vsegs:
565	byte_stream += vseg.cbin( self, verbose, index )
566	index += 1
567
568	if ( verbose ): print '\n'
569
570	# tasks array
571	index = 0
572	for vspace in self.vspaces:
573	for task in vspace.tasks:
574	byte_stream += task.cbin( self, verbose, index, vspace )
575	index += 1
576
577	if ( verbose ): print '\n'
578
579	# procs array
580	index = 0
581	for cluster in self.clusters:
582	for proc in cluster.procs:
583	byte_stream += proc.cbin( self, verbose, index )
584	index += 1
585
586	if ( verbose ): print '\n'
587
588	# irqs array
589	index = 0
590	for cluster in self.clusters:
591	for periph in cluster.periphs:
592	for irq in periph.irqs:
593	byte_stream += irq.cbin( self, verbose, index )
594	index += 1
595
596	if ( verbose ): print '\n'
597
598	# periphs array
599	index = 0
600	for cluster in self.clusters:
601	for periph in cluster.periphs:
602	byte_stream += periph.cbin( self, verbose, index )
603	index += 1
604
605	return byte_stream
606	# end of cbin()
607
608	#######################################################################
609	def giet_vsegs( self ): # compute string for giet_vsegs.ld file
610	# required by giet_vm compilation
611
612	# search the vsegs required for the giet_vsegs.ld
613	boot_code_found = False
614	boot_data_found = False
615	kernel_uncdata_found = False
616	kernel_data_found = False
617	kernel_code_found = False
618	kernel_init_found = False
619	for vseg in self.globs:
620
621	if ( vseg.name[0:13] == 'seg_boot_code' ):
622	boot_code_vbase = vseg.vbase
623	boot_code_size = vseg.length
624	boot_code_found = True
625
626	if ( vseg.name[0:13] == 'seg_boot_data' ):
627	boot_data_vbase = vseg.vbase
628	boot_data_size = vseg.length
629	boot_data_found = True
630
631	if ( vseg.name[0:15] == 'seg_kernel_data' ):
632	kernel_data_vbase = vseg.vbase
633	kernel_data_size = vseg.length
634	kernel_data_found = True
635
636	if ( vseg.name[0:15] == 'seg_kernel_code' ):
637	kernel_code_vbase = vseg.vbase
638	kernel_code_size = vseg.length
639	kernel_code_found = True
640
641	if ( vseg.name[0:15] == 'seg_kernel_init' ):
642	kernel_init_vbase = vseg.vbase
643	kernel_init_size = vseg.length
644	kernel_init_found = True
645
646	# check if all required vsegs have been found
647	if ( boot_code_found == False ):
648	print '[genmap error] in giet_vsegs()'
649	print ' seg_boot_code vseg missing'
650	sys.exit()
651
652	if ( boot_data_found == False ):
653	print '[genmap error] in giet_vsegs()'
654	print ' seg_boot_data vseg missing'
655	sys.exit()
656
657	if ( kernel_data_found == False ):
658	print '[genmap error] in giet_vsegs()'
659	print ' seg_kernel_data vseg missing'
660	sys.exit()
661
662	if ( kernel_code_found == False ):
663	print '[genmap error] in giet_vsegs()'
664	print ' seg_kernel_code vseg missing'
665	sys.exit()
666
667	if ( kernel_init_found == False ):
668	print '[genmap error] in giet_vsegs()'
669	print ' seg_kernel_init vseg missing'
670	sys.exit()
671
672	# build string
673	s = '/* Generated by genmap for %s */\n' % self.name
674	s += '\n'
675
676	s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase
677	s += 'boot_code_size = 0x%x;\n' % boot_code_size
678	s += '\n'
679	s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase
680	s += 'boot_data_size = 0x%x;\n' % boot_data_size
681	s += '\n'
682	s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase
683	s += 'kernel_code_size = 0x%x;\n' % kernel_code_size
684	s += '\n'
685	s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase
686	s += 'kernel_data_size = 0x%x;\n' % kernel_data_size
687	s += '\n'
688	s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase
689	s += 'kernel_init_size = 0x%x;\n' % kernel_init_size
690	s += '\n'
691
692	return s
693
694	######################################################################
695	def hard_config( self ): # compute string for hard_config.h file
696	# required by
697	# - top.cpp compilation
698	# - giet_vm compilation
699	# - tsar_preloader compilation
700
701	nb_total_procs = 0
702
703	# for each peripheral type, define default values
704	# for pbase address, size, number of components, and channels
705	nb_cma = 0
706	cma_channels = 0
707	seg_cma_base = 0xFFFFFFFF
708	seg_cma_size = 0
709
710	nb_dma = 0
711	dma_channels = 0
712	seg_dma_base = 0xFFFFFFFF
713	seg_dma_size = 0
714
715	nb_fbf = 0
716	fbf_channels = 0
717	seg_fbf_base = 0xFFFFFFFF
718	seg_fbf_size = 0
719	fbf_arg0 = 0
720	fbf_arg1 = 0
721
722	nb_iob = 0
723	iob_channels = 0
724	seg_iob_base = 0xFFFFFFFF
725	seg_iob_size = 0
726
727	nb_ioc = 0
728	ioc_channels = 0
729	seg_ioc_base = 0xFFFFFFFF
730	seg_ioc_size = 0
731
732	nb_mmc = 0
733	mmc_channels = 0
734	seg_mmc_base = 0xFFFFFFFF
735	seg_mmc_size = 0
736
737	nb_mwr = 0
738	mwr_channels = 0
739	seg_mwr_base = 0xFFFFFFFF
740	seg_mwr_size = 0
741	mwr_arg0 = 0
742	mwr_arg1 = 0
743	mwr_arg2 = 0
744	mwr_arg3 = 0
745
746	nb_nic = 0
747	nic_channels = 0
748	seg_nic_base = 0xFFFFFFFF
749	seg_nic_size = 0
750
751	nb_pic = 0
752	pic_channels = 0
753	seg_pic_base = 0xFFFFFFFF
754	seg_pic_size = 0
755
756	nb_rom = 0
757	rom_channels = 0
758	seg_rom_base = 0xFFFFFFFF
759	seg_rom_size = 0
760
761	nb_sim = 0
762	sim_channels = 0
763	seg_sim_base = 0xFFFFFFFF
764	seg_sim_size = 0
765
766	nb_tim = 0
767	tim_channels = 0
768	seg_tim_base = 0xFFFFFFFF
769	seg_tim_size = 0
770
771	nb_tty = 0
772	tty_channels = 0
773	seg_tty_base = 0xFFFFFFFF
774	seg_tty_size = 0
775
776	nb_xcu = 0
777	xcu_channels = 0
778	seg_xcu_base = 0xFFFFFFFF
779	seg_xcu_size = 0
780	xcu_arg0 = 0
781
782	nb_drom = 0
783	drom_channels = 0
784	seg_drom_base = 0xFFFFFFFF
785	seg_drom_size = 0
786
787	use_bdv = False
788	use_spi = False
789	use_hba = False
790
791	# get peripherals attributes
792	for cluster in self.clusters:
793	for periph in cluster.periphs:
794	if ( periph.ptype == 'CMA' ):
795	seg_cma_base = periph.pseg.base & 0xFFFFFFFF
796	seg_cma_size = periph.pseg.size
797	cma_channels = periph.channels
798	nb_cma +=1
799
800	elif ( periph.ptype == 'DMA' ):
801	seg_dma_base = periph.pseg.base & 0xFFFFFFFF
802	seg_dma_size = periph.pseg.size
803	dma_channels = periph.channels
804	nb_dma +=1
805
806	elif ( periph.ptype == 'FBF' ):
807	seg_fbf_base = periph.pseg.base & 0xFFFFFFFF
808	seg_fbf_size = periph.pseg.size
809	fbf_channels = periph.channels
810	fbf_arg0 = periph.arg0
811	fbf_arg1 = periph.arg1
812	nb_fbf +=1
813
814	elif ( periph.ptype == 'IOB' ):
815	seg_iob_base = periph.pseg.base & 0xFFFFFFFF
816	seg_iob_size = periph.pseg.size
817	iob_channels = periph.channels
818	nb_iob +=1
819
820	elif ( periph.ptype == 'IOC' ):
821	seg_ioc_base = periph.pseg.base & 0xFFFFFFFF
822	seg_ioc_size = periph.pseg.size
823	ioc_channels = periph.channels
824	nb_ioc += 1
825
826	if self.use_ramdisk: continue
827
828	if ( periph.subtype == 'BDV' ): use_bdv = True
829	elif ( periph.subtype == 'HBA' ): use_hba = True
830	elif ( periph.subtype == 'SPI' ): use_spi = True
831
832	elif ( periph.ptype == 'MMC' ):
833	seg_mmc_base = periph.pseg.base & 0xFFFFFFFF
834	seg_mmc_size = periph.pseg.size
835	mmc_channels = periph.channels
836	nb_mmc +=1
837
838	elif ( periph.ptype == 'MWR' ):
839	seg_mwr_base = periph.pseg.base & 0xFFFFFFFF
840	seg_mwr_size = periph.pseg.size
841	mwr_channels = periph.channels
842	mwr_arg0 = periph.arg0
843	mwr_arg1 = periph.arg1
844	mwr_arg2 = periph.arg2
845	mwr_arg3 = periph.arg3
846	nb_mwr +=1
847
848	elif ( periph.ptype == 'ROM' ):
849	seg_rom_base = periph.pseg.base & 0xFFFFFFFF
850	seg_rom_size = periph.pseg.size
851	rom_channels = periph.channels
852	nb_rom +=1
853
854	elif ( periph.ptype == 'DROM' ):
855	seg_drom_base = periph.pseg.base & 0xFFFFFFFF
856	seg_drom_size = periph.pseg.size
857	drom_channels = periph.channels
858	nb_drom +=1
859
860	elif ( periph.ptype == 'SIM' ):
861	seg_sim_base = periph.pseg.base & 0xFFFFFFFF
862	seg_sim_size = periph.pseg.size
863	sim_channels = periph.channels
864	nb_sim +=1
865
866	elif ( periph.ptype == 'NIC' ):
867	seg_nic_base = periph.pseg.base & 0xFFFFFFFF
868	seg_nic_size = periph.pseg.size
869	nic_channels = periph.channels
870	nb_nic +=1
871
872	elif ( periph.ptype == 'PIC' ):
873	seg_pic_base = periph.pseg.base & 0xFFFFFFFF
874	seg_pic_size = periph.pseg.size
875	pic_channels = periph.channels
876	nb_pic +=1
877
878	elif ( periph.ptype == 'TIM' ):
879	seg_tim_base = periph.pseg.base & 0xFFFFFFFF
880	seg_tim_size = periph.pseg.size
881	tim_channels = periph.channels
882	nb_tim +=1
883
884	elif ( periph.ptype == 'TTY' ):
885	seg_tty_base = periph.pseg.base & 0xFFFFFFFF
886	seg_tty_size = periph.pseg.size
887	tty_channels = periph.channels
888	nb_tty +=1
889
890	elif ( periph.ptype == 'XCU' ):
891	seg_xcu_base = periph.pseg.base & 0xFFFFFFFF
892	seg_xcu_size = periph.pseg.size
893	xcu_channels = periph.channels
894	xcu_arg0 = periph.arg0
895	xcu_arg1 = periph.arg1
896	xcu_arg2 = periph.arg2
897	nb_xcu +=1
898
899	# no more than two access to external peripherals
900	assert ( nb_fbf <= 2 )
901	assert ( nb_cma <= 2 )
902	assert ( nb_ioc <= 2 )
903	assert ( nb_nic <= 2 )
904	assert ( nb_tim <= 2 )
905	assert ( nb_tty <= 2 )
906	assert ( nb_pic <= 2 )
907
908	# one and only one type of IOC controller
909	nb_iocs = 0
910	if use_hba : nb_iocs += 1
911	if use_bdv : nb_iocs += 1
912	if use_spi : nb_iocs += 1
913	if self.use_ramdisk: nb_iocs += 1
914	assert ( nb_iocs == 1 )
915
916	# Compute total number of processors
917	for cluster in self.clusters:
918	nb_total_procs += len( cluster.procs )
919
920	# Compute physical addresses for BOOT vsegs
921	boot_mapping_found = False
922	boot_code_found = False
923	boot_data_found = False
924	boot_stack_found = False
925
926	for vseg in self.globs:
927	if ( vseg.name == 'seg_boot_mapping' ):
928	boot_mapping_base = vseg.vbase
929	boot_mapping_size = vseg.length
930	boot_mapping_identity = vseg.identity
931	boot_mapping_found = True
932
933	if ( vseg.name == 'seg_boot_code' ):
934	boot_code_base = vseg.vbase
935	boot_code_size = vseg.length
936	boot_code_identity = vseg.identity
937	boot_code_found = True
938
939	if ( vseg.name == 'seg_boot_data' ):
940	boot_data_base = vseg.vbase
941	boot_data_size = vseg.length
942	boot_data_identity = vseg.identity
943	boot_data_found = True
944
945	if ( vseg.name == 'seg_boot_stack' ):
946	boot_stack_base = vseg.vbase
947	boot_stack_size = vseg.length
948	boot_stack_identity = vseg.identity
949	boot_stack_found = True
950
951	# check that BOOT vsegs are found and identity mapping
952	if ( (boot_mapping_found == False) or (boot_mapping_identity == False) ):
953	print '[genmap error] in hard_config()'
954	print ' seg_boot_mapping missing or not identity mapping'
955	sys.exit()
956
957	if ( (boot_code_found == False) or (boot_code_identity == False) ):
958	print '[genmap error] in hard_config()'
959	print ' seg_boot_code missing or not identity mapping'
960	sys.exit()
961
962	if ( (boot_data_found == False) or (boot_data_identity == False) ):
963	print '[genmap error] in hard_config()'
964	print ' seg_boot_data missing or not identity mapping'
965	sys.exit()
966
967	if ( (boot_stack_found == False) or (boot_stack_identity == False) ):
968	print '[genmap error] in giet_vsegs()'
969	print ' seg_boot_stask missing or not identity mapping'
970	sys.exit()
971
972	# Search RAMDISK global vseg if required
973	seg_rdk_base = 0xFFFFFFFF
974	seg_rdk_size = 0
975	seg_rdk_found = False
976
977	if self.use_ramdisk:
978	for vseg in self.globs:
979	if ( vseg.name == 'seg_ramdisk' ):
980	seg_rdk_base = vseg.vbase
981	seg_rdk_size = vseg.length
982	seg_rdk_found = True
983
984	if ( seg_rdk_found == False ):
985	print 'Error in hard_config() "seg_ramdisk" not found'
986	sys.exit(1)
987
988	# build string
989	s = '/* Generated by genmap for %s */\n' % self.name
990	s += '\n'
991	s += '#ifndef HARD_CONFIG_H\n'
992	s += '#define HARD_CONFIG_H\n'
993	s += '\n'
994
995	s += '/* General platform parameters */\n'
996	s += '\n'
997	s += '#define X_SIZE %d\n' % self.x_size
998	s += '#define Y_SIZE %d\n' % self.y_size
999	s += '#define X_WIDTH %d\n' % self.x_width
1000	s += '#define Y_WIDTH %d\n' % self.y_width
1001	s += '#define P_WIDTH %d\n' % self.p_width
1002	s += '#define X_IO %d\n' % self.x_io
1003	s += '#define Y_IO %d\n' % self.y_io
1004	s += '#define NB_PROCS_MAX %d\n' % self.nprocs
1005	s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc
1006	s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address
1007	s += '#define NB_TOTAL_PROCS %d\n' % nb_total_procs
1008	s += '\n'
1009
1010	s += '/* Peripherals */\n'
1011	s += '\n'
1012	s += '#define NB_TTY_CHANNELS %d\n' % tty_channels
1013	s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels
1014	s += '#define NB_NIC_CHANNELS %d\n' % nic_channels
1015	s += '#define NB_CMA_CHANNELS %d\n' % cma_channels
1016	s += '#define NB_TIM_CHANNELS %d\n' % tim_channels
1017	s += '#define NB_DMA_CHANNELS %d\n' % dma_channels
1018	s += '\n'
1019	s += '#define USE_XCU %d\n' % ( nb_xcu != 0 )
1020	s += '#define USE_IOB %d\n' % ( nb_iob != 0 )
1021	s += '#define USE_PIC %d\n' % ( nb_pic != 0 )
1022	s += '#define USE_FBF %d\n' % ( nb_fbf != 0 )
1023	s += '\n'
1024	s += '#define USE_IOC_BDV %d\n' % use_bdv
1025	s += '#define USE_IOC_SPI %d\n' % use_spi
1026	s += '#define USE_IOC_HBA %d\n' % use_hba
1027	s += '#define USE_IOC_RDK %d\n' % self.use_ramdisk
1028	s += '\n'
1029	s += '#define FBUF_X_SIZE %d\n' % fbf_arg0
1030	s += '#define FBUF_Y_SIZE %d\n' % fbf_arg1
1031	s += '\n'
1032	s += '#define XCU_NB_HWI %d\n' % xcu_arg0
1033	s += '#define XCU_NB_PTI %d\n' % xcu_arg1
1034	s += '#define XCU_NB_WTI %d\n' % xcu_arg2
1035	s += '#define XCU_NB_OUT %d\n' % xcu_channels
1036	s += '\n'
1037	s += '#define MWR_TO_COPROC %d\n' % mwr_arg0
1038	s += '#define MWR_FROM_COPROC %d\n' % mwr_arg1
1039	s += '#define MWR_CONFIG %d\n' % mwr_arg2
1040	s += '#define MWR_STATUS %d\n' % mwr_arg3
1041	s += '\n'
1042
1043	s += '/* base addresses and sizes for physical segments */\n'
1044	s += '\n'
1045	s += '#define SEG_RAM_BASE 0x%x\n' % self.ram_base
1046	s += '#define SEG_RAM_SIZE 0x%x\n' % self.ram_size
1047	s += '\n'
1048	s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base
1049	s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size
1050	s += '\n'
1051	s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base
1052	s += '#define SEG_DMA_SIZE 0x%x\n' % seg_dma_size
1053	s += '\n'
1054	s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base
1055	s += '#define SEG_FBF_SIZE 0x%x\n' % seg_fbf_size
1056	s += '\n'
1057	s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base
1058	s += '#define SEG_IOB_SIZE 0x%x\n' % seg_iob_size
1059	s += '\n'
1060	s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base
1061	s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size
1062	s += '\n'
1063	s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base
1064	s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size
1065	s += '\n'
1066	s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base
1067	s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size
1068	s += '\n'
1069	s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base
1070	s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size
1071	s += '\n'
1072	s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base
1073	s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size
1074	s += '\n'
1075	s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base
1076	s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size
1077	s += '\n'
1078	s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base
1079	s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size
1080	s += '\n'
1081	s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base
1082	s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size
1083	s += '\n'
1084	s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base
1085	s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size
1086	s += '\n'
1087	s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base
1088	s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size
1089	s += '\n'
1090	s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base
1091	s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size
1092	s += '\n'
1093	s += '#define SEG_DROM_BASE 0x%x\n' % seg_drom_base
1094	s += '#define SEG_DROM_SIZE 0x%x\n' % seg_drom_size
1095	s += '\n'
1096	s += '#define PERI_CLUSTER_INCREMENT 0x%x\n' % self.peri_increment
1097	s += '\n'
1098
1099	s += '/* physical base addresses for identity mapped vsegs */\n'
1100	s += '/* used by the GietVM OS */\n'
1101	s += '\n'
1102	s += '#define SEG_BOOT_MAPPING_BASE 0x%x\n' % boot_mapping_base
1103	s += '#define SEG_BOOT_MAPPING_SIZE 0x%x\n' % boot_mapping_size
1104	s += '\n'
1105	s += '#define SEG_BOOT_CODE_BASE 0x%x\n' % boot_code_base
1106	s += '#define SEG_BOOT_CODE_SIZE 0x%x\n' % boot_code_size
1107	s += '\n'
1108	s += '#define SEG_BOOT_DATA_BASE 0x%x\n' % boot_data_base
1109	s += '#define SEG_BOOT_DATA_SIZE 0x%x\n' % boot_data_size
1110	s += '\n'
1111	s += '#define SEG_BOOT_STACK_BASE 0x%x\n' % boot_stack_base
1112	s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size
1113	s += '#endif\n'
1114
1115	return s
1116
1117	# end of hard_config()
1118
1119	#################################################################
1120	def linux_dts( self ): # compute string for linux.dts file
1121	# used for linux configuration
1122	# header
1123	s = '/dts-v1/;\n'
1124	s += '\n'
1125	s += '/{\n'
1126	s += ' compatible = "tsar,%s";\n' % self.name
1127	s += ' #address-cells = <2>;\n' # physical address on 64 bits
1128	s += ' #size-cells = <1>;\n' # segment size on 32 bits
1129	s += ' model = "%s";\n' % self.name
1130	s += '\n'
1131
1132	# linux globals arguments
1133	s += ' chosen {\n'
1134	s += ' linux,stdout-path = &tty;\n'
1135	s += ' bootargs = "console=tty0 console=ttyVTTY0 earlyprintk";\n'
1136	s += ' };\n\n'
1137
1138	# cpus (for each cluster)
1139	s += ' cpus {\n'
1140	s += ' #address-cells = <1>;\n'
1141	s += ' #size-cells = <0>;\n'
1142
1143	for cluster in self.clusters:
1144	for proc in cluster.procs:
1145	x = cluster.x
1146	y = cluster.y
1147	l = proc.lpid
1148	proc_id = (((x << self.y_width) + y) << self.p_width) + l
1149	s += ' cpu@%d_%d_%d {\n' %(x,y,l)
1150	s += ' device_type = "cpu";\n'
1151	s += ' compatible = "soclib,mips32el";\n'
1152	s += ' reg = <0x%x>;\n' % proc_id
1153	s += ' };\n'
1154	s += '\n'
1155
1156	s += ' };\n\n'
1157
1158	# devices (ram or peripheral) are grouped per cluster
1159	# the "compatible" attribute links a peripheral device
1160	# to one or several drivers identified by ("major","minor")
1161
1162	for cluster in self.clusters:
1163	x = cluster.x
1164	y = cluster.y
1165	found_xcu = False
1166	found_pic = False
1167
1168	s += ' /* cluster[%d,%d] */\n\n' % (x,y)
1169
1170	# scan all psegs to find RAM in current cluster
1171	for pseg in cluster.psegs:
1172	if ( pseg.segtype == 'RAM' ):
1173	msb = pseg.base >> 32
1174	lsb = pseg.base & 0xFFFFFFFF
1175	size = pseg.size
1176
1177	s += ' ram_%d_%d: ram@0x%x {\n' % (x, y, pseg.base)
1178	s += ' device_type = "memory";\n'
1179	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1180	s += ' };\n\n'
1181
1182	# scan all periphs to find XCU or PIC in current cluster
1183	for periph in cluster.periphs:
1184	msb = periph.pseg.base >> 32
1185	lsb = periph.pseg.base & 0xFFFFFFFF
1186	size = periph.pseg.size
1187
1188	# search XCU (can be replicated)
1189	if ( (periph.ptype == 'XCU') ):
1190	found_xcu = True
1191	xcu = periph
1192	irq_ctrl_name = 'xcu_%d_%d' % (x, y)
1193
1194	s += ' %s: xcu@0x%x {\n' % (irq_ctrl_name, periph.pseg.base)
1195	s += ' compatible = "soclib,vci_xicu","soclib,vci_xicu_timer";\n'
1196	s += ' interrupt-controller;\n'
1197	s += ' #interrupt-cells = <1>;\n'
1198	s += ' clocks = <&freq>;\n' # XCU contains a timer
1199	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1200	s += ' };\n\n'
1201
1202	# search PIC (non replicated)
1203	if ( periph.ptype == 'PIC' ):
1204	found_pic = True
1205	pic = periph
1206	irq_ctrl_name = 'pic'
1207
1208	s += ' %s: pic@0x%x {\n' % (irq_ctrl_name, periph.pseg.base)
1209	s += ' compatible = "soclib,vci_iopic";\n'
1210	s += ' interrupt-controller;\n'
1211	s += ' #interrupt-cells = <1>;\n'
1212	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1213	s += ' };\n\n'
1214
1215	# we need one interrupt controler in any cluster containing peripherals
1216	if ( (found_xcu == False) and
1217	(found_pic == False) and
1218	(len(cluster.periphs) > 0) ):
1219	print '[genmap error] in linux_dts()'
1220	print ' No XCU/PIC in cluster(%d,%d)' % (x,y)
1221	sys.exit(1)
1222
1223	if ( found_pic == True ): irq_ctrl = pic
1224	else: irq_ctrl = xcu
1225
1226	# scan all periphs to find TTY and IOC in current cluster
1227	for periph in cluster.periphs:
1228	msb = periph.pseg.base >> 32
1229	lsb = periph.pseg.base & 0xFFFFFFFF
1230	size = periph.pseg.size
1231
1232	# search TTY (non replicated)
1233	if ( periph.ptype == 'TTY' ):
1234
1235	# get HWI index to XCU or PIC (only TTY0 is used by Linux)
1236	hwi_id = 0xFFFFFFFF
1237	for irq in irq_ctrl.irqs:
1238	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == 0) ):
1239	hwi_id = irq.srcid
1240
1241	if ( hwi_id == 0xFFFFFFFF ):
1242	print '[genmap error] in linux.dts()'
1243	print ' IRQ_TTY_RX not found'
1244	sys.exit(1)
1245
1246	s += ' tty: tty@0x%x {\n' % (periph.pseg.base)
1247	s += ' compatible = "soclib,vci_multi_tty";\n'
1248	s += ' interrupt-parent = <&%s>;\n' % (irq_ctrl_name)
1249	s += ' interrupts = <%d>;\n' % hwi_id
1250	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1251	s += ' };\n\n'
1252
1253	# search IOC (non replicated)
1254	elif ( periph.ptype == 'IOC' ):
1255
1256	if ( periph.subtype == 'BDV' ):
1257
1258	# get irq line index associated to bdv
1259	hwi_id = 0xFFFFFFFF
1260	for irq in irq_ctrl.irqs:
1261	if ( irq.isrtype == 'ISR_BDV' ): hwi_id = irq.srcid
1262
1263	if ( hwi_id == 0xFFFFFFFF ):
1264	print '[genmap error] in linux.dts()'
1265	print ' ISR_BDV not found'
1266	sys.exit(1)
1267
1268	s += ' bdv: bdv@0x%x {\n' % (periph.pseg.base)
1269	s += ' compatible = "tsar,vci_block_device";\n'
1270	s += ' interrupt-parent = <&%s>;\n' % (irq_ctrl_name)
1271	s += ' interrupts = <%d>;\n' % hwi_id
1272	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1273	s += ' };\n\n'
1274
1275	else:
1276	print '[genmap warning] in linux_dts() : '
1277	print ' %s' % (periph.subtype),
1278	print 'peripheral not supported by LINUX'
1279
1280	# XCU or PIC have been already parsed
1281	elif ( periph.ptype == 'XCU' ) or ( periph.ptype == 'PIC' ):
1282	pass
1283
1284	# other peripherals
1285	else:
1286	print '[genmap warning] in linux_dts() : '
1287	print ' %s peripheral not supported by LINUX' % (periph.ptype)
1288
1289	# clocks
1290	s += ' /* clocks */\n\n'
1291	s += ' clocks {\n'
1292	s += ' freq: freq@50MHZ {\n'
1293	s += ' #clock-cells = <0>;\n'
1294	s += ' compatible = "fixed-clock";\n'
1295	s += ' clock-frequency = <50000000>;\n'
1296	s += ' };\n'
1297	s += ' };\n\n'
1298	s += ' cpuclk {\n'
1299	s += ' compatible = "soclib,mips32_clksrc";\n'
1300	s += ' clocks = <&freq>;\n'
1301	s += ' };\n'
1302	s += '};\n'
1303
1304	return s
1305	# end linux_dts()
1306
1307
1308	#################################################################
1309	def netbsd_dts( self ): # compute string for netbsd.dts file
1310	# used for netbsd configuration
1311	# header
1312	s = '/dts-v1/;\n'
1313	s += '\n'
1314	s += '/{\n'
1315	s += ' #address-cells = <2>;\n'
1316	s += ' #size-cells = <1>;\n'
1317
1318	# cpus (for each cluster)
1319	s += ' cpus {\n'
1320	s += ' #address-cells = <1>;\n'
1321	s += ' #size-cells = <0>;\n'
1322
1323	for cluster in self.clusters:
1324	for proc in cluster.procs:
1325	proc_id = (((cluster.x << self.y_width) + cluster.y)
1326	<< self.p_width) + proc.lpid
1327
1328	s += ' Mips,32@0x%x {\n' % proc_id
1329	s += ' device_type = "cpu";\n'
1330	s += ' icudev_type = "cpu:mips";\n'
1331	s += ' name = "Mips,32";\n'
1332	s += ' reg = <0x%x>;\n' % proc_id
1333	s += ' };\n'
1334	s += '\n'
1335
1336	s += ' };\n'
1337
1338	# physical memory banks (for each cluster)
1339	for cluster in self.clusters:
1340	for pseg in cluster.psegs:
1341
1342	if ( pseg.segtype == 'RAM' ):
1343	msb = pseg.base >> 32
1344	lsb = pseg.base & 0xFFFFFFFF
1345	size = pseg.size
1346
1347	s += ' %s@0x%x {\n' % (pseg.name, pseg.base)
1348	s += ' cached = <1>;\n'
1349	s += ' device_type = "memory";\n'
1350	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb,lsb,size)
1351	s += ' };\n'
1352
1353	# peripherals (for each cluster)
1354	for cluster in self.clusters:
1355	x = cluster.x
1356	y = cluster.y
1357
1358	# research XCU component
1359	found_xcu = False
1360	for periph in cluster.periphs:
1361	if ( (periph.ptype == 'XCU') ):
1362	found_xcu = True
1363	xcu = periph
1364	msb = periph.pseg.base >> 32
1365	lsb = periph.pseg.base & 0xFFFFFFFF
1366	size = periph.pseg.size
1367
1368	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1369	s += ' device_type = "soclib:xicu:root";\n'
1370	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb,lsb,size)
1371	s += ' input_lines = <%d>;\n' % periph.arg
1372	s += ' ipis = <%d>;\n' % periph.arg
1373	s += ' timers = <%d>;\n' % periph.arg
1374
1375	output_id = 0 # output index from XCU
1376	for lpid in xrange ( len(cluster.procs) ): # destination processor index
1377	for itid in xrange ( self.irq_per_proc ): # input irq index on processor
1378	cluster_xy = (cluster.x << self.y_width) + cluster.y
1379	proc_id = (cluster_xy << self.p_width) + lpid
1380	s += ' out@%d {\n' % output_id
1381	s += ' device_type = "soclib:xicu:filter";\n'
1382	s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid)
1383	s += ' output_line = <%d>;\n' % output_id
1384	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1385	s += ' };\n'
1386
1387	output_id += 1
1388
1389	s += ' };\n'
1390
1391	# research PIC component
1392	found_pic = False
1393	for periph in cluster.periphs:
1394	if ( periph.ptype == 'PIC' ):
1395	found_pic = True
1396	pic = periph
1397	msb = periph.pseg.base >> 32
1398	lsb = periph.pseg.base & 0xFFFFFFFF
1399	size = periph.pseg.size
1400
1401	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1402	s += ' device_type = "soclib:pic:root";\n'
1403	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1404	s += ' input_lines = <%d>;\n' % periph.channels
1405	s += ' };\n'
1406
1407	# at least one interrupt controller
1408	if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ):
1409	print '[genmap error] in netbsd_dts()'
1410	print ' No XCU/PIC in cluster(%d,%d)' % (x,y)
1411	sys.exit(1)
1412
1413	if ( found_pic == True ): irq_tgt = pic
1414	else: irq_tgt = xcu
1415
1416	# get all others peripherals in cluster
1417	for periph in cluster.periphs:
1418	msb = periph.pseg.base >> 32
1419	lsb = periph.pseg.base & 0xFFFFFFFF
1420	size = periph.pseg.size
1421
1422	# research DMA component
1423	if ( periph.ptype == 'DMA' ):
1424
1425	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1426	s += ' device_type = "soclib:dma";\n'
1427	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1428	s += ' channel_count = <%d>;\n' % periph.channels
1429
1430	# multi-channels : get HWI index (to XCU) for each channel
1431	for channel in xrange( periph.channels ):
1432	hwi_id = 0xFFFFFFFF
1433	for irq in xcu.irqs:
1434	if ( (irq.isrtype == 'ISR_DMA') and
1435	(irq.channel == channel) ):
1436	hwi_id = irq.srcid
1437
1438	if ( hwi_id == 0xFFFFFFFF ):
1439	print '[genmap error] in netbsd.dts()'
1440	print ' ISR_DMA channel %d not found' % channel
1441	sys.exit(1)
1442
1443	name = '%s@0x%x' % (xcu.pseg.name, xcu.pseg.base)
1444	s += ' irq@%d{\n' % channel
1445	s += ' device_type = "soclib:periph:irq";\n'
1446	s += ' output_line = <%d>;\n' % channel
1447	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1448	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1449	s += ' };\n'
1450
1451	s += ' };\n'
1452
1453	# research MMC component
1454	elif ( periph.ptype == 'MMC' ):
1455
1456	# get irq line index associated to MMC in XCU
1457	irq_in = 0xFFFFFFFF
1458	for irq in xcu.irqs:
1459	if ( irq.isrtype == 'ISR_MMC' ): irq_in = irq.srcid
1460
1461	if ( irq_in == 0xFFFFFFFF ):
1462	print '[genmap error] in netbsd.dts()'
1463	print ' ISR_MMC not found'
1464	sys.exit(1)
1465
1466	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1467	s += ' device_type = "soclib:mmc";\n'
1468	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
1469	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1470	s += ' };\n'
1471
1472	# research FBF component
1473	elif ( periph.ptype == 'FBF' ):
1474
1475	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1476	s += ' device_type = "soclib:framebuffer";\n'
1477	s += ' mode = <32>;\n' # bits par pixel
1478	s += ' width = <%d>;\n' % periph.arg
1479	s += ' height = <%d>;\n' % periph.arg
1480	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1481	s += ' };\n'
1482
1483	# research IOC component
1484	elif ( periph.ptype == 'IOC' ):
1485
1486	if ( periph.subtype == 'BDV' ):
1487
1488	# get irq line index associated to bdv
1489	irq_in = 0xFFFFFFFF
1490	for irq in irq_tgt.irqs:
1491	if ( irq.isrtype == 'ISR_BDV' ): irq_in = irq.srcid
1492	if ( irq_in == 0xFFFFFFFF ):
1493	print '[genmap error] in netbsd.dts()'
1494	print ' ISR_BDV not found'
1495	sys.exit(1)
1496
1497	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1498	s += ' device_type = "soclib:blockdevice";\n'
1499	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name,irq_tgt.pseg.base,irq_in)
1500	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1501	s += ' };\n'
1502
1503	elif ( periph.subtype == 'HBA' ):
1504	print '[genmap error] in netbsd_dts()'
1505	print ' HBA peripheral not supported by NetBSD'
1506	sys.exit(1)
1507
1508	elif ( periph.subtype == 'SPI' ):
1509
1510	# get irq line index associated to spi
1511	irq_in = 0xFFFFFFFF
1512	for irq in irq_tgt.irqs:
1513	if ( irq.isrtype == 'ISR_SPI' ): irq_in = irq.srcid
1514	if ( irq_in == 0xFFFFFFFF ):
1515	print '[genmap error] in netbsd.dts()'
1516	print ' ISR_SPI not found'
1517	sys.exit(1)
1518
1519	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1520	s += ' device_type = "soclib:spi";\n'
1521	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name,irq_tgt.pseg.base,irq_in)
1522	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1523	s += ' };\n'
1524
1525	# research ROM component
1526	elif ( periph.ptype == 'ROM' ):
1527
1528	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1529	s += ' device_type = "rom";\n'
1530	s += ' cached = <1>;\n'
1531	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1532	s += ' };\n'
1533
1534	# research SIM component
1535	elif ( periph.ptype == 'SIM' ):
1536
1537	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1538	s += ' device_type = "soclib:simhelper";\n'
1539	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1540	s += ' };\n'
1541
1542	# research TTY component
1543	elif ( periph.ptype == 'TTY' ):
1544
1545	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1546	s += ' device_type = "soclib:tty";\n'
1547	s += ' channel_count = < %d >;\n' % periph.channels
1548	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1549
1550	# multi-channels : get HWI index (to XCU or PIC) for each channel
1551	for channel in xrange( periph.channels ):
1552	hwi_id = 0xFFFFFFFF
1553	for irq in irq_tgt.irqs:
1554	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ):
1555	hwi_id = irq.srcid
1556	if ( hwi_id == 0xFFFFFFFF ):
1557	print '[genmap error] in netbsd.dts()'
1558	print ' ISR_TTY_RX channel %d not found' % channel
1559	sys.exit(1)
1560
1561	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1562	s += ' irq@%d{\n' % channel
1563	s += ' device_type = "soclib:periph:irq";\n'
1564	s += ' output_line = <%d>;\n' % channel
1565	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1566	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1567	s += ' };\n'
1568
1569	s += ' };\n'
1570
1571	# research IOB component
1572	elif ( periph.ptype == 'IOB' ):
1573
1574	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1575	s += ' device_type = "soclib:iob";\n'
1576	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1577	s += ' };\n'
1578
1579	# research NIC component
1580	elif ( periph.ptype == 'NIC' ):
1581
1582	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1583	s += ' device_type = "soclib:nic";\n'
1584	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1585	s += ' channel_count = < %d >;\n' % periph.channels
1586
1587	# multi-channels : get HWI index (to XCU or PIC) for RX & TX IRQs
1588	# RX IRQ : (2channel) / TX IRQs : (2channel + 1)
1589	for channel in xrange( periph.channels ):
1590	hwi_id = 0xFFFFFFFF
1591	for irq in irq_tgt.irqs:
1592	if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ):
1593	hwi_id = irq.srcid
1594	if ( hwi_id == 0xFFFFFFFF ):
1595	print '[genmap error] in netbsd.dts()'
1596	print ' ISR_NIC_RX channel %d not found' % channel
1597	sys.exit(1)
1598
1599	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1600	s += ' irq_rx@%d{\n' % channel
1601	s += ' device_type = "soclib:periph:irq";\n'
1602	s += ' output_line = <%d>;\n' % (2*channel)
1603	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1604	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1605	s += ' };\n'
1606
1607	hwi_id = 0xFFFFFFFF
1608	for irq in irq_tgt.irqs:
1609	if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ):
1610	hwi_id = irq.srcid
1611	if ( hwi_id == 0xFFFFFFFF ):
1612	print '[genmap error] in netbsd.dts()'
1613	print ' ISR_NIC_TX channel %d not found' % channel
1614	sys.exit(1)
1615
1616	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1617	s += ' irq_tx@%d{\n' % channel
1618	s += ' device_type = "soclib:periph:irq";\n'
1619	s += ' output_line = <%d>;\n' % (2*channel + 1)
1620	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1621	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1622	s += ' };\n'
1623
1624	s += ' };\n'
1625
1626	# research CMA component
1627	elif ( periph.ptype == 'CMA' ):
1628
1629	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1630	s += ' device_type = "soclib:cma";\n'
1631	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1632	s += ' channel_count = < %d >;\n' % periph.channels
1633
1634	# multi-channels : get HWI index (to XCU or PIC) for each channel
1635	for channel in xrange( periph.channels ):
1636	hwi_id = 0xFFFFFFFF
1637	for irq in irq_tgt.irqs:
1638	if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ):
1639	hwi_id = irq.srcid
1640
1641	if ( hwi_id == 0xFFFFFFFF ):
1642	print '[genmap error] in netbsd.dts()'
1643	print ' ISR_CMA channel %d not found' % channel
1644	sys.exit(1)
1645
1646	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1647	s += ' irq@%d{\n' % channel
1648	s += ' device_type = "soclib:periph:irq";\n'
1649	s += ' output_line = <%d>;\n' % channel
1650	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1651	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1652	s += ' };\n'
1653
1654	s += ' };\n'
1655
1656	# research TIM component
1657	elif ( periph.ptype == 'TIM' ):
1658
1659	print '[genmap error] in netbsd_dts()'
1660	print ' TIM peripheral not supported by NetBSD'
1661	sys.exit(1)
1662
1663	# research MWR component
1664	elif ( periph.ptype == 'MWR' ):
1665
1666	print '[genmap error] in netbsd_dts()'
1667	print ' MWR peripheral not supported by NetBSD'
1668	sys.exit(1)
1669
1670	# topology
1671	s += '\n'
1672	s += ' topology {\n'
1673	s += ' #address-cells = <2>;\n'
1674	s += ' #size-cells = <0>;\n'
1675	for cluster in self.clusters:
1676	s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y)
1677	s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y)
1678	s += ' devices = <\n'
1679
1680	offset = ((cluster.x << self.y_width) + cluster.y) << self.p_width
1681	for proc in cluster.procs:
1682	s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid)
1683	for periph in cluster.periphs:
1684	s += ' &{/%s@0x%x}\n' % (periph.pseg.name, periph.pseg.base)
1685	for pseg in cluster.psegs:
1686	if ( pseg.segtype == 'RAM' ):
1687	s += ' &{/%s@0x%x}\n' % (pseg.name, pseg.base)
1688
1689	s += ' >;\n'
1690	s += ' };\n'
1691	s += ' };\n'
1692	s += '};\n'
1693
1694	return s
1695	# end netbsd_dts()
1696
1697	######################################################################
1698	def almos_archinfo( self ): # compute string for arch.info file
1699	# used for almos configuration
1700	# header
1701	s = '# arch.info file generated by genmap for %s\n' % self.name
1702	s += '\n'
1703	s += '[HEADER]\n'
1704	s += ' REVISION=1\n'
1705	s += ' ARCH=%s\n' % self.name
1706	s += ' XMAX=%d\n' % self.x_size
1707	s += ' YMAX=%d\n' % self.y_size
1708	s += ' CPU_NR=%d\n' % self.nprocs
1709	s += '\n'
1710
1711	# clusters
1712	cluster_id = 0
1713	for cluster in self.clusters:
1714
1715	ram = None
1716	nb_cpus = len( cluster.procs )
1717	nb_devs = len( cluster.periphs )
1718
1719	# search a RAM
1720	for pseg in cluster.psegs:
1721	if ( pseg.segtype == 'RAM' ):
1722	ram = pseg
1723	nb_devs += 1
1724
1725	# search XCU to get IRQs indexes if cluster contains peripherals
1726	if ( len( cluster.periphs ) != 0 ):
1727	tty_irq_id = None
1728	bdv_irq_id = None
1729	dma_irq_id = None
1730
1731	for periph in cluster.periphs:
1732	if ( periph.ptype == 'XCU' ):
1733	# scan irqs
1734	for irq in periph.irqs:
1735	if (irq.isrtype=='ISR_TTY_RX'): tty_irq_id = irq.srcid
1736	if (irq.isrtype=='ISR_BDV' ): bdv_irq_id = irq.srcid
1737	if (irq.isrtype=='ISR_DMA' ): dma_irq_id = irq.srcid
1738
1739	# Build the cluster description
1740	s += '[CLUSTER]\n'
1741	s += ' CID=%d\n' % cluster_id
1742	s += ' ARCH_CID=0x%x\n' % ((cluster.x<<self.y_width)+cluster.y)
1743	s += ' CPU_NR=%d\n' % nb_cpus
1744	s += ' DEV_NR=%d\n' % nb_devs
1745
1746
1747	# Handling RAM when cluster contain a RAM
1748	if (ram != None ):
1749	base = ram.base
1750	size = ram.size
1751	irqid = -1
1752	s += ' DEVID=RAM'
1753	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % (base,size)
1754
1755	# Handling peripherals
1756	for periph in cluster.periphs:
1757	base = periph.pseg.base
1758	size = periph.pseg.size
1759
1760	if ( periph.ptype == 'XCU' ):
1761
1762	s += ' DEVID=XICU'
1763	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' %(base,size)
1764
1765	elif ( (periph.ptype == 'TTY')
1766	and (tty_irq_id != None) ):
1767
1768	s += ' DEVID=TTY'
1769	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' %(base,size,tty_irq_id)
1770
1771	elif ( (periph.ptype == 'DMA')
1772	and (dma_irq_id != None) ):
1773
1774	s += ' DEVID=DMA'
1775	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' %(base,size,dma_irq_id)
1776
1777	elif ( periph.ptype == 'FBF' ):
1778
1779	s += ' DEVID=FB'
1780	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' %(base,size )
1781
1782	elif ( (periph.ptype == 'IOC') and (periph.subtype == 'BDV')
1783	and (bdv_irq_id != None) ):
1784
1785	s += ' DEVID=BLKDEV'
1786	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' %(base,size,bdv_irq_id)
1787
1788	elif ( periph.ptype == 'PIC' ):
1789
1790	s += ' DEVID=IOPIC'
1791	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' %(base,size)
1792
1793	else:
1794	print '# Warning from almos_archinfo() in cluster[%d,%d]' \
1795	% (cluster.x, cluster.y)
1796	print '# peripheral type %s/%s not supported yet\n' \
1797	% ( periph.ptype, periph.subtype )
1798
1799	cluster_id += 1
1800
1801	return s
1802
1803	# end of almos_archinfo()
1804
1805
1806
1807
1808
1809
1810
1811
1812	###################################################################################
1813	class Cluster ( object ):
1814	###################################################################################
1815	def __init__( self,
1816	x,
1817	y ):
1818
1819	self.index = 0 # global index (set by Mapping constructor)
1820	self.x = x # x coordinate
1821	self.y = y # y coordinate
1822	self.psegs = [] # filled by addRam() or addPeriph()
1823	self.procs = [] # filled by addProc()
1824	self.periphs = [] # filled by addPeriph()
1825
1826	return
1827
1828	################
1829	def xml( self ): # xml for a cluster
1830
1831	s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y)
1832	for pseg in self.psegs: s += pseg.xml()
1833	for proc in self.procs: s += proc.xml()
1834	for peri in self.periphs: s += peri.xml()
1835	s += ' </cluster>\n'
1836
1837	return s
1838
1839	#############################################
1840	def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster
1841
1842	if ( verbose ):
1843	print '*** cbin for cluster [%d,%d]' % (self.x, self.y)
1844
1845	# check index
1846	if (self.index != expected):
1847	print '[genmap error] in Cluster.cbin()'
1848	print ' cluster global index = %d / expected = %d' \
1849	% (self.index,expected)
1850	sys.exit(1)
1851
1852	# compute global index for first pseg
1853	if ( len(self.psegs) > 0 ):
1854	pseg_id = self.psegs[0].index
1855	else:
1856	pseg_id = 0
1857
1858	# compute global index for first proc
1859	if ( len(self.procs) > 0 ):
1860	proc_id = self.procs[0].index
1861	else:
1862	proc_id = 0
1863
1864	# compute global index for first periph
1865	if ( len(self.periphs) > 0 ):
1866	periph_id = self.periphs[0].index
1867	else:
1868	periph_id = 0
1869
1870	byte_stream = bytearray()
1871	byte_stream += mapping.int2bytes(4,self.x) # x coordinate
1872	byte_stream += mapping.int2bytes(4,self.y) # x coordinate
1873	byte_stream += mapping.int2bytes(4,len(self.psegs)) # psegs in cluster
1874	byte_stream += mapping.int2bytes(4,pseg_id ) # global index
1875	byte_stream += mapping.int2bytes(4,len(self.procs)) # procs in cluster
1876	byte_stream += mapping.int2bytes(4,proc_id ) # global index
1877	byte_stream += mapping.int2bytes(4,len(self.periphs)) # periphs in cluster
1878	byte_stream += mapping.int2bytes(4, periph_id ) # global index
1879
1880	if ( verbose ):
1881	print 'nb_psegs = %d' % len( self.psegs )
1882	print 'pseg_id = %d' % pseg_id
1883	print 'nb_procs = %d' % len( self.procs )
1884	print 'proc_id = %d' % proc_id
1885	print 'nb_periphs = %d' % len( self.periphs )
1886	print 'periph_id = %d' % periph_id
1887
1888	return byte_stream
1889
1890	##################################################################################
1891	class Vspace( object ):
1892	##################################################################################
1893	def __init__( self,
1894	name,
1895	startname ):
1896
1897	self.index = 0 # global index ( set by addVspace() )
1898	self.name = name # vspace name
1899	self.startname = startname # name of vseg containing the start_vector
1900	self.vsegs = []
1901	self.tasks = []
1902
1903	return
1904
1905	################
1906	def xml( self ): # xml for one vspace
1907
1908	s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname )
1909	for vseg in self.vsegs: s += vseg.xml()
1910	for task in self.tasks: s += task.xml()
1911	s += ' </vspace>\n'
1912
1913	return s
1914
1915	#############################################
1916	def cbin( self, mapping, verbose, expected ): # C binary for Vspace
1917
1918	if ( verbose ):
1919	print '*** cbin for vspace %s' % (self.name)
1920
1921	# check index
1922	if (self.index != expected):
1923	print '[genmap error] in Vspace.cbin()'
1924	print ' vspace global index = %d / expected = %d' \
1925	%(self.index,expected)
1926	sys.exit(1)
1927
1928	# compute global index for vseg containing start_vector
1929	vseg_start_id = 0xFFFFFFFF
1930	for vseg in self.vsegs:
1931	if ( vseg.name == self.startname ): vseg_start_id = vseg.index
1932
1933	if ( vseg_start_id == 0xFFFFFFFF ):
1934	print '[genmap error] in Vspace.cbin()'
1935	print ' startname %s not found for vspace %s' \
1936	%(self.startname,self.name)
1937	sys.exit(1)
1938
1939	# compute first vseg and first task global index
1940	first_vseg_id = self.vsegs[0].index
1941	first_task_id = self.tasks[0].index
1942
1943	# compute number of tasks and number of vsegs
1944	nb_vsegs = len( self.vsegs )
1945	nb_tasks = len( self.tasks )
1946
1947	byte_stream = bytearray()
1948	byte_stream += mapping.str2bytes(32,self.name) # vspace name
1949	byte_stream += mapping.int2bytes(4, vseg_start_id) # vseg start_vector
1950	byte_stream += mapping.int2bytes(4, nb_vsegs) # number of vsegs
1951	byte_stream += mapping.int2bytes(4, nb_tasks) # number of tasks
1952	byte_stream += mapping.int2bytes(4, first_vseg_id) # global index
1953	byte_stream += mapping.int2bytes(4, first_task_id) # global index
1954
1955	if ( verbose ):
1956	print 'start_id = %d' % vseg_start_id
1957	print 'nb_vsegs = %d' % nb_vsegs
1958	print 'nb_tasks = %d' % nb_tasks
1959	print 'vseg_id = %d' % first_vseg_id
1960	print 'task_id = %d' % first_task_id
1961
1962	return byte_stream
1963
1964	##################################################################################
1965	class Task( object ):
1966	##################################################################################
1967	def __init__( self,
1968	name,
1969	trdid,
1970	x,
1971	y,
1972	p,
1973	stackname,
1974	heapname,
1975	startid ):
1976
1977	self.index = 0 # global index value set by addTask()
1978	self.name = name # tsk name
1979	self.trdid = trdid # task index (unique in vspace)
1980	self.x = x # cluster x coordinate
1981	self.y = y # cluster y coordinate
1982	self.p = p # processor local index
1983	self.stackname = stackname # name of vseg containing the stack
1984	self.heapname = heapname # name of vseg containing the heap
1985	self.startid = startid # index in start_vector
1986	return
1987
1988	######################################
1989	def xml( self ): # xml for one task
1990
1991	s = ' <task name="%s"' % self.name
1992	s += ' trdid="%d"' % self.trdid
1993	s += ' x="%d"' % self.x
1994	s += ' y="%d"' % self.y
1995	s += ' p="%d"' % self.p
1996	s += '\n '
1997	s += ' stackname="%s"' % self.stackname
1998	s += ' heapname="%s"' % self.heapname
1999	s += ' startid="%d"' % self.startid
2000	s += ' />\n'
2001
2002	return s
2003
2004	##########################################################################
2005	def cbin( self, mapping, verbose, expected, vspace ): # C binary for Task
2006
2007	if ( verbose ):
2008	print '*** cbin for task %s in vspace %s' \
2009	% (self.name, vspace.name)
2010
2011	# check index
2012	if (self.index != expected):
2013	print '[genmap error] in Task.cbin()'
2014	print ' task global index = %d / expected = %d' \
2015	%(self.index,expected)
2016	sys.exit(1)
2017
2018	# compute cluster global index
2019	cluster_id = (self.x * mapping.y_size) + self.y
2020
2021	# compute vseg index for stack
2022	vseg_stack_id = 0xFFFFFFFF
2023	for vseg in vspace.vsegs:
2024	if ( vseg.name == self.stackname ): vseg_stack_id = vseg.index
2025
2026	if ( vseg_stack_id == 0xFFFFFFFF ):
2027	print '[genmap error] in Task.cbin()'
2028	print ' stackname %s not found for task %s in vspace %s' \
2029	% ( self.stackname, self.name, vspace.name )
2030	sys.exit(1)
2031
2032	# compute vseg index for heap
2033	if ( self.heapname == '' ):
2034	vseg_heap_id = 0
2035	else:
2036	vseg_heap_id = 0xFFFFFFFF
2037	for vseg in vspace.vsegs:
2038	if ( vseg.name == self.heapname ): vseg_heap_id = vseg.index
2039
2040	if ( vseg_heap_id == 0xFFFFFFFF ):
2041	print '[genmap error] in Task.cbin()'
2042	print ' heapname %s not found for task %s in vspace %s' \
2043	% ( self.heapname, self.name, vspace.name )
2044	sys.exit(1)
2045
2046	byte_stream = bytearray()
2047	byte_stream += mapping.str2bytes(32,self.name) # task name in vspace
2048	byte_stream += mapping.int2bytes(4, cluster_id) # cluster global index
2049	byte_stream += mapping.int2bytes(4, self.p) # processor local index
2050	byte_stream += mapping.int2bytes(4, self.trdid) # thread index in vspace
2051	byte_stream += mapping.int2bytes(4, vseg_stack_id) # stack vseg local index
2052	byte_stream += mapping.int2bytes(4, vseg_heap_id) # heap vseg local index
2053	byte_stream += mapping.int2bytes(4, self.startid) # index in start vector
2054
2055	if ( verbose ):
2056	print 'clusterid = %d' % cluster_id
2057	print 'lpid = %d' % self.p
2058	print 'trdid = %d' % self.trdid
2059	print 'stackid = %d' % vseg_stack_id
2060	print 'heapid = %d' % vseg_heap_id
2061	print 'startid = %d' % self.startid
2062
2063	return byte_stream
2064
2065	##################################################################################
2066	class Vseg( object ):
2067	##################################################################################
2068	def __init__( self,
2069	name,
2070	vbase,
2071	length,
2072	mode,
2073	vtype,
2074	x,
2075	y,
2076	pseg,
2077	identity = False,
2078	local = False,
2079	big = False,
2080	binpath = '' ):
2081
2082	assert (vbase & 0xFFFFFFFF) == vbase
2083
2084	assert (length & 0xFFFFFFFF) == length
2085
2086	assert mode in VSEGMODES
2087
2088	assert vtype in VSEGTYPES
2089
2090	assert (vtype != 'ELF') or (binpath != '')
2091
2092	self.index = 0 # global index ( set by addVseg() )
2093	self.name = name # vseg name (unique in vspace)
2094	self.vbase = vbase # virtual base address in vspace
2095	self.length = length # vseg length (bytes)
2096	self.vtype = vtype # vseg type (defined in VSEGTYPES)
2097	self.mode = mode # CXWU access rights
2098	self.x = x # x coordinate of destination cluster
2099	self.y = y # y coordinate of destination cluster
2100	self.psegname = pseg # name of pseg in destination cluster
2101	self.identity = identity # identity mapping required
2102	self.local = local # only mapped in local PTAB when true
2103	self.big = big # to be mapped in a big physical page
2104	self.binpath = binpath # pathname for binary file (ELF or BLOB)
2105
2106	return
2107
2108	##################################
2109	def xml( self ): # xml for a vseg
2110
2111	s = ' <vseg name="%s"' %(self.name)
2112	s += ' vbase="0x%x"' %(self.vbase)
2113	s += ' length="0x%x"' %(self.length)
2114	s += ' type="%s"' %(self.vtype)
2115	s += ' mode="%s"' %(self.mode)
2116	s += '\n '
2117	s += ' x="%d"' %(self.x)
2118	s += ' y="%d"' %(self.y)
2119	s += ' psegname="%s"' %(self.psegname)
2120	if ( self.identity ): s += ' ident="1"'
2121	if ( self.local ): s += ' local="1"'
2122	if ( self.big ): s += ' big="1"'
2123	if ( self.binpath != '' ): s += ' binpath="%s"' %(self.binpath)
2124	s += ' />\n'
2125
2126	return s
2127
2128	#####################################################################
2129	def cbin( self, mapping, verbose, expected ): # C binary for Vseg
2130
2131	if ( verbose ):
2132	print '*** cbin for vseg[%d] %s' % (self.index, self.name)
2133
2134	# check index
2135	if (self.index != expected):
2136	print '[genmap error] in Vseg.cbin()'
2137	print ' vseg global index = %d / expected = %d' \
2138	% (self.index, expected )
2139	sys.exit(1)
2140
2141	# compute pseg_id
2142	pseg_id = 0xFFFFFFFF
2143	cluster_id = (self.x * mapping.y_size) + self.y
2144	cluster = mapping.clusters[cluster_id]
2145	for pseg in cluster.psegs:
2146	if (self.psegname == pseg.name):
2147	pseg_id = pseg.index
2148	if (pseg_id == 0xFFFFFFFF):
2149	print '[genmap error] in Vseg.cbin() : '
2150	print ' psegname %s not found for vseg %s in cluster %d' \
2151	% ( self.psegname, self.name, cluster_id )
2152	sys.exit(1)
2153
2154	# compute numerical value for mode
2155	mode_id = 0xFFFFFFFF
2156	for x in xrange( len(VSEGMODES) ):
2157	if ( self.mode == VSEGMODES[x] ):
2158	mode_id = x
2159	if ( mode_id == 0xFFFFFFFF ):
2160	print '[genmap error] in Vseg.cbin() : '
2161	print ' undefined vseg mode %s' % self.mode
2162	sys.exit(1)
2163
2164	# compute numerical value for vtype
2165	vtype_id = 0xFFFFFFFF
2166	for x in xrange( len(VSEGTYPES) ):
2167	if ( self.vtype == VSEGTYPES[x] ):
2168	vtype_id = x
2169	if ( vtype_id == 0xFFFFFFFF ):
2170	print '[genmap error] in Vseg.cbin()'
2171	print ' undefined vseg type %s' % self.vtype
2172	sys.exit(1)
2173
2174	byte_stream = bytearray()
2175	byte_stream += mapping.str2bytes(32,self.name ) # vseg name
2176	byte_stream += mapping.str2bytes(64,self.binpath ) # binpath
2177	byte_stream += mapping.int2bytes(4, self.vbase ) # virtual base address
2178	byte_stream += mapping.int2bytes(8, 0 ) # physical base address
2179	byte_stream += mapping.int2bytes(4, self.length ) # vseg size (bytes)
2180	byte_stream += mapping.int2bytes(4, pseg_id ) # pseg global index
2181	byte_stream += mapping.int2bytes(4, mode_id ) # CXWU flags
2182	byte_stream += mapping.int2bytes(4, vtype_id ) # vseg type
2183	byte_stream += mapping.int2bytes(1, 0 ) # mapped when non zero
2184	byte_stream += mapping.int2bytes(1, self.identity ) # identity mapping
2185	byte_stream += mapping.int2bytes(1, self.local ) # only in local PTAB
2186	byte_stream += mapping.int2bytes(1, self.big ) # to be mapped in BPP
2187
2188	if ( verbose ):
2189	print 'binpath = %s' % self.binpath
2190	print 'vbase = %x' % self.vbase
2191	print 'pbase = 0'
2192	print 'length = %x' % self.length
2193	print 'pseg_id = %d' % pseg_id
2194	print 'mode = %d' % mode_id
2195	print 'type = %d' % vtype_id
2196	print 'mapped = 0'
2197	print 'ident = %d' % self.identity
2198	print 'local = %d' % self.local
2199	print 'big = %d' % self.big
2200
2201	return byte_stream
2202
2203	##################################################################################
2204	class Processor ( object ):
2205	##################################################################################
2206	def __init__( self,
2207	x,
2208	y,
2209	lpid ):
2210
2211	self.index = 0 # global index ( set by addProc() )
2212	self.x = x # x cluster coordinate
2213	self.y = y # y cluster coordinate
2214	self.lpid = lpid # processor local index
2215
2216	return
2217
2218	########################################
2219	def xml( self ): # xml for a processor
2220	return ' <proc index="%d" />\n' % (self.lpid)
2221
2222	####################################################################
2223	def cbin( self, mapping, verbose, expected ): # C binary for Proc
2224
2225	if ( verbose ):
2226	print '*** cbin for proc %d in cluster (%d,%d)' \
2227	% (self.lpid, self.x, self.y)
2228
2229	# check index
2230	if (self.index != expected):
2231	print '[genmap error] in Proc.cbin()'
2232	print ' proc global index = %d / expected = %d' \
2233	% (self.index,expected)
2234	sys.exit(1)
2235
2236	byte_stream = bytearray()
2237	byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index
2238
2239	return byte_stream
2240
2241	##################################################################################
2242	class Pseg ( object ):
2243	##################################################################################
2244	def __init__( self,
2245	name,
2246	base,
2247	size,
2248	x,
2249	y,
2250	segtype ):
2251
2252	assert( segtype in PSEGTYPES )
2253
2254	self.index = 0 # global index ( set by addPseg() )
2255	self.name = name # pseg name (unique in cluster)
2256	self.base = base # physical base address
2257	self.size = size # segment size (bytes)
2258	self.x = x # cluster x coordinate
2259	self.y = y # cluster y coordinate
2260	self.segtype = segtype # RAM / PERI (defined in mapping_info.h)
2261
2262	return
2263
2264	###################################
2265	def xml( self ): # xml for a pseg
2266
2267	s = ' <pseg name="%s" type="%s" base="0x%x" length="0x%x" />\n' \
2268	% (self.name, self.segtype, self.base, self.size)
2269	return s
2270
2271	###########################################################################
2272	def cbin( self, mapping, verbose, expected, cluster ): # C binary for Pseg
2273
2274	if ( verbose ):
2275	print '*** cbin for pseg[%d] %s in cluster[%d,%d]' \
2276	% (self.index, self.name, cluster.x, cluster.y)
2277
2278	# check index
2279	if (self.index != expected):
2280	print '[genmap error] in Pseg.cbin()'
2281	print ' pseg global index = %d / expected = %d' \
2282	% (self.index,expected)
2283	sys.exit(1)
2284
2285	# compute numerical value for segtype
2286	segtype_int = 0xFFFFFFFF
2287	for x in xrange( len(PSEGTYPES) ):
2288	if ( self.segtype == PSEGTYPES[x] ): segtype_int = x
2289
2290	if ( segtype_int == 0xFFFFFFFF ):
2291	print '[genmap error] in Pseg.cbin()'
2292	print ' undefined segment type %s' % self.segtype
2293	sys.exit(1)
2294
2295	byte_stream = bytearray()
2296	byte_stream += mapping.str2bytes(32,self.name) # pseg name
2297	byte_stream += mapping.int2bytes(8 ,self.base) # physical base address
2298	byte_stream += mapping.int2bytes(8 ,self.size) # segment length
2299	byte_stream += mapping.int2bytes(4 ,segtype_int) # segment type
2300	byte_stream += mapping.int2bytes(4 ,cluster.index) # cluster global index
2301	byte_stream += mapping.int2bytes(4 ,0) # linked list of vsegs
2302
2303	if ( verbose ):
2304	print 'pbase = %x' % self.base
2305	print 'size = %x' % self.size
2306	print 'type = %s' % self.segtype
2307
2308	return byte_stream
2309
2310	##################################################################################
2311	class Periph ( object ):
2312	##################################################################################
2313	def __init__( self,
2314	pseg, # associated pseg
2315	ptype, # peripheral type
2316	subtype = 'NONE', # peripheral subtype
2317	channels = 1, # for multi-channels peripherals
2318	arg0 = 0, # optional (semantic depends on ptype)
2319	arg1 = 0, # optional (semantic depends on ptype)
2320	arg2 = 0, # optional (semantic depends on ptype)
2321	arg3 = 0 ): # optional (semantic depends on ptype)
2322
2323	self.index = 0 # global index ( set by addPeriph() )
2324	self.channels = channels
2325	self.ptype = ptype
2326	self.subtype = subtype
2327	self.arg0 = arg0
2328	self.arg1 = arg1
2329	self.arg2 = arg2
2330	self.arg3 = arg3
2331	self.pseg = pseg
2332	self.irqs = []
2333	return
2334
2335	######################################
2336	def xml( self ): # xml for a periph
2337
2338	s = ' <periph type="%s"' % self.ptype
2339	s += ' subtype="%s"' % self.subtype
2340	s += ' psegname="%s"' % self.pseg.name
2341	s += ' channels="%d"' % self.channels
2342	s += ' arg0="%d"' % self.arg0
2343	s += ' arg1="%d"' % self.arg1
2344	s += ' arg2="%d"' % self.arg2
2345	s += ' arg3="%d"' % self.arg3
2346	if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') ):
2347	s += ' >\n'
2348	for irq in self.irqs: s += irq.xml()
2349	s += ' </periph>\n'
2350	else:
2351	s += ' />\n'
2352	return s
2353
2354	######################################################################
2355	def cbin( self, mapping, verbose, expected ): # C binary for Periph
2356
2357	if ( verbose ):
2358	print '*** cbin for periph %s in cluster [%d,%d]' \
2359	% (self.ptype, self.pseg.x, self.pseg.y)
2360
2361	# check index
2362	if (self.index != expected):
2363	print '[genmap error] in Periph.cbin()'
2364	print ' periph global index = %d / expected = %d' \
2365	% (self.index,expected)
2366	sys.exit(1)
2367
2368	# compute pseg global index
2369	pseg_id = self.pseg.index
2370
2371	# compute first irq global index
2372	if ( len(self.irqs) > 0 ):
2373	irq_id = self.irqs[0].index
2374	else:
2375	irq_id = 0
2376
2377	# compute numerical value for ptype
2378	ptype_id = 0xFFFFFFFF
2379	for x in xrange( len(PERIPHTYPES) ):
2380	if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x
2381
2382	if ( ptype_id == 0xFFFFFFFF ):
2383	print '[genmap error] in Periph.cbin()'
2384	print ' undefined peripheral type %s' % self.ptype
2385	sys.exit(1)
2386
2387	# compute numerical value for subtype
2388	subtype_id = 0xFFFFFFFF
2389	if (self.ptype == 'IOC'):
2390	for x in xrange( len(IOCSUBTYPES) ):
2391	if ( self.subtype == IOCSUBTYPES[x] ): subtype_id = x
2392	if (self.ptype == 'MWR'):
2393	for x in xrange( len(MWRSUBTYPES) ):
2394	if ( self.subtype == MWRSUBTYPES[x] ): subtype_id = x
2395
2396	byte_stream = bytearray()
2397	byte_stream += mapping.int2bytes(4,ptype_id) # peripheral type
2398	byte_stream += mapping.int2bytes(4,subtype_id) # peripheral subtype
2399	byte_stream += mapping.int2bytes(4,pseg_id) # pseg global index
2400	byte_stream += mapping.int2bytes(4,self.channels) # number of channels
2401	byte_stream += mapping.int2bytes(4,self.arg0) # optionnal arg0
2402	byte_stream += mapping.int2bytes(4,self.arg1) # optionnal arg1
2403	byte_stream += mapping.int2bytes(4,self.arg2) # optionnal arg2
2404	byte_stream += mapping.int2bytes(4,self.arg3) # optionnal arg3
2405	byte_stream += mapping.int2bytes(4,len(self.irqs)) # number of input irqs
2406	byte_stream += mapping.int2bytes( 4 , irq_id ) # global index
2407
2408	if ( verbose ):
2409	print 'ptype = %d' % ptype_id
2410	print 'subtype = %d' % subtype_id
2411	print 'pseg_id = %d' % pseg_id
2412	print 'nb_irqs = %d' % len( self.irqs )
2413	print 'irq_id = %d' % irq_id
2414	return byte_stream
2415
2416	##################################################################################
2417	class Irq ( object ):
2418	##################################################################################
2419	def __init__( self,
2420	irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only)
2421	srcid, # input IRQ index (for XCU or PIC)
2422	isrtype, # Type of ISR to be executed
2423	channel = 0 ): # channel index for multi-channel ISR
2424
2425	assert irqtype in IRQTYPES
2426	assert isrtype in ISRTYPES
2427	assert srcid < 32
2428
2429	self.index = 0 # global index ( set by addIrq() )
2430	self.irqtype = irqtype # IRQ type
2431	self.srcid = srcid # source IRQ index
2432	self.isrtype = isrtype # ISR type
2433	self.channel = channel # channel index (for multi-channels ISR)
2434	return
2435
2436	################################
2437	def xml( self ): # xml for Irq
2438
2439	s = ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" />\n' \
2440	% ( self.irqtype, self.srcid, self.isrtype, self.channel )
2441	return s
2442
2443	####################################################################
2444	def cbin( self, mapping, verbose, expected ): # C binary for Irq
2445
2446	if ( verbose ):
2447	print '*** cbin for irq[%d]' % (self.index)
2448
2449	# check index
2450	if (self.index != expected):
2451	print '[genmap error] in Irq.cbin()'
2452	print ' irq global index = %d / expected = %d' \
2453	% (self.index,expected)
2454	sys.exit(1)
2455
2456	# compute numerical value for irqtype
2457	irqtype_id = 0xFFFFFFFF
2458	for x in xrange( len(IRQTYPES) ):
2459	if ( self.irqtype == IRQTYPES[x] ): irqtype_id = x
2460
2461	if ( irqtype_id == 0xFFFFFFFF ):
2462	print '[genmap error] in Irq.cbin()'
2463	print ' undefined irqtype %s' % self.irqtype
2464	sys.exit(1)
2465
2466	# compute numerical value for isrtype
2467	isrtype_id = 0xFFFFFFFF
2468	for x in xrange( len(ISRTYPES) ):
2469	if ( self.isrtype == ISRTYPES[x] ): isrtype_id = x
2470
2471	if ( isrtype_id == 0xFFFFFFFF ):
2472	print '[genmap error] in Irq.cbin()'
2473	print ' undefined isrtype %s' % self.isrtype
2474	sys.exit(1)
2475
2476	byte_stream = bytearray()
2477	byte_stream += mapping.int2bytes( 4, irqtype_id )
2478	byte_stream += mapping.int2bytes( 4, self.srcid )
2479	byte_stream += mapping.int2bytes( 4, isrtype_id )
2480	byte_stream += mapping.int2bytes( 4, self.channel )
2481	byte_stream += mapping.int2bytes( 4, 0 )
2482	byte_stream += mapping.int2bytes( 4, 0 )
2483
2484	if ( verbose ):
2485	print 'irqtype = %s' % self.irqtype
2486	print 'srcid = %d' % self.srcid
2487	print 'isrtype = %s' % self.isrtype
2488	print 'channel = %d' % self.channel
2489
2490	return byte_stream
2491
2492	# Local Variables:
2493	# tab-width: 4;
2494	# c-basic-offset: 4;
2495	# c-file-offsets:((innamespace . 0)(inline-open . 0));
2496	# indent-tabs-mode: nil;
2497	# End:
2498	#
2499	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
2500

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