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mapping.py @ 521

Last change on this file since 521 was 520, checked in by alain, 11 years ago

1) Simplification of the mapping objects: the coproc and cp_port objects
have been removedr.:A coprocessor is now described as a peripheral with MWR type,
and the coprocessor type is defined by the subtype argument.
The addPeriph() prototype has been modified to support 4 arguments: arg0, arg1, arg2, arg3
(the semanting depends on the peripheral type).

2) A new application, called "coproc", and using the GCD coprocessor and
the MWMR_DMA controller, has been introduced in genmap.

Property svn:executable set to *

File size: 100.1 KB

Line
1	#!/usr/bin/env python
2
3	import sys
4
5	########################################################################################
6	# file : giet_mapping.py
7	# date : april 2014
8	# author : Alain Greiner
9	########################################################################################
10	# This file contains the classes required to define a mapping for the GIET_VM.
11	# - A 'Mapping' contains a set of 'Cluster' (hardware architecture)
12	# a set of 'Vseg' (kernel glogals virtual segments)
13	# a set of 'Vspace' (one or several user applications)
14	# - A 'Cluster' contains a set of 'Pseg' (physical segments in cluster)
15	# a set of 'Proc' (processors in cluster)
16	# a set of 'Periph' (peripherals in cluster)
17	# - A 'Vspace' contains a set of 'Vseg' (user virtual segments)
18	# a set of 'Task' (user parallel tasks)
19	# - A 'Periph' contains a set of 'Irq' (only for XCU and PIC types )
20	########################################################################################
21	# Implementation Note
22	# The objects used to describe a mapping are distributed in the PYTHON structure:
23	# For example the psegs set is split in several subsets (one subset per cluster),
24	# or the tasks set is split in several subsets (one subset per vspace), etc...
25	# In the C binary data structure used by the giet_vm, all objects of same type
26	# are stored in a linear array (one single array for all psegs for example).
27	# For all objects, we compute and store in the PYTHON object itself a "global index"
28	# corresponding to the index in this global array, and this index can be used as
29	# a pseudo-pointer to identify a specific object of a given type.
30	########################################################################################
31
32	########################################################################################
33	# Various constants
34	########################################################################################
35
36	PADDR_WIDTH = 40 # number of bits for physical address
37	X_WIDTH = 4 # number of bits encoding x coordinate
38	Y_WIDTH = 4 # number of bits encoding y coordinate
39	P_WIDTH = 4 # number of bits encoding local proc_id
40	VPN_ANTI_MASK = 0x00000FFF # mask virtual address to get offset in a small page
41	BPN_MASK = 0xFFE00000 # mask virtual address to get the BPN (big page)
42	PERI_INCREMENT = 0x10000 # virtual address increment for replicated l vsegs
43	RESET_ADDRESS = 0xBFC00000 # Processor wired boot_address
44	MAPPING_SIGNATURE = 0xDACE2014 # Magic number indicating a valid C binary struture
45
46	########################################################################################
47	# These lists must be consistent with values defined in
48	# mapping_info.h / xml_driver.c /xml_parser.c
49	########################################################################################
50	PERIPHTYPES = [
51	'CMA',
52	'DMA',
53	'FBF',
54	'IOB',
55	'IOC',
56	'MMC',
57	'MWR',
58	'NIC',
59	'ROM',
60	'SIM',
61	'TIM',
62	'TTY',
63	'XCU',
64	'PIC',
65	'DROM',
66	]
67
68	IOCSUBTYPES = [
69	'BDV',
70	'HBA',
71	'SPI',
72	'NONE',
73	]
74
75	MWRSUBTYPES = [
76	'GCD',
77	'DCT',
78	]
79
80	######################################################################################
81	# These lists must be consistent with values defined in
82	# irq_handler.c / irq_handler.h / xml_driver.c / xml_parser.c
83	######################################################################################
84	IRQTYPES = [
85	'HWI',
86	'WTI',
87	'PTI',
88	]
89
90	ISRTYPES = [
91	'ISR_DEFAULT',
92	'ISR_TICK',
93	'ISR_TTY_RX',
94	'ISR_TTY_TX',
95	'ISR_BDV',
96	'ISR_TIMER',
97	'ISR_WAKUP',
98	'ISR_NIC_RX',
99	'ISR_NIC_TX',
100	'ISR_CMA',
101	'ISR_MMC',
102	'ISR_DMA',
103	'ISR_SPI',
104	'ISR_MWR'
105	]
106
107	VSEGTYPES = [
108	'ELF',
109	'BLOB',
110	'PTAB',
111	'PERI',
112	'MWMR', # deprecated
113	'LOCK', # deprecated
114	'BUFFER',
115	'BARRIER', # deprecated
116	'CONST', # deprecated
117	'MEMSPACE', # deprecated
118	'SCHED',
119	'HEAP',
120	]
121
122	VSEGMODES = [
123	'____',
124	'___U',
125	'__W_',
126	'__WU',
127	'_X__',
128	'_X_U',
129	'_XW_',
130	'_XWU',
131	'C___',
132	'C__U',
133	'C_W_',
134	'C_WU',
135	'CX__',
136	'CX_U',
137	'CXW_',
138	'CXWU',
139	]
140
141	PSEGTYPES = [
142	'RAM',
143	'PERI',
144	]
145
146	#######################################################################################
147	class Mapping( object ):
148	#######################################################################################
149	def __init__( self,
150	name, # mapping name
151	x_size, # number of clusters in a row
152	y_size, # number of clusters in a column
153	nprocs, # max number of processors per cluster
154	x_width = X_WIDTH, # number of bits encoding x coordinate
155	y_width = Y_WIDTH, # number of bits encoding y coordinate
156	p_width = P_WIDTH, # number of bits encoding lpid
157	paddr_width = PADDR_WIDTH, # number of bits for physical address
158	coherence = 1, # hardware cache coherence if non-zero
159	irq_per_proc = 1, # number or IRQs from XCU to processor
160	use_ramdisk = False, # use ramdisk when true
161	x_io = 0, # cluster_io x coordinate
162	y_io = 0, # cluster_io y coordinate
163	peri_increment = PERI_INCREMENT, # address increment for globals
164	reset_address = RESET_ADDRESS, # Processor wired boot_address
165	ram_base = 0, # RAM physical base in cluster[0,0]
166	ram_size = 0 ): # RAM size in each cluster (bytes)
167
168	assert ( x_size <= (1<<X_WIDTH) )
169	assert ( y_size <= (1<<Y_WIDTH) )
170	assert ( nprocs <= (1<<P_WIDTH) )
171
172	self.signature = MAPPING_SIGNATURE
173	self.name = name
174	self.name = name
175	self.paddr_width = paddr_width
176	self.coherence = coherence
177	self.x_size = x_size
178	self.y_size = y_size
179	self.nprocs = nprocs
180	self.x_width = x_width
181	self.y_width = y_width
182	self.p_width = p_width
183	self.irq_per_proc = irq_per_proc
184	self.use_ramdisk = use_ramdisk
185	self.x_io = x_io
186	self.y_io = y_io
187	self.peri_increment = peri_increment
188	self.reset_address = reset_address
189	self.ram_base = ram_base
190	self.ram_size = ram_size
191
192	self.total_vspaces = 0
193	self.total_globals = 0
194	self.total_psegs = 0
195	self.total_vsegs = 0
196	self.total_tasks = 0
197	self.total_procs = 0
198	self.total_irqs = 0
199	self.total_periphs = 0
200
201	self.clusters = []
202	self.globs = []
203	self.vspaces = []
204
205	for x in xrange( self.x_size ):
206	for y in xrange( self.y_size ):
207	cluster = Cluster( x , y )
208	cluster.index = (x * self.y_size) + y
209	self.clusters.append( cluster )
210
211	return
212
213	########################## add a ram pseg in a cluster
214	def addRam( self,
215	name, # pseg name
216	base, # pseg base address
217	size ): # pseg length (bytes)
218
219	# computes cluster index and coordinates from the base address
220	paddr_lsb_width = self.paddr_width - self.x_width - self.y_width
221	cluster_xy = base >> paddr_lsb_width
222	x = cluster_xy >> (self.y_width);
223	y = cluster_xy & ((1 << self.y_width) - 1)
224	cluster_id = (x * self.y_size) + y
225
226	assert (base & VPN_ANTI_MASK) == 0
227
228	assert (x < self.x_size) and (y < self.y_size)
229
230	assert ( (base & ((1<<paddr_lsb_width)-1)) == self.ram_base )
231
232	assert ( size == self.ram_size )
233
234	# add one pseg in the mapping
235	pseg = Pseg( name, base, size, x, y, 'RAM' )
236	self.clusters[cluster_id].psegs.append( pseg )
237	pseg.index = self.total_psegs
238	self.total_psegs += 1
239
240	return pseg
241
242	########################## add a peripheral and the associated pseg in a cluster
243	def addPeriph( self,
244	name, # associated pseg name
245	base, # associated pseg base address
246	size, # associated pseg length (bytes)
247	ptype, # peripheral type
248	subtype = 'NONE', # peripheral subtype
249	channels = 1, # number of channels
250	arg0 = 0, # optional argument (semantic depends on ptype)
251	arg1 = 0, # optional argument (semantic depends on ptype)
252	arg2 = 0, # optional argument (semantic depends on ptype)
253	arg3 = 0 ): # optional argument (semantic depends on ptype)
254
255	# computes cluster index and coordinates from the base address
256	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
257	x = cluster_xy >> (self.y_width);
258	y = cluster_xy & ((1 << self.y_width) - 1)
259	cluster_id = (x * self.y_size) + y
260
261	assert (x < self.x_size) and (y < self.y_size)
262
263	assert (base & VPN_ANTI_MASK) == 0
264
265	assert ptype in PERIPHTYPES
266
267	if (ptype == 'IOC'): assert subtype in IOCSUBTYPES
268	if (ptype == 'MWR'): assert subtype in MWRSUBTYPES
269
270	# add one pseg into mapping
271	pseg = Pseg( name, base, size, x, y, 'PERI' )
272	self.clusters[cluster_id].psegs.append( pseg )
273	pseg.index = self.total_psegs
274	self.total_psegs += 1
275
276	# add one periph into mapping
277	periph = Periph( pseg, ptype, subtype, channels, arg0, arg1, arg2, arg3 )
278	self.clusters[cluster_id].periphs.append( periph )
279	periph.index = self.total_periphs
280	self.total_periphs += 1
281
282	return periph
283
284	################################ add an IRQ in a peripheral
285	def addIrq( self,
286	periph, # peripheral containing IRQ (PIC or XCU)
287	index, # peripheral input port index
288	isrtype, # ISR type
289	channel = 0 ): # channel for multi-channels ISR
290
291	assert isrtype in ISRTYPES
292
293	assert index < 32
294
295	# add one irq into mapping
296	irq = Irq( 'HWI', index , isrtype, channel )
297	periph.irqs.append( irq )
298	irq.index = self.total_irqs
299	self.total_irqs += 1
300
301	return irq
302
303	########################## add a processor in a cluster
304	def addProc( self,
305	x, # cluster x coordinate
306	y, # cluster y coordinate
307	lpid ): # processor local index
308
309	assert (x < self.x_size) and (y < self.y_size)
310
311	cluster_id = (x * self.y_size) + y
312
313	# add one proc into mapping
314	proc = Processor( x, y, lpid )
315	self.clusters[cluster_id].procs.append( proc )
316	proc.index = self.total_procs
317	self.total_procs += 1
318
319	return proc
320
321	############################ add one global vseg into mapping
322	def addGlobal( self,
323	name, # vseg name
324	vbase, # virtual base address
325	length, # vseg length (bytes)
326	mode, # CXWU flags
327	vtype, # vseg type
328	x, # destination x coordinate
329	y, # destination y coordinate
330	pseg, # destination pseg name
331	identity = False, # identity mapping required if true
332	local = False, # only mapped in local PTAB if true
333	big = False, # to be mapped in a big physical page
334	binpath = '' ): # pathname for binary code if required
335
336	# two global vsegs must not overlap if they have different names
337	for prev in self.globs:
338	if ( ((prev.vbase + prev.length) > vbase ) and
339	((vbase + length) > prev.vbase) and
340	(prev.name != name) ):
341	print '[genmap error] in addGlobal()'
342	print ' global vseg %s overlap %s' % (name, prev.name)
343	print ' %s : base = %x / size = %x' %( name, vbase, size )
344	print ' %s : base = %x / size = %x' %( prev.name, prev.vbase, prev.size )
345	sys.exit(1)
346
347	# add one vseg into mapping
348	vseg = Vseg( name, vbase, length, mode, vtype, x, y, pseg,
349	identity = identity, local = local, big = big, binpath = binpath )
350
351	self.globs.append( vseg )
352	self.total_globals += 1
353	vseg.index = self.total_vsegs
354	self.total_vsegs += 1
355
356	return
357
358	################################ add a vspace into mapping
359	def addVspace( self,
360	name, # vspace name
361	startname ): # name of vseg containing start_vector
362
363	# add one vspace into mapping
364	vspace = Vspace( name, startname )
365	self.vspaces.append( vspace )
366	vspace.index = self.total_vspaces
367	self.total_vspaces += 1
368
369	return vspace
370
371	################################# add a private vseg in a vspace
372	def addVseg( self,
373	vspace, # vspace containing the vseg
374	name, # vseg name
375	vbase, # virtual base address
376	length, # vseg length (bytes)
377	mode, # CXWU flags
378	vtype, # vseg type
379	x, # destination x coordinate
380	y, # destination y coordinate
381	pseg, # destination pseg name
382	local = False, # only mapped in local PTAB if true
383	big = False, # to be mapped in a big physical page
384	binpath = '' ): # pathname for binary code
385
386	assert mode in VSEGMODES
387
388	assert vtype in VSEGTYPES
389
390	assert (x < self.x_size) and (y < self.y_size)
391
392	# add one vseg into mapping
393	vseg = Vseg( name, vbase, length, mode, vtype, x, y, pseg,
394	identity = False, local = local, big = big, binpath = binpath )
395	vspace.vsegs.append( vseg )
396	vseg.index = self.total_vsegs
397	self.total_vsegs += 1
398
399	return vseg
400
401	################################ add a task in a vspace
402	def addTask( self,
403	vspace, # vspace containing task
404	name, # task name
405	trdid, # task index in vspace
406	x, # destination x coordinate
407	y, # destination y coordinate
408	lpid, # destination processor local index
409	stackname, # name of vseg containing stack
410	heapname, # name of vseg containing heap
411	startid ): # index in start_vector
412
413	assert (x < self.x_size) and (y < self.y_size)
414	assert lpid < self.nprocs
415
416	# add one task into mapping
417	task = Task( name, trdid, x, y, lpid, stackname, heapname, startid )
418	vspace.tasks.append( task )
419	task.index = self.total_tasks
420	self.total_tasks += 1
421
422	return task
423
424	#################################
425	def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array
426
427	byte_stream = bytearray()
428	length = len( s )
429	if length < (nbytes - 1):
430	for b in s:
431	byte_stream.append( b )
432	for x in xrange(nbytes-length):
433	byte_stream.append( '\0' )
434	else:
435	print '[genmap error] in str2bytes()'
436	print ' string %s too long' % s
437	sys.exit(1)
438
439	return byte_stream
440
441	###################################
442	def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array
443
444	byte_stream = bytearray()
445	for n in xrange( nbytes ):
446	byte_stream.append( (val >> (n<<3)) & 0xFF )
447
448	return byte_stream
449
450	################
451	def xml( self ): # compute string for map.xml file generation
452
453	s = '<?xml version="1.0"?>\n\n'
454	s += '<mapping_info signature = "0x%x"\n' % (self.signature)
455	s += ' name = "%s"\n' % (self.name)
456	s += ' x_size = "%d"\n' % (self.x_size)
457	s += ' y_size = "%d"\n' % (self.y_size)
458	s += ' x_width = "%d"\n' % (self.x_width)
459	s += ' y_width = "%d"\n' % (self.y_width)
460	s += ' irq_per_proc = "%d"\n' % (self.irq_per_proc)
461	s += ' use_ramdisk = "%d"\n' % (self.use_ramdisk)
462	s += ' x_io = "%d"\n' % (self.x_io)
463	s += ' y_io = "%d" >\n' % (self.y_io)
464	s += '\n'
465
466	s += ' <clusterset>\n'
467	for x in xrange ( self.x_size ):
468	for y in xrange ( self.y_size ):
469	cluster_id = (x * self.y_size) + y
470	s += self.clusters[cluster_id].xml()
471	s += ' </clusterset>\n'
472	s += '\n'
473
474	s += ' <globalset>\n'
475	for vseg in self.globs: s += vseg.xml()
476	s += ' </globalset>\n'
477	s += '\n'
478
479	s += ' <vspaceset>\n'
480	for vspace in self.vspaces: s += vspace.xml()
481	s += ' </vspaceset>\n'
482
483	s += '</mapping_info>\n'
484	return s
485
486	##########################
487	def cbin( self, verbose ): # C binary structure for map.bin file generation
488
489	byte_stream = bytearray()
490
491	# header
492	byte_stream += self.int2bytes(4, self.signature)
493	byte_stream += self.int2bytes(4, self.x_size)
494	byte_stream += self.int2bytes(4, self.y_size)
495	byte_stream += self.int2bytes(4, self.x_width)
496	byte_stream += self.int2bytes(4, self.y_width)
497	byte_stream += self.int2bytes(4, self.x_io)
498	byte_stream += self.int2bytes(4, self.y_io)
499	byte_stream += self.int2bytes(4, self.irq_per_proc)
500	byte_stream += self.int2bytes(4, self.use_ramdisk)
501	byte_stream += self.int2bytes(4, self.total_globals)
502	byte_stream += self.int2bytes(4, self.total_vspaces)
503	byte_stream += self.int2bytes(4, self.total_psegs)
504	byte_stream += self.int2bytes(4, self.total_vsegs)
505	byte_stream += self.int2bytes(4, self.total_tasks)
506	byte_stream += self.int2bytes(4, self.total_procs)
507	byte_stream += self.int2bytes(4, self.total_irqs)
508	byte_stream += self.int2bytes(4, self.total_periphs)
509	byte_stream += self.str2bytes(32, self.name)
510
511	if ( verbose ):
512	print '\n'
513	print 'name = %s' % self.name
514	print 'signature = %x' % self.signature
515	print 'x_size = %d' % self.x_size
516	print 'y_size = %d' % self.y_size
517	print 'x_width = %d' % self.x_width
518	print 'y_width = %d' % self.y_width
519	print 'x_io = %d' % self.x_io
520	print 'y_io = %d' % self.y_io
521	print 'irq_per_proc = %d' % self.irq_per_proc
522	print 'use_ramdisk = %d' % self.use_ramdisk
523	print 'total_globals = %d' % self.total_globals
524	print 'total_psegs = %d' % self.total_psegs
525	print 'total_vsegs = %d' % self.total_vsegs
526	print 'total_tasks = %d' % self.total_tasks
527	print 'total_procs = %d' % self.total_procs
528	print 'total_irqs = %d' % self.total_irqs
529	print 'total_periphs = %d' % self.total_periphs
530	print '\n'
531
532	# clusters array
533	index = 0
534	for cluster in self.clusters:
535	byte_stream += cluster.cbin( self, verbose, index )
536	index += 1
537
538	if ( verbose ): print '\n'
539
540	# psegs array
541	index = 0
542	for cluster in self.clusters:
543	for pseg in cluster.psegs:
544	byte_stream += pseg.cbin( self, verbose, index, cluster )
545	index += 1
546
547	if ( verbose ): print '\n'
548
549	# vspaces array
550	index = 0
551	for vspace in self.vspaces:
552	byte_stream += vspace.cbin( self, verbose, index )
553	index += 1
554
555	if ( verbose ): print '\n'
556
557	# vsegs array
558	index = 0
559	for vseg in self.globs:
560	byte_stream += vseg.cbin( self, verbose, index )
561	index += 1
562	for vspace in self.vspaces:
563	for vseg in vspace.vsegs:
564	byte_stream += vseg.cbin( self, verbose, index )
565	index += 1
566
567	if ( verbose ): print '\n'
568
569	# tasks array
570	index = 0
571	for vspace in self.vspaces:
572	for task in vspace.tasks:
573	byte_stream += task.cbin( self, verbose, index, vspace )
574	index += 1
575
576	if ( verbose ): print '\n'
577
578	# procs array
579	index = 0
580	for cluster in self.clusters:
581	for proc in cluster.procs:
582	byte_stream += proc.cbin( self, verbose, index )
583	index += 1
584
585	if ( verbose ): print '\n'
586
587	# irqs array
588	index = 0
589	for cluster in self.clusters:
590	for periph in cluster.periphs:
591	for irq in periph.irqs:
592	byte_stream += irq.cbin( self, verbose, index )
593	index += 1
594
595	if ( verbose ): print '\n'
596
597	# periphs array
598	index = 0
599	for cluster in self.clusters:
600	for periph in cluster.periphs:
601	byte_stream += periph.cbin( self, verbose, index )
602	index += 1
603
604	return byte_stream
605	# end of cbin()
606
607	##################################################################################
608	def giet_vsegs( self ): # compute string for giet_vsegs.ld file generation
609	# required by giet_vm compilation
610
611	# search the vsegs required for the giet_vsegs.ld
612	boot_code_found = False
613	boot_data_found = False
614	kernel_uncdata_found = False
615	kernel_data_found = False
616	kernel_code_found = False
617	kernel_init_found = False
618	for vseg in self.globs:
619
620	if ( vseg.name == 'seg_boot_code' ):
621	boot_code_vbase = vseg.vbase
622	boot_code_size = vseg.length
623	boot_code_found = True
624
625	if ( vseg.name == 'seg_boot_data' ):
626	boot_data_vbase = vseg.vbase
627	boot_data_size = vseg.length
628	boot_data_found = True
629
630	if ( vseg.name == 'seg_kernel_data' ):
631	kernel_data_vbase = vseg.vbase
632	kernel_data_size = vseg.length
633	kernel_data_found = True
634
635	if ( vseg.name == 'seg_kernel_code' ):
636	kernel_code_vbase = vseg.vbase
637	kernel_code_size = vseg.length
638	kernel_code_found = True
639
640	if ( vseg.name == 'seg_kernel_init' ):
641	kernel_init_vbase = vseg.vbase
642	kernel_init_size = vseg.length
643	kernel_init_found = True
644
645	# check if all required vsegs have been found
646	if ( boot_code_found == False ):
647	print '[genmap error] in giet_vsegs()'
648	print ' seg_boot_code vseg missing'
649	sys.exit()
650
651	if ( boot_data_found == False ):
652	print '[genmap error] in giet_vsegs()'
653	print ' seg_boot_data vseg missing'
654	sys.exit()
655
656	if ( kernel_data_found == False ):
657	print '[genmap error] in giet_vsegs()'
658	print ' seg_kernel_data vseg missing'
659	sys.exit()
660
661	if ( kernel_code_found == False ):
662	print '[genmap error] in giet_vsegs()'
663	print ' seg_kernel_code vseg missing'
664	sys.exit()
665
666	if ( kernel_init_found == False ):
667	print '[genmap error] in giet_vsegs()'
668	print ' seg_kernel_init vseg missing'
669	sys.exit()
670
671	# build string
672	s = '/* Generated by genmap for %s */\n' % self.name
673	s += '\n'
674
675	s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase
676	s += 'boot_code_size = 0x%x;\n' % boot_code_size
677	s += '\n'
678	s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase
679	s += 'boot_data_size = 0x%x;\n' % boot_data_size
680	s += '\n'
681	s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase
682	s += 'kernel_code_size = 0x%x;\n' % kernel_code_size
683	s += '\n'
684	s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase
685	s += 'kernel_data_size = 0x%x;\n' % kernel_data_size
686	s += '\n'
687	s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase
688	s += 'kernel_init_size = 0x%x;\n' % kernel_init_size
689	s += '\n'
690
691	return s
692
693	###################################################################################
694	def hard_config( self ): # compute string for hard_config.h file generation,
695	# required by
696	# - top.cpp compilation
697	# - giet_vm compilation
698	# - tsar_preloader compilation
699
700	nb_total_procs = 0
701
702	# for each peripheral type, define default values
703	# for pbase address, size, number of components, and channels
704	nb_cma = 0
705	cma_channels = 0
706	seg_cma_base = 0xFFFFFFFF
707	seg_cma_size = 0
708
709	nb_dma = 0
710	dma_channels = 0
711	seg_dma_base = 0xFFFFFFFF
712	seg_dma_size = 0
713
714	nb_fbf = 0
715	fbf_channels = 0
716	seg_fbf_base = 0xFFFFFFFF
717	seg_fbf_size = 0
718	fbf_arg0 = 0
719	fbf_arg1 = 0
720
721	nb_iob = 0
722	iob_channels = 0
723	seg_iob_base = 0xFFFFFFFF
724	seg_iob_size = 0
725
726	nb_ioc = 0
727	ioc_channels = 0
728	seg_ioc_base = 0xFFFFFFFF
729	seg_ioc_size = 0
730
731	nb_mmc = 0
732	mmc_channels = 0
733	seg_mmc_base = 0xFFFFFFFF
734	seg_mmc_size = 0
735
736	nb_mwr = 0
737	mwr_channels = 0
738	seg_mwr_base = 0xFFFFFFFF
739	seg_mwr_size = 0
740	mwr_arg0 = 0
741	mwr_arg1 = 0
742	mwr_arg2 = 0
743	mwr_arg3 = 0
744
745	nb_nic = 0
746	nic_channels = 0
747	seg_nic_base = 0xFFFFFFFF
748	seg_nic_size = 0
749
750	nb_pic = 0
751	pic_channels = 0
752	seg_pic_base = 0xFFFFFFFF
753	seg_pic_size = 0
754
755	nb_rom = 0
756	rom_channels = 0
757	seg_rom_base = 0xFFFFFFFF
758	seg_rom_size = 0
759
760	nb_sim = 0
761	sim_channels = 0
762	seg_sim_base = 0xFFFFFFFF
763	seg_sim_size = 0
764
765	nb_tim = 0
766	tim_channels = 0
767	seg_tim_base = 0xFFFFFFFF
768	seg_tim_size = 0
769
770	nb_tty = 0
771	tty_channels = 0
772	seg_tty_base = 0xFFFFFFFF
773	seg_tty_size = 0
774
775	nb_xcu = 0
776	xcu_channels = 0
777	seg_xcu_base = 0xFFFFFFFF
778	seg_xcu_size = 0
779	xcu_arg0 = 0
780
781	nb_drom = 0
782	drom_channels = 0
783	seg_drom_base = 0xFFFFFFFF
784	seg_drom_size = 0
785
786	use_bdv = False
787	use_spi = False
788	use_hba = False
789
790	# get peripherals attributes
791	for cluster in self.clusters:
792	for periph in cluster.periphs:
793	if ( periph.ptype == 'CMA' ):
794	seg_cma_base = periph.pseg.base & 0xFFFFFFFF
795	seg_cma_size = periph.pseg.size
796	cma_channels = periph.channels
797	nb_cma +=1
798
799	elif ( periph.ptype == 'DMA' ):
800	seg_dma_base = periph.pseg.base & 0xFFFFFFFF
801	seg_dma_size = periph.pseg.size
802	dma_channels = periph.channels
803	nb_dma +=1
804
805	elif ( periph.ptype == 'FBF' ):
806	seg_fbf_base = periph.pseg.base & 0xFFFFFFFF
807	seg_fbf_size = periph.pseg.size
808	fbf_channels = periph.channels
809	fbf_arg0 = periph.arg0
810	fbf_arg1 = periph.arg1
811	nb_fbf +=1
812
813	elif ( periph.ptype == 'IOB' ):
814	seg_iob_base = periph.pseg.base & 0xFFFFFFFF
815	seg_iob_size = periph.pseg.size
816	iob_channels = periph.channels
817	nb_iob +=1
818
819	elif ( periph.ptype == 'IOC' ):
820	seg_ioc_base = periph.pseg.base & 0xFFFFFFFF
821	seg_ioc_size = periph.pseg.size
822	ioc_channels = periph.channels
823	nb_ioc += 1
824
825	if self.use_ramdisk: continue
826
827	if ( periph.subtype == 'BDV' ): use_bdv = True
828	elif ( periph.subtype == 'HBA' ): use_hba = True
829	elif ( periph.subtype == 'SPI' ): use_spi = True
830
831	elif ( periph.ptype == 'MMC' ):
832	seg_mmc_base = periph.pseg.base & 0xFFFFFFFF
833	seg_mmc_size = periph.pseg.size
834	mmc_channels = periph.channels
835	nb_mmc +=1
836
837	elif ( periph.ptype == 'MWR' ):
838	seg_mwr_base = periph.pseg.base & 0xFFFFFFFF
839	seg_mwr_size = periph.pseg.size
840	mwr_channels = periph.channels
841	mwr_arg0 = periph.arg0
842	mwr_arg1 = periph.arg1
843	mwr_arg2 = periph.arg2
844	mwr_arg3 = periph.arg3
845	nb_mwr +=1
846
847	elif ( periph.ptype == 'ROM' ):
848	seg_rom_base = periph.pseg.base & 0xFFFFFFFF
849	seg_rom_size = periph.pseg.size
850	rom_channels = periph.channels
851	nb_rom +=1
852
853	elif ( periph.ptype == 'DROM' ):
854	seg_drom_base = periph.pseg.base & 0xFFFFFFFF
855	seg_drom_size = periph.pseg.size
856	drom_channels = periph.channels
857	nb_drom +=1
858
859	elif ( periph.ptype == 'SIM' ):
860	seg_sim_base = periph.pseg.base & 0xFFFFFFFF
861	seg_sim_size = periph.pseg.size
862	sim_channels = periph.channels
863	nb_sim +=1
864
865	elif ( periph.ptype == 'NIC' ):
866	seg_nic_base = periph.pseg.base & 0xFFFFFFFF
867	seg_nic_size = periph.pseg.size
868	nic_channels = periph.channels
869	nb_nic +=1
870
871	elif ( periph.ptype == 'PIC' ):
872	seg_pic_base = periph.pseg.base & 0xFFFFFFFF
873	seg_pic_size = periph.pseg.size
874	pic_channels = periph.channels
875	nb_pic +=1
876
877	elif ( periph.ptype == 'TIM' ):
878	seg_tim_base = periph.pseg.base & 0xFFFFFFFF
879	seg_tim_size = periph.pseg.size
880	tim_channels = periph.channels
881	nb_tim +=1
882
883	elif ( periph.ptype == 'TTY' ):
884	seg_tty_base = periph.pseg.base & 0xFFFFFFFF
885	seg_tty_size = periph.pseg.size
886	tty_channels = periph.channels
887	nb_tty +=1
888
889	elif ( periph.ptype == 'XCU' ):
890	seg_xcu_base = periph.pseg.base & 0xFFFFFFFF
891	seg_xcu_size = periph.pseg.size
892	xcu_channels = periph.channels
893	xcu_arg0 = periph.arg0
894	nb_xcu +=1
895
896	# no more than two access to external peripherals
897	assert ( nb_fbf <= 2 )
898	assert ( nb_cma <= 2 )
899	assert ( nb_ioc <= 2 )
900	assert ( nb_nic <= 2 )
901	assert ( nb_tim <= 2 )
902	assert ( nb_tty <= 2 )
903	assert ( nb_pic <= 2 )
904
905	# one and only one type of IOC controller
906	nb_iocs = 0
907	if use_hba : nb_iocs += 1
908	if use_bdv : nb_iocs += 1
909	if use_spi : nb_iocs += 1
910	if self.use_ramdisk: nb_iocs += 1
911	assert ( nb_iocs == 1 )
912
913	# Compute total number of processors
914	for cluster in self.clusters:
915	nb_total_procs += len( cluster.procs )
916
917	# Compute physical addresses for BOOT vsegs
918	boot_mapping_found = False
919	boot_code_found = False
920	boot_data_found = False
921	boot_stack_found = False
922
923	for vseg in self.globs:
924	if ( vseg.name == 'seg_boot_mapping' ):
925	boot_mapping_base = vseg.vbase
926	boot_mapping_size = vseg.length
927	boot_mapping_identity = vseg.identity
928	boot_mapping_found = True
929
930	if ( vseg.name == 'seg_boot_code' ):
931	boot_code_base = vseg.vbase
932	boot_code_size = vseg.length
933	boot_code_identity = vseg.identity
934	boot_code_found = True
935
936	if ( vseg.name == 'seg_boot_data' ):
937	boot_data_base = vseg.vbase
938	boot_data_size = vseg.length
939	boot_data_identity = vseg.identity
940	boot_data_found = True
941
942	if ( vseg.name == 'seg_boot_stack' ):
943	boot_stack_base = vseg.vbase
944	boot_stack_size = vseg.length
945	boot_stack_identity = vseg.identity
946	boot_stack_found = True
947
948	# check that BOOT vsegs are found and identity mapping
949	if ( (boot_mapping_found == False) or (boot_mapping_identity == False) ):
950	print '[genmap error] in hard_config()'
951	print ' seg_boot_mapping missing or not identity mapping'
952	sys.exit()
953
954	if ( (boot_code_found == False) or (boot_code_identity == False) ):
955	print '[genmap error] in hard_config()'
956	print ' seg_boot_code missing or not identity mapping'
957	sys.exit()
958
959	if ( (boot_data_found == False) or (boot_data_identity == False) ):
960	print '[genmap error] in hard_config()'
961	print ' seg_boot_data missing or not identity mapping'
962	sys.exit()
963
964	if ( (boot_stack_found == False) or (boot_stack_identity == False) ):
965	print '[genmap error] in giet_vsegs()'
966	print ' seg_boot_stask missing or not identity mapping'
967	sys.exit()
968
969	# Search RAMDISK global vseg if required
970	seg_rdk_base = 0xFFFFFFFF
971	seg_rdk_size = 0
972	seg_rdk_found = False
973
974	if self.use_ramdisk:
975	for vseg in self.globs:
976	if ( vseg.name == 'seg_ramdisk' ):
977	seg_rdk_base = vseg.vbase
978	seg_rdk_size = vseg.length
979	seg_rdk_found = True
980
981	if ( seg_rdk_found == False ):
982	print 'Error in hard_config() "seg_ramdisk" not found'
983	sys.exit(1)
984
985	# build string
986	s = '/* Generated by genmap for %s */\n' % self.name
987	s += '\n'
988	s += '#ifndef HARD_CONFIG_H\n'
989	s += '#define HARD_CONFIG_H\n'
990	s += '\n'
991
992	s += '/* General platform parameters */\n'
993	s += '\n'
994	s += '#define X_SIZE %d\n' % self.x_size
995	s += '#define Y_SIZE %d\n' % self.y_size
996	s += '#define X_WIDTH %d\n' % self.x_width
997	s += '#define Y_WIDTH %d\n' % self.y_width
998	s += '#define P_WIDTH %d\n' % self.p_width
999	s += '#define X_IO %d\n' % self.x_io
1000	s += '#define Y_IO %d\n' % self.y_io
1001	s += '#define NB_PROCS_MAX %d\n' % self.nprocs
1002	s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc
1003	s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address
1004	s += '#define NB_TOTAL_PROCS %d\n' % nb_total_procs
1005	s += '\n'
1006
1007	s += '/* Peripherals */\n'
1008	s += '\n'
1009	s += '#define NB_TTY_CHANNELS %d\n' % tty_channels
1010	s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels
1011	s += '#define NB_NIC_CHANNELS %d\n' % nic_channels
1012	s += '#define NB_CMA_CHANNELS %d\n' % cma_channels
1013	s += '#define NB_TIM_CHANNELS %d\n' % tim_channels
1014	s += '#define NB_DMA_CHANNELS %d\n' % dma_channels
1015	s += '\n'
1016	s += '#define USE_XCU %d\n' % ( nb_xcu != 0 )
1017	s += '#define USE_IOB %d\n' % ( nb_iob != 0 )
1018	s += '#define USE_PIC %d\n' % ( nb_pic != 0 )
1019	s += '#define USE_FBF %d\n' % ( nb_fbf != 0 )
1020	s += '\n'
1021	s += '#define USE_IOC_BDV %d\n' % use_bdv
1022	s += '#define USE_IOC_SPI %d\n' % use_spi
1023	s += '#define USE_IOC_HBA %d\n' % use_hba
1024	s += '#define USE_IOC_RDK %d\n' % self.use_ramdisk
1025	s += '\n'
1026	s += '#define FBUF_X_SIZE %d\n' % fbf_arg0
1027	s += '#define FBUF_Y_SIZE %d\n' % fbf_arg1
1028	s += '\n'
1029	s += '#define XCU_NB_INPUTS %d\n' % xcu_arg0
1030	s += '\n'
1031	s += '#define MWR_TO_COPROC %d\n' % mwr_arg0
1032	s += '#define MWR_FROM_COPROC %d\n' % mwr_arg1
1033	s += '#define MWR_CONFIG %d\n' % mwr_arg2
1034	s += '#define MWR_STATUS %d\n' % mwr_arg3
1035	s += '\n'
1036
1037	s += '/* base addresses and sizes for physical segments */\n'
1038	s += '\n'
1039	s += '#define SEG_RAM_BASE 0x%x\n' % self.ram_base
1040	s += '#define SEG_RAM_SIZE 0x%x\n' % self.ram_size
1041	s += '\n'
1042	s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base
1043	s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size
1044	s += '\n'
1045	s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base
1046	s += '#define SEG_DMA_SIZE 0x%x\n' % seg_dma_size
1047	s += '\n'
1048	s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base
1049	s += '#define SEG_FBF_SIZE 0x%x\n' % seg_fbf_size
1050	s += '\n'
1051	s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base
1052	s += '#define SEG_IOB_SIZE 0x%x\n' % seg_iob_size
1053	s += '\n'
1054	s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base
1055	s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size
1056	s += '\n'
1057	s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base
1058	s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size
1059	s += '\n'
1060	s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base
1061	s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size
1062	s += '\n'
1063	s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base
1064	s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size
1065	s += '\n'
1066	s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base
1067	s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size
1068	s += '\n'
1069	s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base
1070	s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size
1071	s += '\n'
1072	s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base
1073	s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size
1074	s += '\n'
1075	s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base
1076	s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size
1077	s += '\n'
1078	s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base
1079	s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size
1080	s += '\n'
1081	s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base
1082	s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size
1083	s += '\n'
1084	s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base
1085	s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size
1086	s += '\n'
1087	s += '#define SEG_DROM_BASE 0x%x\n' % seg_drom_base
1088	s += '#define SEG_DROM_SIZE 0x%x\n' % seg_drom_size
1089	s += '\n'
1090	s += '#define PERI_CLUSTER_INCREMENT 0x%x\n' % self.peri_increment
1091	s += '\n'
1092
1093	s += '/* physical base addresses for identity mapped vsegs */\n'
1094	s += '/* used by the GietVM OS */\n'
1095	s += '\n'
1096	s += '#define SEG_BOOT_MAPPING_BASE 0x%x\n' % boot_mapping_base
1097	s += '#define SEG_BOOT_MAPPING_SIZE 0x%x\n' % boot_mapping_size
1098	s += '\n'
1099	s += '#define SEG_BOOT_CODE_BASE 0x%x\n' % boot_code_base
1100	s += '#define SEG_BOOT_CODE_SIZE 0x%x\n' % boot_code_size
1101	s += '\n'
1102	s += '#define SEG_BOOT_DATA_BASE 0x%x\n' % boot_data_base
1103	s += '#define SEG_BOOT_DATA_SIZE 0x%x\n' % boot_data_size
1104	s += '\n'
1105	s += '#define SEG_BOOT_STACK_BASE 0x%x\n' % boot_stack_base
1106	s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size
1107	s += '#endif\n'
1108
1109	return s
1110
1111	# end of hard_config()
1112
1113	################################################################################
1114	def linux_dts( self ): # compute string for linux.dts file generation
1115	# used for linux configuration
1116	# header
1117	s = '/dts-v1/;\n'
1118	s += '\n'
1119	s += '/{\n'
1120	s += ' compatible = "tsar,%s";\n' % self.name
1121	s += ' #address-cells = <2>;\n' # physical address on 64 bits
1122	s += ' #size-cells = <1>;\n' # segment size on 32 bits
1123	s += ' model = "%s";\n' % self.name
1124	s += '\n'
1125
1126	# linux globals arguments
1127	s += ' chosen {\n'
1128	s += ' linux,stdout-path = &tty;\n'
1129	s += ' bootargs = "console=tty0 console=ttyVTTY0 earlyprintk";\n'
1130	s += ' };\n\n'
1131
1132	# cpus (for each cluster)
1133	s += ' cpus {\n'
1134	s += ' #address-cells = <1>;\n'
1135	s += ' #size-cells = <0>;\n'
1136
1137	for cluster in self.clusters:
1138	for proc in cluster.procs:
1139	x = cluster.x
1140	y = cluster.y
1141	l = proc.lpid
1142	proc_id = (((x << self.y_width) + y) << self.p_width) + l
1143	s += ' cpu@%d_%d_%d {\n' %(x,y,l)
1144	s += ' device_type = "cpu";\n'
1145	s += ' compatible = "soclib,mips32el";\n'
1146	s += ' reg = <0x%x>;\n' % proc_id
1147	s += ' };\n'
1148	s += '\n'
1149
1150	s += ' };\n\n'
1151
1152	# devices (ram or peripheral) are grouped per cluster
1153	# the "compatible" attribute links a peripheral device
1154	# to one or several drivers identified by ("major","minor")
1155
1156	for cluster in self.clusters:
1157	x = cluster.x
1158	y = cluster.y
1159	found_xcu = False
1160	found_pic = False
1161
1162	s += ' /* cluster[%d,%d] */\n\n' % (x,y)
1163
1164	# scan all psegs to find RAM in current cluster
1165	for pseg in cluster.psegs:
1166	if ( pseg.segtype == 'RAM' ):
1167	msb = pseg.base >> 32
1168	lsb = pseg.base & 0xFFFFFFFF
1169	size = pseg.size
1170
1171	s += ' ram_%d_%d: ram@0x%x {\n' % (x, y, pseg.base)
1172	s += ' device_type = "memory";\n'
1173	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1174	s += ' };\n\n'
1175
1176	# scan all periphs to find XCU or PIC in current cluster
1177	for periph in cluster.periphs:
1178	msb = periph.pseg.base >> 32
1179	lsb = periph.pseg.base & 0xFFFFFFFF
1180	size = periph.pseg.size
1181
1182	# search XCU (can be replicated)
1183	if ( (periph.ptype == 'XCU') ):
1184	found_xcu = True
1185	xcu = periph
1186	irq_ctrl_name = 'xcu_%d_%d' % (x, y)
1187
1188	s += ' %s: xcu@0x%x {\n' % (irq_ctrl_name, periph.pseg.base)
1189	s += ' compatible = "soclib,vci_xicu","soclib,vci_xicu_timer";\n'
1190	s += ' interrupt-controller;\n'
1191	s += ' #interrupt-cells = <1>;\n'
1192	s += ' clocks = <&freq>;\n' # XCU contains a timer
1193	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1194	s += ' };\n\n'
1195
1196	# search PIC (non replicated)
1197	if ( periph.ptype == 'PIC' ):
1198	found_pic = True
1199	pic = periph
1200	irq_ctrl_name = 'pic'
1201
1202	s += ' %s: pic@0x%x {\n' % (irq_ctrl_name, periph.pseg.base)
1203	s += ' compatible = "soclib,vci_iopic";\n'
1204	s += ' interrupt-controller;\n'
1205	s += ' #interrupt-cells = <1>;\n'
1206	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1207	s += ' };\n\n'
1208
1209	# we need one interrupt controler in any cluster containing peripherals
1210	if ( (found_xcu == False) and
1211	(found_pic == False) and
1212	(len(cluster.periphs) > 0) ):
1213	print '[genmap error] in linux_dts()'
1214	print ' No XCU/PIC in cluster(%d,%d)' % (x,y)
1215	sys.exit(1)
1216
1217	if ( found_pic == True ): irq_ctrl = pic
1218	else: irq_ctrl = xcu
1219
1220	# scan all periphs to find TTY and IOC in current cluster
1221	for periph in cluster.periphs:
1222	msb = periph.pseg.base >> 32
1223	lsb = periph.pseg.base & 0xFFFFFFFF
1224	size = periph.pseg.size
1225
1226	# search TTY (non replicated)
1227	if ( periph.ptype == 'TTY' ):
1228
1229	# get HWI index to XCU or PIC (only TTY channel 0 is used by Linux)
1230	hwi_id = 0xFFFFFFFF
1231	for irq in irq_ctrl.irqs:
1232	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == 0) ):
1233	hwi_id = irq.srcid
1234
1235	if ( hwi_id == 0xFFFFFFFF ):
1236	print '[genmap error] in linux.dts()'
1237	print ' IRQ_TTY_RX not found'
1238	sys.exit(1)
1239
1240	s += ' tty: tty {\n'
1241	s += ' compatible = "soclib,vci_multi_tty";\n'
1242	s += ' interrupt-parent = <&%s>;\n' % (irq_ctrl_name)
1243	s += ' interrupts = <%d>;\n' % hwi_id
1244	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1245	s += ' };\n\n'
1246
1247	# search IOC (non replicated)
1248	elif ( periph.ptype == 'IOC' ):
1249
1250	if ( periph.subtype == 'BDV' ):
1251
1252	# get irq line index associated to bdv
1253	hwi_id = 0xFFFFFFFF
1254	for irq in irq_ctrl.irqs:
1255	if ( irq.isrtype == 'ISR_BDV' ): hwi_id = irq.srcid
1256
1257	if ( hwi_id == 0xFFFFFFFF ):
1258	print '[genmap error] in linux.dts()'
1259	print ' ISR_BDV not found'
1260	sys.exit(1)
1261
1262	s += ' bdv: bdv {\n'
1263	s += ' compatible = "tsar,vci_block_device";\n'
1264	s += ' interrupt-parent = <&%s>;\n' % (irq_ctrl_name)
1265	s += ' interrupts = <%d>;\n' % hwi_id
1266	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1267	s += ' };\n\n'
1268
1269	elif ( periph.subtype == 'HBA' ):
1270
1271	print '[genmap error] in linux_dts()'
1272	print ' HBA peripheral not supported by LINUX'
1273	sys.exit(1)
1274
1275	elif ( periph.subtype == 'SPI' ):
1276
1277	print '[genmap error] in linux_dts()'
1278	print ' SPI peripheral not supported by LINUX'
1279	sys.exit(1)
1280
1281	# XCU or PIC have been already parsed
1282	elif ( periph.ptype == 'XCU' ) or ( periph.ptype == 'PIC' ):
1283	pass
1284
1285	# other peripherals
1286	else:
1287	print '[genmap warning] in linux_dts()'
1288	print ' %s peripheral not supported by LINUX' % (periph.ptype)
1289
1290	# clocks
1291	s += ' /* clocks */\n\n'
1292	s += ' clocks {\n'
1293	s += ' freq: freq@50MHZ {\n'
1294	s += ' #clock-cells = <0>;\n'
1295	s += ' compatible = "fixed-clock";\n'
1296	s += ' clock-frequency = <50000000>;\n'
1297	s += ' };\n'
1298	s += ' };\n\n'
1299	s += ' cpuclk {\n'
1300	s += ' compatible = "soclib,mips32_clksrc";\n'
1301	s += ' clocks = <&freq>;\n'
1302	s += ' };\n'
1303	s += '};\n'
1304
1305	return s
1306	# end linux_dts()
1307
1308
1309	#############################################################################
1310	def netbsd_dts( self ): # compute string for netbsd.dts file generation,
1311	# used for netbsd configuration
1312	# header
1313	s = '/dts-v1/;\n'
1314	s += '\n'
1315	s += '/{\n'
1316	s += ' #address-cells = <2>;\n'
1317	s += ' #size-cells = <1>;\n'
1318
1319	# cpus (for each cluster)
1320	s += ' cpus {\n'
1321	s += ' #address-cells = <1>;\n'
1322	s += ' #size-cells = <0>;\n'
1323
1324	for cluster in self.clusters:
1325	for proc in cluster.procs:
1326	proc_id = (((cluster.x << self.y_width) + cluster.y) << self.p_width) + proc.lpid
1327
1328	s += ' Mips,32@0x%x {\n' % proc_id
1329	s += ' device_type = "cpu";\n'
1330	s += ' icudev_type = "cpu:mips";\n'
1331	s += ' name = "Mips,32";\n'
1332	s += ' reg = <0x%x>;\n' % proc_id
1333	s += ' };\n'
1334	s += '\n'
1335
1336	s += ' };\n'
1337
1338	# physical memory banks (for each cluster)
1339	for cluster in self.clusters:
1340	for pseg in cluster.psegs:
1341
1342	if ( pseg.segtype == 'RAM' ):
1343	msb = pseg.base >> 32
1344	lsb = pseg.base & 0xFFFFFFFF
1345	size = pseg.size
1346
1347	s += ' %s@0x%x {\n' % (pseg.name, pseg.base)
1348	s += ' cached = <1>;\n'
1349	s += ' device_type = "memory";\n'
1350	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1351	s += ' };\n'
1352
1353	# peripherals (for each cluster)
1354	for cluster in self.clusters:
1355	x = cluster.x
1356	y = cluster.y
1357
1358	# research XCU component
1359	found_xcu = False
1360	for periph in cluster.periphs:
1361	if ( (periph.ptype == 'XCU') ):
1362	found_xcu = True
1363	xcu = periph
1364	msb = periph.pseg.base >> 32
1365	lsb = periph.pseg.base & 0xFFFFFFFF
1366	size = periph.pseg.size
1367
1368	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1369	s += ' device_type = "soclib:xicu:root";\n'
1370	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1371	s += ' input_lines = <%d>;\n' % periph.arg
1372	s += ' ipis = <%d>;\n' % periph.arg
1373	s += ' timers = <%d>;\n' % periph.arg
1374
1375	output_id = 0 # output index from XCU
1376	for lpid in xrange ( len(cluster.procs) ): # destination processor index
1377	for itid in xrange ( self.irq_per_proc ): # input irq index on processor
1378	cluster_xy = (cluster.x << self.y_width) + cluster.y
1379	proc_id = (cluster_xy << self.p_width) + lpid
1380	s += ' out@%d {\n' % output_id
1381	s += ' device_type = "soclib:xicu:filter";\n'
1382	s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid)
1383	s += ' output_line = <%d>;\n' % output_id
1384	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1385	s += ' };\n'
1386
1387	output_id += 1
1388
1389	s += ' };\n'
1390
1391	# research PIC component
1392	found_pic = False
1393	for periph in cluster.periphs:
1394	if ( periph.ptype == 'PIC' ):
1395	found_pic = True
1396	pic = periph
1397	msb = periph.pseg.base >> 32
1398	lsb = periph.pseg.base & 0xFFFFFFFF
1399	size = periph.pseg.size
1400
1401	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1402	s += ' device_type = "soclib:pic:root";\n'
1403	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1404	s += ' input_lines = <%d>;\n' % periph.channels
1405	s += ' };\n'
1406
1407	# at least one interrupt controller
1408	if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ):
1409	print '[genmap error] in netbsd_dts()'
1410	print ' No XCU/PIC in cluster(%d,%d)' % (x,y)
1411	sys.exit(1)
1412
1413	if ( found_pic == True ): irq_tgt = pic
1414	else: irq_tgt = xcu
1415
1416	# get all others peripherals in cluster
1417	for periph in cluster.periphs:
1418	msb = periph.pseg.base >> 32
1419	lsb = periph.pseg.base & 0xFFFFFFFF
1420	size = periph.pseg.size
1421
1422	# research DMA component
1423	if ( periph.ptype == 'DMA' ):
1424
1425	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1426	s += ' device_type = "soclib:dma";\n'
1427	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1428	s += ' channel_count = <%d>;\n' % periph.channels
1429
1430	# multi-channels : get HWI index (to XCU) for each channel
1431	for channel in xrange( periph.channels ):
1432	hwi_id = 0xFFFFFFFF
1433	for irq in xcu.irqs:
1434	if ( (irq.isrtype == 'ISR_DMA') and (irq.channel == channel) ):
1435	hwi_id = irq.srcid
1436
1437	if ( hwi_id == 0xFFFFFFFF ):
1438	print '[genmap error] in netbsd.dts()'
1439	print ' ISR_DMA channel %d not found' % channel
1440	sys.exit(1)
1441
1442	name = '%s@0x%x' % (xcu.pseg.name, xcu.pseg.base)
1443	s += ' irq@%d{\n' % channel
1444	s += ' device_type = "soclib:periph:irq";\n'
1445	s += ' output_line = <%d>;\n' % channel
1446	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1447	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1448	s += ' };\n'
1449
1450	s += ' };\n'
1451
1452	# research MMC component
1453	elif ( periph.ptype == 'MMC' ):
1454
1455	# get irq line index associated to MMC in XCU
1456	irq_in = 0xFFFFFFFF
1457	for irq in xcu.irqs:
1458	if ( irq.isrtype == 'ISR_MMC' ): irq_in = irq.srcid
1459
1460	if ( irq_in == 0xFFFFFFFF ):
1461	print '[genmap error] in netbsd.dts()'
1462	print ' ISR_MMC not found'
1463	sys.exit(1)
1464
1465	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1466	s += ' device_type = "soclib:mmc";\n'
1467	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
1468	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1469	s += ' };\n'
1470
1471	# research FBF component
1472	elif ( periph.ptype == 'FBF' ):
1473
1474	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1475	s += ' device_type = "soclib:framebuffer";\n'
1476	s += ' mode = <32>;\n' # bits par pixel
1477	s += ' width = <%d>;\n' % periph.arg
1478	s += ' height = <%d>;\n' % periph.arg
1479	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1480	s += ' };\n'
1481
1482	# research IOC component
1483	elif ( periph.ptype == 'IOC' ):
1484
1485	if ( periph.subtype == 'BDV' ):
1486
1487	# get irq line index associated to bdv
1488	irq_in = 0xFFFFFFFF
1489	for irq in irq_tgt.irqs:
1490	if ( irq.isrtype == 'ISR_BDV' ): irq_in = irq.srcid
1491	if ( irq_in == 0xFFFFFFFF ):
1492	print '[genmap error] in netbsd.dts()'
1493	print ' ISR_BDV not found'
1494	sys.exit(1)
1495
1496	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1497	s += ' device_type = "soclib:blockdevice";\n'
1498	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name,irq_tgt.pseg.base,irq_in)
1499	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1500	s += ' };\n'
1501
1502	elif ( periph.subtype == 'HBA' ):
1503	print '[genmap error] in netbsd_dts()'
1504	print ' HBA peripheral not supported by NetBSD'
1505	sys.exit(1)
1506
1507	elif ( periph.subtype == 'SPI' ):
1508
1509	# get irq line index associated to spi
1510	irq_in = 0xFFFFFFFF
1511	for irq in irq_tgt.irqs:
1512	if ( irq.isrtype == 'ISR_SPI' ): irq_in = irq.srcid
1513	if ( irq_in == 0xFFFFFFFF ):
1514	print '[genmap error] in netbsd.dts()'
1515	print ' ISR_SPI not found'
1516	sys.exit(1)
1517
1518	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1519	s += ' device_type = "soclib:spi";\n'
1520	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name,irq_tgt.pseg.base,irq_in)
1521	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1522	s += ' };\n'
1523
1524	# research ROM component
1525	elif ( periph.ptype == 'ROM' ):
1526
1527	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1528	s += ' device_type = "rom";\n'
1529	s += ' cached = <1>;\n'
1530	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1531	s += ' };\n'
1532
1533	# research SIM component
1534	elif ( periph.ptype == 'SIM' ):
1535
1536	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1537	s += ' device_type = "soclib:simhelper";\n'
1538	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1539	s += ' };\n'
1540
1541	# research TTY component
1542	elif ( periph.ptype == 'TTY' ):
1543
1544	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1545	s += ' device_type = "soclib:tty";\n'
1546	s += ' channel_count = < %d >;\n' % periph.channels
1547	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1548
1549	# multi-channels : get HWI index (to XCU or PIC) for each channel
1550	for channel in xrange( periph.channels ):
1551	hwi_id = 0xFFFFFFFF
1552	for irq in irq_tgt.irqs:
1553	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ):
1554	hwi_id = irq.srcid
1555	if ( hwi_id == 0xFFFFFFFF ):
1556	print '[genmap error] in netbsd.dts()'
1557	print ' ISR_TTY_RX channel %d not found' % channel
1558	sys.exit(1)
1559
1560	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1561	s += ' irq@%d{\n' % channel
1562	s += ' device_type = "soclib:periph:irq";\n'
1563	s += ' output_line = <%d>;\n' % channel
1564	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1565	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1566	s += ' };\n'
1567
1568	s += ' };\n'
1569
1570	# research IOB component
1571	elif ( periph.ptype == 'IOB' ):
1572
1573	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1574	s += ' device_type = "soclib:iob";\n'
1575	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1576	s += ' };\n'
1577
1578	# research NIC component
1579	elif ( periph.ptype == 'NIC' ):
1580
1581	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1582	s += ' device_type = "soclib:nic";\n'
1583	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1584	s += ' channel_count = < %d >;\n' % periph.channels
1585
1586	# multi-channels : get HWI index (to XCU or PIC) for RX & TX IRQs
1587	# RX IRQ : (2channel) / TX IRQs : (2channel + 1)
1588	for channel in xrange( periph.channels ):
1589	hwi_id = 0xFFFFFFFF
1590	for irq in irq_tgt.irqs:
1591	if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ):
1592	hwi_id = irq.srcid
1593	if ( hwi_id == 0xFFFFFFFF ):
1594	print '[genmap error] in netbsd.dts()'
1595	print ' ISR_NIC_RX channel %d not found' % channel
1596	sys.exit(1)
1597
1598	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1599	s += ' irq_rx@%d{\n' % channel
1600	s += ' device_type = "soclib:periph:irq";\n'
1601	s += ' output_line = <%d>;\n' % (2*channel)
1602	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1603	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1604	s += ' };\n'
1605
1606	hwi_id = 0xFFFFFFFF
1607	for irq in irq_tgt.irqs:
1608	if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ):
1609	hwi_id = irq.srcid
1610	if ( hwi_id == 0xFFFFFFFF ):
1611	print '[genmap error] in netbsd.dts()'
1612	print ' ISR_NIC_TX channel %d not found' % channel
1613	sys.exit(1)
1614
1615	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1616	s += ' irq_tx@%d{\n' % channel
1617	s += ' device_type = "soclib:periph:irq";\n'
1618	s += ' output_line = <%d>;\n' % (2*channel + 1)
1619	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1620	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1621	s += ' };\n'
1622
1623	s += ' };\n'
1624
1625	# research CMA component
1626	elif ( periph.ptype == 'CMA' ):
1627
1628	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1629	s += ' device_type = "soclib:cma";\n'
1630	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1631	s += ' channel_count = < %d >;\n' % periph.channels
1632
1633	# multi-channels : get HWI index (to XCU or PIC) for each channel
1634	for channel in xrange( periph.channels ):
1635	hwi_id = 0xFFFFFFFF
1636	for irq in irq_tgt.irqs:
1637	if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ):
1638	hwi_id = irq.srcid
1639
1640	if ( hwi_id == 0xFFFFFFFF ):
1641	print '[genmap error] in netbsd.dts()'
1642	print ' ISR_CMA channel %d not found' % channel
1643	sys.exit(1)
1644
1645	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1646	s += ' irq@%d{\n' % channel
1647	s += ' device_type = "soclib:periph:irq";\n'
1648	s += ' output_line = <%d>;\n' % channel
1649	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1650	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1651	s += ' };\n'
1652
1653	s += ' };\n'
1654
1655	# research TIM component
1656	elif ( periph.ptype == 'TIM' ):
1657
1658	print '[genmap error] in netbsd_dts()'
1659	print ' TIM peripheral not supported by NetBSD'
1660	sys.exit(1)
1661
1662	# research MWR component
1663	elif ( periph.ptype == 'MWR' ):
1664
1665	print '[genmap error] in netbsd_dts()'
1666	print ' MWR peripheral not supported by NetBSD'
1667	sys.exit(1)
1668
1669	# topology
1670	s += '\n'
1671	s += ' topology {\n'
1672	s += ' #address-cells = <2>;\n'
1673	s += ' #size-cells = <0>;\n'
1674	for cluster in self.clusters:
1675	s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y)
1676	s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y)
1677	s += ' devices = <\n'
1678
1679	offset = ((cluster.x << self.y_width) + cluster.y) << self.p_width
1680	for proc in cluster.procs:
1681	s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid)
1682	for periph in cluster.periphs:
1683	s += ' &{/%s@0x%x}\n' % (periph.pseg.name, periph.pseg.base)
1684	for pseg in cluster.psegs:
1685	if ( pseg.segtype == 'RAM' ):
1686	s += ' &{/%s@0x%x}\n' % (pseg.name, pseg.base)
1687
1688	s += ' >;\n'
1689	s += ' };\n'
1690	s += ' };\n'
1691	s += '};\n'
1692
1693	return s
1694	# end netbsd_dts()
1695
1696	###########################
1697	def almos_archinfo( self ): # compute string for arch.info file generation,
1698	# used for almos configuration
1699	# header
1700	s = '# arch.info file generated by genmap for %s\n' % self.name
1701	s += '\n'
1702	s += '[HEADER]\n'
1703	s += ' REVISION=1\n'
1704	s += ' ARCH=%s\n' % self.name
1705	s += ' XMAX=%d\n' % self.x_size
1706	s += ' YMAX=%d\n' % self.y_size
1707	s += ' CPU_NR=%d\n' % self.nprocs
1708	s += '\n'
1709
1710	# clusters
1711	cluster_id = 0
1712	for cluster in self.clusters:
1713
1714	ram = None
1715	nb_cpus = len( cluster.procs )
1716	nb_devs = len( cluster.periphs )
1717
1718	# search a RAM
1719	for pseg in cluster.psegs:
1720	if ( pseg.segtype == 'RAM' ):
1721	ram = pseg
1722	nb_devs += 1
1723
1724	# search XCU to get IRQs indexes if cluster contains peripherals
1725	if ( len( cluster.periphs ) != 0 ):
1726	tty_irq_id = None
1727	bdv_irq_id = None
1728	dma_irq_id = None
1729
1730	for periph in cluster.periphs:
1731	if ( periph.ptype == 'XCU' ):
1732	# scan irqs
1733	for irq in periph.irqs:
1734	if ( irq.isrtype == 'ISR_TTY_RX' ) : tty_irq_id = irq.srcid
1735	if ( irq.isrtype == 'ISR_BDV' ) : bdv_irq_id = irq.srcid
1736	if ( irq.isrtype == 'ISR_DMA' ) : dma_irq_id = irq.srcid
1737
1738	# Build the cluster description
1739	s += '[CLUSTER]\n'
1740	s += ' CID=%d\n' % cluster_id
1741	s += ' ARCH_CID=0x%x\n' % ((cluster.x << self.y_width) + cluster.y)
1742	s += ' CPU_NR=%d\n' % nb_cpus
1743	s += ' DEV_NR=%d\n' % nb_devs
1744
1745
1746	# Handling RAM when cluster contain a RAM
1747	if (ram != None ):
1748	base = ram.base
1749	size = ram.size
1750	irqid = -1
1751	s += ' DEVID=RAM'
1752	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1753
1754	# Handling peripherals
1755	for periph in cluster.periphs:
1756	base = periph.pseg.base
1757	size = periph.pseg.size
1758
1759	if ( periph.ptype == 'XCU' ):
1760
1761	s += ' DEVID=XICU'
1762	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1763
1764	elif ( (periph.ptype == 'TTY')
1765	and (tty_irq_id != None) ):
1766
1767	s += ' DEVID=TTY'
1768	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, tty_irq_id )
1769
1770	elif ( (periph.ptype == 'DMA')
1771	and (dma_irq_id != None) ):
1772
1773	s += ' DEVID=DMA'
1774	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, dma_irq_id )
1775
1776	elif ( periph.ptype == 'FBF' ):
1777
1778	s += ' DEVID=FB'
1779	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1780
1781	elif ( (periph.ptype == 'IOC') and (periph.subtype == 'BDV')
1782	and (bdv_irq_id != None) ):
1783
1784	s += ' DEVID=BLKDEV'
1785	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, bdv_irq_id )
1786
1787	elif ( periph.ptype == 'PIC' ):
1788
1789	s += ' DEVID=IOPIC'
1790	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1791
1792	else:
1793	print '# Warning from almos_archinfo() in cluster[%d,%d]' \
1794	% (cluster.x, cluster.y)
1795	print '# peripheral type %s/%s not supported yet\n' \
1796	% ( periph.ptype, periph.subtype )
1797
1798	cluster_id += 1
1799
1800	return s
1801
1802	# end of almos_archinfo()
1803
1804
1805
1806
1807
1808
1809
1810
1811	###########################################################################################
1812	class Cluster ( object ):
1813	###########################################################################################
1814	def __init__( self,
1815	x,
1816	y ):
1817
1818	self.index = 0 # global index (set by Mapping constructor)
1819	self.x = x # x coordinate
1820	self.y = y # y coordinate
1821	self.psegs = [] # filled by addRam() or addPeriph()
1822	self.procs = [] # filled by addProc()
1823	self.periphs = [] # filled by addPeriph()
1824
1825	return
1826
1827	################
1828	def xml( self ): # xml for a cluster
1829
1830	s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y)
1831	for pseg in self.psegs: s += pseg.xml()
1832	for proc in self.procs: s += proc.xml()
1833	for peri in self.periphs: s += peri.xml()
1834	s += ' </cluster>\n'
1835
1836	return s
1837
1838	#############################################
1839	def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster
1840
1841	if ( verbose ):
1842	print '*** cbin for cluster [%d,%d]' % (self.x, self.y)
1843
1844	# check index
1845	if (self.index != expected):
1846	print '[genmap error] in Cluster.cbin()'
1847	print ' cluster global index = %d / expected = %d' % (self.index,expected)
1848	sys.exit(1)
1849
1850	# compute global index for first pseg
1851	if ( len(self.psegs) > 0 ):
1852	pseg_id = self.psegs[0].index
1853	else:
1854	pseg_id = 0
1855
1856	# compute global index for first proc
1857	if ( len(self.procs) > 0 ):
1858	proc_id = self.procs[0].index
1859	else:
1860	proc_id = 0
1861
1862	# compute global index for first periph
1863	if ( len(self.periphs) > 0 ):
1864	periph_id = self.periphs[0].index
1865	else:
1866	periph_id = 0
1867
1868	byte_stream = bytearray()
1869	byte_stream += mapping.int2bytes( 4 , self.x ) # x coordinate
1870	byte_stream += mapping.int2bytes( 4 , self.y ) # x coordinate
1871	byte_stream += mapping.int2bytes( 4 , len( self.psegs ) ) # number psegs in cluster
1872	byte_stream += mapping.int2bytes( 4 , pseg_id ) # first pseg global index
1873	byte_stream += mapping.int2bytes( 4 , len( self.procs ) ) # number procs in cluster
1874	byte_stream += mapping.int2bytes( 4 , proc_id ) # first proc global index
1875	byte_stream += mapping.int2bytes( 4 , len( self.periphs ) ) # number periphs in cluster
1876	byte_stream += mapping.int2bytes( 4 , periph_id ) # first periph global index
1877
1878	if ( verbose ):
1879	print 'nb_psegs = %d' % len( self.psegs )
1880	print 'pseg_id = %d' % pseg_id
1881	print 'nb_procs = %d' % len( self.procs )
1882	print 'proc_id = %d' % proc_id
1883	print 'nb_periphs = %d' % len( self.periphs )
1884	print 'periph_id = %d' % periph_id
1885
1886	return byte_stream
1887
1888	########################################################################################
1889	class Vspace( object ):
1890	########################################################################################
1891	def __init__( self,
1892	name,
1893	startname ):
1894
1895	self.index = 0 # global index ( set by addVspace() )
1896	self.name = name # vspace name
1897	self.startname = startname # name of vseg containing the start_vector
1898	self.vsegs = []
1899	self.tasks = []
1900
1901	return
1902
1903	################
1904	def xml( self ): # xml for one vspace
1905
1906	s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname )
1907	for vseg in self.vsegs: s += vseg.xml()
1908	for task in self.tasks: s += task.xml()
1909	s += ' </vspace>\n'
1910
1911	return s
1912
1913	#############################################
1914	def cbin( self, mapping, verbose, expected ): # C binary structure for Vspace
1915
1916	if ( verbose ):
1917	print '*** cbin for vspace %s' % (self.name)
1918
1919	# check index
1920	if (self.index != expected):
1921	print '[genmap error] in Vspace.cbin()'
1922	print ' vspace global index = %d / expected = %d' %(self.index,expected)
1923	sys.exit(1)
1924
1925	# compute global index for vseg containing start_vector
1926	vseg_start_id = 0xFFFFFFFF
1927	for vseg in self.vsegs:
1928	if ( vseg.name == self.startname ): vseg_start_id = vseg.index
1929
1930	if ( vseg_start_id == 0xFFFFFFFF ):
1931	print '[genmap error] in Vspace.cbin()'
1932	print ' startname %s not found for vspace %s' %(self.startname,self.name)
1933	sys.exit(1)
1934
1935	# compute first vseg and first task global index
1936	first_vseg_id = self.vsegs[0].index
1937	first_task_id = self.tasks[0].index
1938
1939	# compute number of tasks and number of vsegs
1940	nb_vsegs = len( self.vsegs )
1941	nb_tasks = len( self.tasks )
1942
1943	byte_stream = bytearray()
1944	byte_stream += mapping.str2bytes( 32, self.name ) # vspace name
1945	byte_stream += mapping.int2bytes( 4, vseg_start_id ) # vseg start_vector
1946	byte_stream += mapping.int2bytes( 4, nb_vsegs ) # number of vsegs
1947	byte_stream += mapping.int2bytes( 4, nb_tasks ) # number of tasks
1948	byte_stream += mapping.int2bytes( 4, first_vseg_id ) # first vseg global index
1949	byte_stream += mapping.int2bytes( 4, first_task_id ) # first task global index
1950
1951	if ( verbose ):
1952	print 'start_id = %d' % vseg_start_id
1953	print 'nb_vsegs = %d' % nb_vsegs
1954	print 'nb_tasks = %d' % nb_tasks
1955	print 'vseg_id = %d' % first_vseg_id
1956	print 'task_id = %d' % first_task_id
1957
1958	return byte_stream
1959
1960	########################################################################################
1961	class Task( object ):
1962	########################################################################################
1963	def __init__( self,
1964	name,
1965	trdid,
1966	x,
1967	y,
1968	p,
1969	stackname,
1970	heapname,
1971	startid ):
1972
1973	self.index = 0 # global index value set by addTask()
1974	self.name = name # tsk name
1975	self.trdid = trdid # task index (unique in vspace)
1976	self.x = x # cluster x coordinate
1977	self.y = y # cluster y coordinate
1978	self.p = p # processor local index
1979	self.stackname = stackname # name of vseg containing the stack
1980	self.heapname = heapname # name of vseg containing the heap
1981	self.startid = startid # index in start_vector
1982	return
1983
1984	################
1985	def xml( self ): # xml for one task
1986
1987	s = ' <task name="%s"' % self.name
1988	s += ' trdid="%d"' % self.trdid
1989	s += ' x="%d"' % self.x
1990	s += ' y="%d"' % self.y
1991	s += ' p="%d"' % self.p
1992	s += '\n '
1993	s += ' stackname="%s"' % self.stackname
1994	s += ' heapname="%s"' % self.heapname
1995	s += ' startid="%d"' % self.startid
1996	s += ' />\n'
1997
1998	return s
1999
2000	#####################################################
2001	def cbin( self, mapping, verbose, expected, vspace ): # C binary data structure for Task
2002
2003	if ( verbose ):
2004	print '*** cbin for task %s in vspace %s' % (self.name, vspace.name)
2005
2006	# check index
2007	if (self.index != expected):
2008	print '[genmap error] in Task.cbin()'
2009	print ' task global index = %d / expected = %d' %(self.index,expected)
2010	sys.exit(1)
2011
2012	# compute cluster global index
2013	cluster_id = (self.x * mapping.y_size) + self.y
2014
2015	# compute vseg index for stack
2016	vseg_stack_id = 0xFFFFFFFF
2017	for vseg in vspace.vsegs:
2018	if ( vseg.name == self.stackname ): vseg_stack_id = vseg.index
2019
2020	if ( vseg_stack_id == 0xFFFFFFFF ):
2021	print '[genmap error] in Task.cbin()'
2022	print ' stackname %s not found for task %s in vspace %s' \
2023	% ( self.stackname, self.name, vspace.name )
2024	sys.exit(1)
2025
2026	# compute vseg index for heap
2027	if ( self.heapname == '' ):
2028	vseg_heap_id = 0
2029	else:
2030	vseg_heap_id = 0xFFFFFFFF
2031	for vseg in vspace.vsegs:
2032	if ( vseg.name == self.heapname ): vseg_heap_id = vseg.index
2033
2034	if ( vseg_heap_id == 0xFFFFFFFF ):
2035	print '[genmap error] in Task.cbin()'
2036	print ' heapname %s not found for task %s in vspace %s' \
2037	% ( self.heapname, self.name, vspace.name )
2038	sys.exit(1)
2039
2040	byte_stream = bytearray()
2041	byte_stream += mapping.str2bytes( 32, self.name ) # task name in vspace
2042	byte_stream += mapping.int2bytes( 4, cluster_id ) # cluster global index
2043	byte_stream += mapping.int2bytes( 4, self.p ) # processor local index
2044	byte_stream += mapping.int2bytes( 4, self.trdid ) # thread local index in vspace
2045	byte_stream += mapping.int2bytes( 4, vseg_stack_id ) # stack vseg local index
2046	byte_stream += mapping.int2bytes( 4, vseg_heap_id ) # heap vseg local index
2047	byte_stream += mapping.int2bytes( 4, self.startid ) # index in start vector
2048
2049	if ( verbose ):
2050	print 'clusterid = %d' % cluster_id
2051	print 'lpid = %d' % self.p
2052	print 'trdid = %d' % self.trdid
2053	print 'stackid = %d' % vseg_stack_id
2054	print 'heapid = %d' % vseg_heap_id
2055	print 'startid = %d' % self.startid
2056
2057	return byte_stream
2058
2059	########################################################################################
2060	class Vseg( object ):
2061	########################################################################################
2062	def __init__( self,
2063	name,
2064	vbase,
2065	length,
2066	mode,
2067	vtype,
2068	x,
2069	y,
2070	pseg,
2071	identity = False,
2072	local = False,
2073	big = False,
2074	binpath = '' ):
2075
2076	assert (vbase & 0xFFFFFFFF) == vbase
2077
2078	assert (length & 0xFFFFFFFF) == length
2079
2080	assert mode in VSEGMODES
2081
2082	assert vtype in VSEGTYPES
2083
2084	assert (vtype != 'ELF') or (binpath != '')
2085
2086	self.index = 0 # global index ( set by addVseg() )
2087	self.name = name # vseg name (unique in vspace)
2088	self.vbase = vbase # virtual base address in vspace
2089	self.length = length # vseg length (bytes)
2090	self.vtype = vtype # vseg type (defined in VSEGTYPES)
2091	self.mode = mode # CXWU access rights
2092	self.x = x # x coordinate of destination cluster
2093	self.y = y # y coordinate of destination cluster
2094	self.psegname = pseg # name of pseg in destination cluster
2095	self.identity = identity # identity mapping required
2096	self.local = local # only mapped in local PTAB when true
2097	self.big = big # to be mapped in a big physical page
2098	self.binpath = binpath # path name for binary file (ELF or BLOB)
2099
2100	return
2101
2102	################
2103	def xml( self ): # xml for one vseg
2104
2105	s = ' <vseg name="%s"' %(self.name)
2106	s += ' vbase="0x%x"' %(self.vbase)
2107	s += ' length="0x%x"' %(self.length)
2108	s += ' type="%s"' %(self.vtype)
2109	s += ' mode="%s"' %(self.mode)
2110	s += '\n '
2111	s += ' x="%d"' %(self.x)
2112	s += ' y="%d"' %(self.y)
2113	s += ' psegname="%s"' %(self.psegname)
2114	if ( self.identity ): s += ' ident="1"'
2115	if ( self.local ): s += ' local="1"'
2116	if ( self.big ): s += ' big="1"'
2117	if ( self.binpath != '' ): s += ' binpath="%s"' %(self.binpath)
2118	s += ' />\n'
2119
2120	return s
2121
2122	#############################################
2123	def cbin( self, mapping, verbose, expected ): # C binary structure for Vseg
2124
2125	if ( verbose ):
2126	print '*** cbin for vseg[%d] %s' % (self.index, self.name)
2127
2128	# check index
2129	if (self.index != expected):
2130	print '[genmap error] in Vseg.cbin()'
2131	print ' vseg global index = %d / expected = %d' \
2132	% (self.index, expected )
2133	sys.exit(1)
2134
2135	# compute pseg_id
2136	pseg_id = 0xFFFFFFFF
2137	cluster_id = (self.x * mapping.y_size) + self.y
2138	cluster = mapping.clusters[cluster_id]
2139	for pseg in cluster.psegs:
2140	if (self.psegname == pseg.name):
2141	pseg_id = pseg.index
2142	if (pseg_id == 0xFFFFFFFF):
2143	print '[genmap error] in Vseg.cbin() : '
2144	print ' psegname %s not found for vseg %s in cluster %d' \
2145	% ( self.psegname, self.name, cluster_id )
2146	sys.exit(1)
2147
2148	# compute numerical value for mode
2149	mode_id = 0xFFFFFFFF
2150	for x in xrange( len(VSEGMODES) ):
2151	if ( self.mode == VSEGMODES[x] ):
2152	mode_id = x
2153	if ( mode_id == 0xFFFFFFFF ):
2154	print '[genmap error] in Vseg.cbin() : '
2155	print ' undefined vseg mode %s' % self.mode
2156	sys.exit(1)
2157
2158	# compute numerical value for vtype
2159	vtype_id = 0xFFFFFFFF
2160	for x in xrange( len(VSEGTYPES) ):
2161	if ( self.vtype == VSEGTYPES[x] ):
2162	vtype_id = x
2163	if ( vtype_id == 0xFFFFFFFF ):
2164	print '[genmap error] in Vseg.cbin()'
2165	print ' undefined vseg type %s' % self.vtype
2166	sys.exit(1)
2167
2168	byte_stream = bytearray()
2169	byte_stream += mapping.str2bytes( 32, self.name ) # vseg name
2170	byte_stream += mapping.str2bytes( 64, self.binpath ) # binpath
2171	byte_stream += mapping.int2bytes( 4, self.vbase ) # virtual base address
2172	byte_stream += mapping.int2bytes( 8, 0 ) # physical base address
2173	byte_stream += mapping.int2bytes( 4, self.length ) # vseg size (bytes)
2174	byte_stream += mapping.int2bytes( 4, pseg_id ) # pseg global index
2175	byte_stream += mapping.int2bytes( 4, mode_id ) # CXWU flags
2176	byte_stream += mapping.int2bytes( 4, vtype_id ) # vseg type
2177	byte_stream += mapping.int2bytes( 1, 0 ) # mapped when non zero
2178	byte_stream += mapping.int2bytes( 1, self.identity ) # identity mapping
2179	byte_stream += mapping.int2bytes( 1, self.local ) # only mapped in local PTAB
2180	byte_stream += mapping.int2bytes( 1, self.big ) # to be mapped in BPP
2181
2182	if ( verbose ):
2183	print 'binpath = %s' % self.binpath
2184	print 'vbase = %x' % self.vbase
2185	print 'pbase = 0'
2186	print 'length = %x' % self.length
2187	print 'pseg_id = %d' % pseg_id
2188	print 'mode = %d' % mode_id
2189	print 'type = %d' % vtype_id
2190	print 'mapped = 0'
2191	print 'ident = %d' % self.identity
2192	print 'local = %d' % self.local
2193	print 'big = %d' % self.big
2194
2195	return byte_stream
2196
2197	######################################################################################
2198	class Processor ( object ):
2199	######################################################################################
2200	def __init__( self,
2201	x,
2202	y,
2203	lpid ):
2204
2205	self.index = 0 # global index ( set by addProc() )
2206	self.x = x # x cluster coordinate
2207	self.y = y # y cluster coordinate
2208	self.lpid = lpid # processor local index
2209
2210	return
2211
2212	################
2213	def xml( self ): # xml for a processor
2214	return ' <proc index="%d" />\n' % (self.lpid)
2215
2216	#############################################
2217	def cbin( self, mapping, verbose, expected ): # C binary structure for Proc
2218
2219	if ( verbose ):
2220	print '*** cbin for proc %d in cluster (%d,%d)' % (self.lpid, self.x, self.y)
2221
2222	# check index
2223	if (self.index != expected):
2224	print '[genmap error] in Proc.cbin()'
2225	print ' proc global index = %d / expected = %d' % (self.index,expected)
2226	sys.exit(1)
2227
2228	byte_stream = bytearray()
2229	byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index
2230
2231	return byte_stream
2232
2233	######################################################################################
2234	class Pseg ( object ):
2235	######################################################################################
2236	def __init__( self,
2237	name,
2238	base,
2239	size,
2240	x,
2241	y,
2242	segtype ):
2243
2244	assert( segtype in PSEGTYPES )
2245
2246	self.index = 0 # global index ( set by addPseg() )
2247	self.name = name # pseg name (unique in cluster)
2248	self.base = base # physical base address
2249	self.size = size # segment size (bytes)
2250	self.x = x # cluster x coordinate
2251	self.y = y # cluster y coordinate
2252	self.segtype = segtype # RAM / PERI (defined in mapping_info.h)
2253
2254	return
2255
2256	################
2257	def xml( self ): # xml for a pseg
2258
2259	return ' <pseg name="%s" type="%s" base="0x%x" length="0x%x" />\n' \
2260	% (self.name, self.segtype, self.base, self.size)
2261
2262	######################################################
2263	def cbin( self, mapping, verbose, expected, cluster ): # C binary structure for Pseg
2264
2265	if ( verbose ):
2266	print '*** cbin for pseg[%d] %s in cluster[%d,%d]' \
2267	% (self.index, self.name, cluster.x, cluster.y)
2268
2269	# check index
2270	if (self.index != expected):
2271	print '[genmap error] in Pseg.cbin()'
2272	print ' pseg global index = %d / expected = %d' % (self.index,expected)
2273	sys.exit(1)
2274
2275	# compute numerical value for segtype
2276	segtype_int = 0xFFFFFFFF
2277	for x in xrange( len(PSEGTYPES) ):
2278	if ( self.segtype == PSEGTYPES[x] ): segtype_int = x
2279
2280	if ( segtype_int == 0xFFFFFFFF ):
2281	print '[genmap error] in Pseg.cbin()'
2282	print ' undefined segment type %s' % self.segtype
2283	sys.exit(1)
2284
2285	byte_stream = bytearray()
2286	byte_stream += mapping.str2bytes( 32, self.name ) # pseg name
2287	byte_stream += mapping.int2bytes( 8 , self.base ) # physical base address
2288	byte_stream += mapping.int2bytes( 8 , self.size ) # segment length
2289	byte_stream += mapping.int2bytes( 4 , segtype_int ) # segment type
2290	byte_stream += mapping.int2bytes( 4 , cluster.index ) # cluster global index
2291	byte_stream += mapping.int2bytes( 4 , 0 ) # linked list of vsegs
2292
2293	if ( verbose ):
2294	print 'pbase = %x' % self.base
2295	print 'size = %x' % self.size
2296	print 'type = %s' % self.segtype
2297
2298	return byte_stream
2299
2300	######################################################################################
2301	class Periph ( object ):
2302	######################################################################################
2303	def __init__( self,
2304	pseg, # associated pseg
2305	ptype, # peripheral type
2306	subtype = 'NONE', # peripheral subtype
2307	channels = 1, # for multi-channels peripherals
2308	arg0 = 0, # optional argument (semantic depends on ptype)
2309	arg1 = 0, # optional argument (semantic depends on ptype)
2310	arg2 = 0, # optional argument (semantic depends on ptype)
2311	arg3 = 0 ): # optional argument (semantic depends on ptype)
2312
2313	self.index = 0 # global index ( set by addPeriph() )
2314	self.channels = channels
2315	self.ptype = ptype
2316	self.subtype = subtype
2317	self.arg0 = arg0
2318	self.arg1 = arg1
2319	self.arg2 = arg2
2320	self.arg3 = arg3
2321	self.pseg = pseg
2322	self.irqs = []
2323	return
2324
2325	################
2326	def xml( self ): # xml for a periph
2327
2328	s = ' <periph type="%s"' % self.ptype
2329	s += ' subtype="%s"' % self.subtype
2330	s += ' psegname="%s"' % self.pseg.name
2331	s += ' channels="%d"' % self.channels
2332	s += ' arg0="%d"' % self.arg0
2333	s += ' arg1="%d"' % self.arg1
2334	s += ' arg2="%d"' % self.arg2
2335	s += ' arg3="%d"' % self.arg3
2336	if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') ):
2337	s += ' >\n'
2338	for irq in self.irqs: s += irq.xml()
2339	s += ' </periph>\n'
2340	else:
2341	s += ' />\n'
2342	return s
2343
2344	#############################################
2345	def cbin( self, mapping, verbose, expected ): # C binary structure for Periph
2346
2347	if ( verbose ):
2348	print '*** cbin for periph %s in cluster [%d,%d]' \
2349	% (self.ptype, self.pseg.x, self.pseg.y)
2350
2351	# check index
2352	if (self.index != expected):
2353	print '[genmap error] in Periph.cbin()'
2354	print ' periph global index = %d / expected = %d' % (self.index,expected)
2355	sys.exit(1)
2356
2357	# compute pseg global index
2358	pseg_id = self.pseg.index
2359
2360	# compute first irq global index
2361	if ( len(self.irqs) > 0 ):
2362	irq_id = self.irqs[0].index
2363	else:
2364	irq_id = 0
2365
2366	# compute numerical value for ptype
2367	ptype_id = 0xFFFFFFFF
2368	for x in xrange( len(PERIPHTYPES) ):
2369	if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x
2370
2371	if ( ptype_id == 0xFFFFFFFF ):
2372	print '[genmap error] in Periph.cbin()'
2373	print ' undefined peripheral type %s' % self.ptype
2374	sys.exit(1)
2375
2376	# compute numerical value for subtype
2377	subtype_id = 0xFFFFFFFF
2378	if (self.ptype == 'IOC'):
2379	for x in xrange( len(IOCSUBTYPES) ):
2380	if ( self.subtype == IOCSUBTYPES[x] ): subtype_id = x
2381	if (self.ptype == 'MWR'):
2382	for x in xrange( len(MWRSUBTYPES) ):
2383	if ( self.subtype == MWRSUBTYPES[x] ): subtype_id = x
2384
2385	byte_stream = bytearray()
2386	byte_stream += mapping.int2bytes( 4 , ptype_id ) # peripheral type
2387	byte_stream += mapping.int2bytes( 4 , subtype_id ) # peripheral subtype
2388	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
2389	byte_stream += mapping.int2bytes( 4 , self.channels ) # number of channels
2390	byte_stream += mapping.int2bytes( 4 , self.arg0 ) # optionnal arg0
2391	byte_stream += mapping.int2bytes( 4 , self.arg1 ) # optionnal arg1
2392	byte_stream += mapping.int2bytes( 4 , self.arg2 ) # optionnal arg2
2393	byte_stream += mapping.int2bytes( 4 , self.arg3 ) # optionnal arg3
2394	byte_stream += mapping.int2bytes( 4 , len( self.irqs ) ) # number of input irqs
2395	byte_stream += mapping.int2bytes( 4 , irq_id ) # first irq global index
2396
2397	if ( verbose ):
2398	print 'ptype = %d' % ptype_id
2399	print 'subtype = %d' % subtype_id
2400	print 'pseg_id = %d' % pseg_id
2401	print 'nb_irqs = %d' % len( self.irqs )
2402	print 'irq_id = %d' % irq_id
2403	return byte_stream
2404
2405	######################################################################################
2406	class Irq ( object ):
2407	######################################################################################
2408	def __init__( self,
2409	irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only)
2410	srcid, # input IRQ index (for XCU or PIC)
2411	isrtype, # Type of ISR to be executed
2412	channel = 0 ): # channel index for multi-channel ISR
2413
2414	assert irqtype in IRQTYPES
2415	assert isrtype in ISRTYPES
2416	assert srcid < 32
2417
2418	self.index = 0 # global index ( set by addIrq() )
2419	self.irqtype = irqtype # IRQ type
2420	self.srcid = srcid # source IRQ index
2421	self.isrtype = isrtype # ISR type
2422	self.channel = channel # channel index (for multi-channels ISR)
2423	return
2424
2425	################
2426	def xml( self ): # xml for Irq
2427
2428	return ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" />\n' \
2429	% ( self.irqtype, self.srcid, self.isrtype, self.channel )
2430
2431	#############################################
2432	def cbin( self, mapping, verbose, expected ): # C binary structure for Irq
2433
2434	if ( verbose ):
2435	print '*** cbin for irq[%d]' % (self.index)
2436
2437	# check index
2438	if (self.index != expected):
2439	print '[genmap error] in Irq.cbin()'
2440	print ' irq global index = %d / expected = %d' % (self.index,expected)
2441	sys.exit(1)
2442
2443	# compute numerical value for irqtype
2444	irqtype_id = 0xFFFFFFFF
2445	for x in xrange( len(IRQTYPES) ):
2446	if ( self.irqtype == IRQTYPES[x] ): irqtype_id = x
2447
2448	if ( irqtype_id == 0xFFFFFFFF ):
2449	print '[genmap error] in Irq.cbin()'
2450	print ' undefined irqtype %s' % self.irqtype
2451	sys.exit(1)
2452
2453	# compute numerical value for isrtype
2454	isrtype_id = 0xFFFFFFFF
2455	for x in xrange( len(ISRTYPES) ):
2456	if ( self.isrtype == ISRTYPES[x] ): isrtype_id = x
2457
2458	if ( isrtype_id == 0xFFFFFFFF ):
2459	print '[genmap error] in Irq.cbin()'
2460	print ' undefined isrtype %s' % self.isrtype
2461	sys.exit(1)
2462
2463	byte_stream = bytearray()
2464	byte_stream += mapping.int2bytes( 4, irqtype_id )
2465	byte_stream += mapping.int2bytes( 4, self.srcid )
2466	byte_stream += mapping.int2bytes( 4, isrtype_id )
2467	byte_stream += mapping.int2bytes( 4, self.channel )
2468	byte_stream += mapping.int2bytes( 4, 0 )
2469	byte_stream += mapping.int2bytes( 4, 0 )
2470
2471	if ( verbose ):
2472	print 'irqtype = %s' % self.irqtype
2473	print 'srcid = %d' % self.srcid
2474	print 'isrtype = %s' % self.isrtype
2475	print 'channel = %d' % self.channel
2476
2477	return byte_stream
2478
2479	# Local Variables:
2480	# tab-width: 4;
2481	# c-basic-offset: 4;
2482	# c-file-offsets:((innamespace . 0)(inline-open . 0));
2483	# indent-tabs-mode: nil;
2484	# End:
2485	#
2486	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
2487

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source: soft/giet_vm/giet_python/mapping.py @ 521

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