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source: soft/giet_vm/giet_python/mapping.py @ 406

Last change on this file since 406 was 406, checked in by cfuguet, 10 years ago

Introducing P_WIDTH field in hard_config.h file

This constant represents the number of bits used in the EBASE[9:0] MIPS CP0 register to encode the local processor id. This way, the EBASE[9:0] uses a complete fixed format:

X_WIDTH | Y_WIDTH | P_WIDTH

Property svn:executable set to *

File size: 101.5 KB

Line
1	#!/usr/bin/env python
2
3	import sys
4
5	##########################################################################################
6	# file : giet_mapping.py
7	# date : april 2014
8	# author : Alain Greiner
9	##########################################################################################
10	# This file contains the classes required to define a mapping for the GIET_VM.
11	# - A 'Mapping' contains a set of 'Cluster' (hardware architecture)
12	# a set of 'Vseg' (kernel virtual segments mapping)
13	# a set of 'Vspace' (several user applications).
14	# - A 'Cluster' contains a set of 'Pseg' (all physical segments in cluster)
15	# a set of 'Proc' (processors in cluster)
16	# a set of 'Periph' (peripherals in cluster)
17	# a set of 'Coproc' (coprocessors in cluster)
18	# - A 'Vspace' contains a set of 'Vseg' (user virtual segments mapping)
19	# a set of 'Task' (user tasks mapping)
20	# - A 'Vseg' contains a set of 'Vobj'
21	# - A 'Periph' contains a set of 'Irq' (only for XCU, ICU and PIC types )
22	# - A 'Coproc' contains a set of 'Cpports' (one port per MWMR channel)
23	##########################################################################################
24	# Implementation Note
25	# As described above, the various objects are distributed in the PYTHON structure:
26	# For example the psegs set is split in several subsets (one subset per cluster),
27	# or the tasks set is split in several subsets (one subset per vspace), etc...
28	# In the C binary data structure used by the giet_vm, all objects of same type
29	# are stored in a linear array (one single array for all psegs for example).
30	# For all objects, we compute and store in the PYTHON object itsel a "global index"
31	# corresponding to the index in this global array, and this index can be used as
32	# a pseudo-pointer to identify a specific object of a given type.
33	##########################################################################################
34
35	######################################################################################
36	# These global lists must be consistent with enums in mapping_info.h or irq_handler.h
37	######################################################################################
38	PERIPHTYPES = [
39	'CMA',
40	'DMA',
41	'FBF',
42	'ICU',
43	'IOB',
44	'IOC',
45	'MMC',
46	'MWR',
47	'NIC',
48	'ROM',
49	'SIM',
50	'TIM',
51	'TTY',
52	'XCU',
53	'PIC',
54	]
55
56	PERIPHSUBTYPES = [
57	'BDV',
58	'HBA',
59	'SPI',
60	'NONE',
61	]
62
63	IRQTYPES = [
64	'HWI',
65	'WTI',
66	'PTI',
67	]
68
69	ISRTYPES = [
70	'ISR_DEFAULT',
71	'ISR_TICK',
72	'ISR_TTY_RX',
73	'ISR_TTY_TX',
74	'ISR_BDV',
75	'ISR_TIMER',
76	'ISR_WAKUP',
77	'ISR_NIC_RX',
78	'ISR_NIC_TX',
79	'ISR_CMA',
80	'ISR_MMC',
81	'ISR_DMA',
82	'ISR_SPI',
83	]
84
85	VOBJTYPES = [
86	'ELF',
87	'BLOB',
88	'PTAB',
89	'PERI',
90	'MWMR',
91	'LOCK',
92	'BUFFER',
93	'BARRIER',
94	'CONST',
95	'MEMSPACE',
96	'SCHED',
97	]
98
99	VSEGMODES = [
100	'____',
101	'___U',
102	'__W_',
103	'__WU',
104	'_X__',
105	'_X_U',
106	'_XW_',
107	'_XWU',
108	'C___',
109	'C__U',
110	'C_W_',
111	'C_WU',
112	'CX__',
113	'CX_U',
114	'CXW_',
115	'CXWU',
116	]
117
118	PSEGTYPES = [
119	'RAM',
120	'ROM', # deprecated => use PERI
121	'PERI',
122	]
123
124	CP_PORT_DIRS = [
125	'TO_COPROC',
126	'FROM_COPROC',
127	]
128
129	##########################################################################################
130	class Mapping( object ):
131	##########################################################################################
132	def __init__( self,
133	name, # mapping name
134	x_size, # number of clusters in a row
135	y_size, # number of clusters in a column
136	procs_max = 2, # max number of processors per cluster
137	x_width = 4, # number of bits encoding x coordinate
138	y_width = 4, # number of bits encoding y coordinate
139	p_width = 2, # number of bits encoding local proc id
140	paddr_width = 40, # number of bits for physical address
141	coherence = 1, # hardware cache coherence when non-zero
142	irq_per_proc = 1, # number or IRQs from XCU to processor
143	use_ramdisk = False, # use ramdisk when true
144	x_io = 0, # cluster_io x coordinate
145	y_io = 0, # cluster_io y coordinate
146	peri_increment = 0x10000, # address increment for globals
147	reset_address = 0xBFC00000, # Processor wired boot_address
148	ram_base = 0, # RAM physical base address in cluster[0,0]
149	ram_size = 0 ): # RAM size in each cluster (bytes)
150
151	assert (procs_max <= (1 << p_width))
152
153	self.signature = 0xDACE2014
154	self.name = name
155	self.paddr_width = paddr_width
156	self.coherence = coherence
157	self.x_size = x_size
158	self.y_size = y_size
159	self.procs_max = procs_max
160	self.x_width = x_width
161	self.y_width = y_width
162	self.p_width = p_width
163	self.irq_per_proc = irq_per_proc
164	self.use_ramdisk = use_ramdisk
165	self.x_io = x_io
166	self.y_io = y_io
167	self.peri_increment = peri_increment
168	self.reset_address = reset_address
169	self.ram_base = ram_base
170	self.ram_size = ram_size
171
172
173	self.total_vspaces = 0
174	self.total_globals = 0
175	self.total_psegs = 0
176	self.total_vsegs = 0
177	self.total_vobjs = 0
178	self.total_tasks = 0
179	self.total_procs = 0
180	self.total_irqs = 0
181	self.total_coprocs = 0
182	self.total_cpports = 0
183	self.total_periphs = 0
184
185	self.clusters = []
186	self.globs = []
187	self.vspaces = []
188
189	for x in xrange( self.x_size ):
190	for y in xrange( self.y_size ):
191	cluster = Cluster( x , y )
192	cluster.index = (x * self.y_size) + y
193	self.clusters.append( cluster )
194
195	return
196
197	########################## add a ram pseg in a cluster
198	def addRam( self,
199	name, # pseg name
200	base, # pseg base address
201	size ): # pseg length (bytes)
202
203	# check coordinates (obtained from the base address)
204	paddr_lsb_width = self.paddr_width - self.x_width - self.y_width
205	cluster_xy = base >> paddr_lsb_width
206	x = cluster_xy >> (self.y_width);
207	y = cluster_xy & ((1 << self.y_width) - 1)
208
209	assert (base & 0xFFF) == 0
210
211	assert (x < self.x_size) and (y < self.y_size)
212
213	assert ( (base & ((1<<paddr_lsb_width)-1)) == self.ram_base )
214
215	assert ( size == self.ram_size )
216
217	cluster_id = (x * self.y_size) + y
218
219	# add one pseg in the mapping
220	pseg = Pseg( name, base, size, x, y, 'RAM' )
221	self.clusters[cluster_id].psegs.append( pseg )
222	pseg.index = self.total_psegs
223	self.total_psegs += 1
224
225	return pseg
226
227	############################## add a peripheral and the associated pseg in a cluster
228	def addPeriph( self,
229	name, # associated pseg name
230	base, # associated pseg base address
231	size, # associated pseg length (bytes)
232	ptype, # peripheral type
233	subtype = 'NONE', # peripheral subtype
234	channels = 1, # number of channels
235	arg = 0 ): # optional argument (semantic depends on ptype)
236
237	# check cluster coordinates (obtained from the base address)
238	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
239	x = cluster_xy >> (self.y_width);
240	y = cluster_xy & ((1 << self.y_width) - 1)
241
242	assert (x < self.x_size) and (y < self.y_size)
243
244	assert (base & 0xFFF) == 0
245
246	assert ptype in PERIPHTYPES
247
248	assert subtype in PERIPHSUBTYPES
249
250	cluster_id = (x * self.y_size) + y
251
252	# add one pseg into mapping
253	pseg = Pseg( name, base, size, x, y, 'PERI' )
254	self.clusters[cluster_id].psegs.append( pseg )
255	pseg.index = self.total_psegs
256	self.total_psegs += 1
257
258	# add one periph into mapping
259	periph = Periph( pseg, ptype, subtype, channels, arg )
260	self.clusters[cluster_id].periphs.append( periph )
261	periph.index = self.total_periphs
262	self.total_periphs += 1
263
264	return periph
265
266	################################ add an IRQ in a peripheral
267	def addIrq( self,
268	periph, # peripheral containing IRQ (PIC or XCU)
269	index, # peripheral input port index
270	isrtype, # ISR type
271	channel = 0 ): # channel for multi-channels ISR
272
273	assert isrtype in ISRTYPES
274
275	assert index < 32
276
277	# add one irq into mapping
278	irq = Irq( 'HWI', index , isrtype, channel )
279	periph.irqs.append( irq )
280	irq.index = self.total_irqs
281	self.total_irqs += 1
282
283	return irq
284
285	########################## add a processor in a cluster
286	def addProc( self,
287	x, # cluster x coordinate
288	y, # cluster y coordinate
289	p ): # processor local index
290
291	assert (x < self.x_size) and (y < self.y_size)
292
293	cluster_id = (x * self.y_size) + y
294
295	# add one proc into mapping
296	proc = Processor( x, y, p )
297	self.clusters[cluster_id].procs.append( proc )
298	proc.index = self.total_procs
299	self.total_procs += 1
300
301	return proc
302
303	############################## add a coprocessor in a cluster
304	def addCoproc( self,
305	name, # associated pseg name
306	base, # associated pseg base address
307	size ): # associated pseg length
308
309	# check cluster coordinates (obtained from the base address)
310	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
311	x = cluster_xy >> (self.y_width);
312	y = cluster_xy & ((1 << self.y_width) - 1)
313
314	assert (x < self.x_size) and (y < self.y_size)
315
316	cluster_id = (x * self.y_size) + y
317
318	# add one pseg into mapping
319	pseg = Pseg( name, base, size, x, y, 'PERI' )
320	self.clusters[cluster_id].psegs.append( pseg )
321	pseg.index = self.total_psegs
322	self.total_psegs += 1
323
324	# add one coproc into mapping
325	periph = Coproc( pseg )
326	self.clusters[cluster_id].coprocs.append( coproc )
327	periph.index = self.total_coprocs
328	self.total_coprocs += 1
329
330	return coproc
331
332	################################## add a port in a coprocessor
333	def addPort( self,
334	coproc, # coprocessor containing the port
335	direction, # direction (TO_COPROC / FROM_COPROC)
336	vspacename, # name of vspace using the coproc
337	mwmrname ): # name of the vobj defining the MWMR channel
338
339	assert direction in CP_PORT_DIRS
340
341	# add one cpport into mapping
342	port = Cpport( direction, vspacename, mwmrname )
343	coproc.ports.append( port )
344	port.index = self.total_cpports
345	self.total_cpports += 1
346
347	return port
348
349	############################ add one (or several) global vseg into mapping
350	def addGlobal( self,
351	name, # vseg name
352	vbase, # virtual base address
353	size, # vobj length (bytes)
354	mode, # CXWU flags
355	vtype, # vobj type
356	x, # destination x coordinate
357	y, # destination y coordinate
358	pseg, # destination pseg name
359	identity = False, # identity mapping required if true
360	binpath = '', # pathname for binary code
361	local = False ): # non shared vseg when true
362
363	assert mode in VSEGMODES
364
365	assert vtype in VOBJTYPES
366
367	assert (vbase & 0xFFF) == 0
368
369	assert (x < self.x_size) and (y < self.y_size)
370
371	# add one vseg into mapping
372	vseg = Vseg( name, vbase, mode, x, y, pseg,
373	identity = identity, local = local )
374
375	self.globs.append( vseg )
376	self.total_globals += 1
377	vseg.index = self.total_vsegs
378	self.total_vsegs += 1
379
380	# add one vobj into mapping
381	vobj = Vobj( name, size, vtype, binpath, 0, 0 )
382	vseg.vobjs.append( vobj )
383	vobj.index = self.total_vobjs
384	self.total_vobjs += 1
385
386	return
387
388	################################ add a vspace into mapping
389	def addVspace( self,
390	name, # vspace name
391	startname ): # name of vobj containing start_vector
392
393	# add one vspace into mapping
394	vspace = Vspace( name, startname )
395	self.vspaces.append( vspace )
396	vspace.index = self.total_vspaces
397	self.total_vspaces += 1
398
399	return vspace
400
401	################################# add a private vseg and a vobj in a vspace
402	def addVseg( self,
403	vspace, # vspace containing the vseg
404	name, # vseg name
405	vbase, # virtual base address
406	size, # vobj length (bytes)
407	mode, # CXWU flags
408	vtype, # vobj type
409	x, # destination x coordinate
410	y, # destination y coordinate
411	pseg, # destination pseg name
412	binpath = '', # pathname for binary code
413	align = 0, # alignment required
414	init = 0, # initial value
415	local = False ): # non shared when true
416
417	assert mode in VSEGMODES
418
419	assert vtype in VOBJTYPES
420
421	assert (x < self.x_size) and (y < self.y_size)
422
423	# add one vseg into mapping
424	vseg = Vseg( name, vbase, mode, x, y, pseg, local = local )
425	vspace.vsegs.append( vseg )
426	vseg.index = self.total_vsegs
427	self.total_vsegs += 1
428
429	# add one vobj into mapping
430	vobj = Vobj( name, size, vtype, binpath, align, init )
431	vseg.vobjs.append( vobj )
432	vobj.index = self.total_vobjs
433	self.total_vobjs += 1
434
435	return vseg
436
437	################################ add a vobj in a private vseg
438	def addVobj( self,
439	vseg, # vseg containing vobj
440	name, # vobj name
441	size, # vobj length (bytes)
442	vtype, # vobj type
443	binpath = '', # pathname to binary
444	align = 0, # alignment constraint
445	init = 0 ): # initial value
446
447	assert vtype in VOBJTYPES
448
449	# add one vobj into mapping
450	vobj = Vobj( name, size, vtype, binpath, align, init )
451	vseg.vobjs.append( vobj )
452	vobj.index = self.total_vobjs
453	self.total_vobjs += 1
454
455	return vobj
456
457	################################ add a task in a vspace
458	def addTask( self,
459	vspace, # vspace containing task
460	name, # task name
461	trdid, # task index in vspace
462	x, # destination x coordinate
463	y, # destination y coordinate
464	lpid, # destination processor local index
465	stackname, # name of vobj containing stack
466	heapname, # name of vobj containing heap
467	startid, # index in start_vector
468	usetty = False, # request a private TTY channel
469	usenic = False, # request a private NIC channel
470	usecma = False, # request a private CMA channel
471	usehba = False, # request a private HBA channel
472	usetim = False ): # request a private TIM channel
473
474	assert (x < self.x_size) and (y < self.y_size)
475	assert lpid < self.procs_max
476
477	# add one task into mapping
478	task = Task( name, trdid, x, y, lpid, stackname, heapname, startid,
479	usetty, usenic, usecma, usehba, usetim )
480	vspace.tasks.append( task )
481	task.index = self.total_tasks
482	self.total_tasks += 1
483
484	return task
485
486	#################################
487	def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array
488
489	byte_stream = bytearray()
490	length = len( s )
491	if length < (nbytes - 1):
492	for b in s:
493	byte_stream.append( b )
494	for x in xrange(nbytes-length):
495	byte_stream.append( '\0' )
496	else:
497	print '[genmap error] in str2bytes() : string %s too long' % s
498	sys.exit(1)
499
500	return byte_stream
501
502	###################################
503	def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array
504
505	byte_stream = bytearray()
506	for n in xrange( nbytes ):
507	byte_stream.append( (val >> (n<<3)) & 0xFF )
508
509	return byte_stream
510
511	################
512	def xml( self ): # xml file generation for mapping
513
514	s = '<?xml version="1.0"?>\n\n'
515	s += '<mapping_info signature = "0x%x"\n' % (self.signature)
516	s += ' name = "%s"\n' % (self.name)
517	s += ' x_size = "%d"\n' % (self.x_size)
518	s += ' y_size = "%d"\n' % (self.y_size)
519	s += ' x_width = "%d"\n' % (self.x_width)
520	s += ' y_width = "%d"\n' % (self.y_width)
521	s += ' irq_per_proc = "%d"\n' % (self.irq_per_proc)
522	s += ' use_ramdisk = "%d"\n' % (self.use_ramdisk)
523	s += ' x_io = "%d"\n' % (self.x_io)
524	s += ' y_io = "%d" >\n' % (self.y_io)
525	s += '\n'
526
527	s += ' <clusterset>\n'
528	for x in xrange ( self.x_size ):
529	for y in xrange ( self.y_size ):
530	cluster_id = (x * self.y_size) + y
531	s += self.clusters[cluster_id].xml()
532	s += ' </clusterset>\n'
533	s += '\n'
534
535	s += ' <globalset>\n'
536	for vseg in self.globs: s += vseg.xml()
537	s += ' </globalset>\n'
538	s += '\n'
539
540	s += ' <vspaceset>\n'
541	for vspace in self.vspaces: s += vspace.xml()
542	s += ' </vspaceset>\n'
543
544	s += '</mapping_info>\n'
545	return s
546
547	#########################
548	def cbin( self, verbose ): # C binary structure generation for mapping
549
550	byte_stream = bytearray()
551
552	# header
553	byte_stream += self.int2bytes(4, self.signature)
554	byte_stream += self.int2bytes(4, self.x_size)
555	byte_stream += self.int2bytes(4, self.y_size)
556	byte_stream += self.int2bytes(4, self.x_width)
557	byte_stream += self.int2bytes(4, self.y_width)
558	byte_stream += self.int2bytes(4, self.x_io)
559	byte_stream += self.int2bytes(4, self.y_io)
560	byte_stream += self.int2bytes(4, self.irq_per_proc)
561	byte_stream += self.int2bytes(4, self.use_ramdisk)
562	byte_stream += self.int2bytes(4, self.total_globals)
563	byte_stream += self.int2bytes(4, self.total_vspaces)
564	byte_stream += self.int2bytes(4, self.total_psegs)
565	byte_stream += self.int2bytes(4, self.total_vsegs)
566	byte_stream += self.int2bytes(4, self.total_vobjs)
567	byte_stream += self.int2bytes(4, self.total_tasks)
568	byte_stream += self.int2bytes(4, self.total_procs)
569	byte_stream += self.int2bytes(4, self.total_irqs)
570	byte_stream += self.int2bytes(4, self.total_coprocs)
571	byte_stream += self.int2bytes(4, self.total_cpports)
572	byte_stream += self.int2bytes(4, self.total_periphs)
573	byte_stream += self.str2bytes(32, self.name)
574
575	if ( verbose ):
576	print '\n'
577	print 'name = %s' % self.name
578	print 'signature = %x' % self.signature
579	print 'x_size = %d' % self.x_size
580	print 'y_size = %d' % self.y_size
581	print 'x_width = %d' % self.x_width
582	print 'y_width = %d' % self.y_width
583	print 'x_io = %d' % self.x_io
584	print 'y_io = %d' % self.y_io
585	print 'irq_per_proc = %d' % self.irq_per_proc
586	print 'use_ramdisk = %d' % self.use_ramdisk
587	print 'total_globals = %d' % self.total_globals
588	print 'total_psegs = %d' % self.total_psegs
589	print 'total_vsegs = %d' % self.total_vsegs
590	print 'total_vobjs = %d' % self.total_vobjs
591	print 'total_tasks = %d' % self.total_tasks
592	print 'total_procs = %d' % self.total_procs
593	print 'total_irqs = %d' % self.total_irqs
594	print 'total_coprocs = %d' % self.total_coprocs
595	print 'total_cpports = %d' % self.total_cpports
596	print 'total_periphs = %d' % self.total_periphs
597	print '\n'
598
599	# clusters array
600	index = 0
601	for cluster in self.clusters:
602	byte_stream += cluster.cbin( self, verbose, index )
603	index += 1
604
605	if ( verbose ): print '\n'
606
607	# psegs array
608	index = 0
609	for cluster in self.clusters:
610	for pseg in cluster.psegs:
611	byte_stream += pseg.cbin( self, verbose, index, cluster )
612	index += 1
613
614	if ( verbose ): print '\n'
615
616	# vspaces array
617	index = 0
618	for vspace in self.vspaces:
619	byte_stream += vspace.cbin( self, verbose, index )
620	index += 1
621
622	if ( verbose ): print '\n'
623
624	# vsegs array
625	index = 0
626	for vseg in self.globs:
627	byte_stream += vseg.cbin( self, verbose, index )
628	index += 1
629	for vspace in self.vspaces:
630	for vseg in vspace.vsegs:
631	byte_stream += vseg.cbin( self, verbose, index )
632	index += 1
633
634	if ( verbose ): print '\n'
635
636	# vobjs array
637	index = 0
638	for vseg in self.globs:
639	for vobj in vseg.vobjs:
640	byte_stream += vobj.cbin( self, verbose, index )
641	index += 1
642	for vspace in self.vspaces:
643	for vseg in vspace.vsegs:
644	for vobj in vseg.vobjs:
645	byte_stream += vobj.cbin( self, verbose, index )
646	index += 1
647
648	if ( verbose ): print '\n'
649
650	# tasks array
651	index = 0
652	for vspace in self.vspaces:
653	for task in vspace.tasks:
654	byte_stream += task.cbin( self, verbose, index, vspace )
655	index += 1
656
657	if ( verbose ): print '\n'
658
659	# procs array
660	index = 0
661	for cluster in self.clusters:
662	for proc in cluster.procs:
663	byte_stream += proc.cbin( self, verbose, index )
664	index += 1
665
666	if ( verbose ): print '\n'
667
668	# irqs array
669	index = 0
670	for cluster in self.clusters:
671	for periph in cluster.periphs:
672	for irq in periph.irqs:
673	byte_stream += irq.cbin( self, verbose, index )
674	index += 1
675
676	if ( verbose ): print '\n'
677
678	# coprocs array
679	index = 0
680	for cluster in self.clusters:
681	for coproc in cluster.coprocs:
682	byte_stream += coproc.cbin( self, verbose, index )
683	index += 1
684
685	if ( verbose ): print '\n'
686
687	# cpports array
688	index = 0
689	for cluster in self.clusters:
690	for coproc in cluster.coprocs:
691	for port in coproc.ports:
692	byte_stream += port.cbin( self, verbose, index )
693	index += 1
694
695	if ( verbose ): print '\n'
696
697	# periphs array
698	index = 0
699	for cluster in self.clusters:
700	for periph in cluster.periphs:
701	byte_stream += periph.cbin( self, verbose, index )
702	index += 1
703
704	return byte_stream
705	# end of cbin()
706
707	#######################
708	def giet_vsegs( self ): # compute string for giet_vsegs.ld file
709	# required by giet_vm compilation
710
711	# search the vsegs required for the giet_vsegs.ld
712	boot_code_found = False
713	boot_data_found = False
714	kernel_uncdata_found = False
715	kernel_data_found = False
716	kernel_code_found = False
717	kernel_init_found = False
718	for vseg in self.globs:
719
720	if ( vseg.name == 'seg_boot_code' ):
721	boot_code_vbase = vseg.vbase
722	boot_code_size = vseg.vobjs[0].length
723	boot_code_found = True
724
725	if ( vseg.name == 'seg_boot_data' ):
726	boot_data_vbase = vseg.vbase
727	boot_data_size = vseg.vobjs[0].length
728	boot_data_found = True
729
730	if ( vseg.name == 'seg_kernel_uncdata' ):
731	kernel_uncdata_vbase = vseg.vbase
732	kernel_uncdata_size = vseg.vobjs[0].length
733	kernel_uncdata_found = True
734
735	if ( vseg.name == 'seg_kernel_data' ):
736	kernel_data_vbase = vseg.vbase
737	kernel_data_size = vseg.vobjs[0].length
738	kernel_data_found = True
739
740	if ( vseg.name == 'seg_kernel_code' ):
741	kernel_code_vbase = vseg.vbase
742	kernel_code_size = vseg.vobjs[0].length
743	kernel_code_found = True
744
745	if ( vseg.name == 'seg_kernel_init' ):
746	kernel_init_vbase = vseg.vbase
747	kernel_init_size = vseg.vobjs[0].length
748	kernel_init_found = True
749
750	# check if all required vsegs have been found
751	if ( boot_code_found == False ):
752	print '[genmap error] in giet_vsegs() : seg_boot_code vseg missing'
753	sys.exit()
754
755	if ( boot_data_found == False ):
756	print '[genmap error] in giet_vsegs() : seg_boot_data vseg missing'
757	sys.exit()
758
759	if ( kernel_data_found == False ):
760	print '[genmap error] in giet_vsegs() : seg_kernel_data vseg missing'
761	sys.exit()
762
763	if ( kernel_uncdata_found == False ):
764	print '[genmap error] in giet_vsegs() : seg_kernel_uncdata vseg missing'
765	sys.exit()
766
767	if ( kernel_code_found == False ):
768	print '[genmap error] in giet_vsegs() : seg_kernel_code vseg missing'
769	sys.exit()
770
771	if ( kernel_init_found == False ):
772	print '[genmap error] in giet_vsegs() : seg_kernel_init vseg missing'
773	sys.exit()
774
775	# build string
776	s = '/* Generated by genmap for %s */\n' % self.name
777	s += '\n'
778
779	s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase
780	s += 'boot_code_size = 0x%x;\n' % boot_code_size
781	s += '\n'
782	s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase
783	s += 'boot_data_size = 0x%x;\n' % boot_data_size
784	s += '\n'
785	s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase
786	s += 'kernel_code_size = 0x%x;\n' % kernel_code_size
787	s += '\n'
788	s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase
789	s += 'kernel_data_size = 0x%x;\n' % kernel_data_size
790	s += '\n'
791	s += 'kernel_uncdata_vbase = 0x%x;\n' % kernel_uncdata_vbase
792	s += 'kernel_uncdata_size = 0x%x;\n' % kernel_uncdata_size
793	s += '\n'
794	s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase
795	s += 'kernel_init_size = 0x%x;\n' % kernel_init_size
796	s += '\n'
797
798	return s
799
800	########################
801	def hard_config( self ): # compute string for hard_config.h file required by
802	# - top.cpp compilation
803	# - giet_vm compilation
804	# - tsar_preloader compilation
805
806	nb_total_procs = 0
807
808	# for each peripheral type, define default values
809	# for pbase address, size, number of components, and channels
810	nb_cma = 0
811	cma_channels = 0
812	seg_cma_base = 0xFFFFFFFF
813	seg_cma_size = 0
814
815	nb_dma = 0
816	dma_channels = 0
817	seg_dma_base = 0xFFFFFFFF
818	seg_dma_size = 0
819
820	nb_fbf = 0
821	fbf_channels = 0
822	fbf_arg = 0
823	seg_fbf_base = 0xFFFFFFFF
824	seg_fbf_size = 0
825
826	nb_icu = 0
827	icu_channels = 0
828	seg_icu_base = 0xFFFFFFFF
829	seg_icu_size = 0
830
831	nb_iob = 0
832	iob_channels = 0
833	seg_iob_base = 0xFFFFFFFF
834	seg_iob_size = 0
835
836	nb_ioc = 0
837	ioc_channels = 0
838	seg_ioc_base = 0xFFFFFFFF
839	seg_ioc_size = 0
840
841	nb_mmc = 0
842	mmc_channels = 0
843	seg_mmc_base = 0xFFFFFFFF
844	seg_mmc_size = 0
845
846	nb_mwr = 0
847	mwr_channels = 0
848	seg_mwr_base = 0xFFFFFFFF
849	seg_mwr_size = 0
850
851	nb_nic = 0
852	nic_channels = 0
853	seg_nic_base = 0xFFFFFFFF
854	seg_nic_size = 0
855
856	nb_pic = 0
857	pic_channels = 0
858	seg_pic_base = 0xFFFFFFFF
859	seg_pic_size = 0
860
861	nb_rom = 0
862	rom_channels = 0
863	seg_rom_base = 0xFFFFFFFF
864	seg_rom_size = 0
865
866	nb_sim = 0
867	sim_channels = 0
868	seg_sim_base = 0xFFFFFFFF
869	seg_sim_size = 0
870
871	nb_tim = 0
872	tim_channels = 0
873	seg_tim_base = 0xFFFFFFFF
874	seg_tim_size = 0
875
876	nb_tty = 0
877	tty_channels = 0
878	seg_tty_base = 0xFFFFFFFF
879	seg_tty_size = 0
880
881	nb_xcu = 0
882	xcu_channels = 0
883	xcu_arg = 0
884	seg_xcu_base = 0xFFFFFFFF
885	seg_xcu_size = 0
886
887	use_bdv = False
888	use_spi = False
889	use_hba = False
890
891	# get peripherals attributes
892	for cluster in self.clusters:
893	for periph in cluster.periphs:
894	if ( periph.ptype == 'CMA' ):
895	seg_cma_base = periph.pseg.base & 0xFFFFFFFF
896	seg_cma_size = periph.pseg.size
897	cma_channels = periph.channels
898	nb_cma +=1
899
900	elif ( periph.ptype == 'DMA' ):
901	seg_dma_base = periph.pseg.base & 0xFFFFFFFF
902	seg_dma_size = periph.pseg.size
903	dma_channels = periph.channels
904	nb_dma +=1
905
906	elif ( periph.ptype == 'FBF' ):
907	seg_fbf_base = periph.pseg.base & 0xFFFFFFFF
908	seg_fbf_size = periph.pseg.size
909	fbf_channels = periph.channels
910	fbf_arg = periph.arg
911	nb_fbf +=1
912
913	elif ( periph.ptype == 'ICU' ):
914	seg_icu_base = periph.pseg.base & 0xFFFFFFFF
915	seg_icu_size = periph.pseg.size
916	icu_channels = periph.channels
917	nb_icu +=1
918
919	elif ( periph.ptype == 'IOB' ):
920	seg_iob_base = periph.pseg.base & 0xFFFFFFFF
921	seg_iob_size = periph.pseg.size
922	iob_channels = periph.channels
923	nb_iob +=1
924
925	elif ( periph.ptype == 'IOC' ):
926	seg_ioc_base = periph.pseg.base & 0xFFFFFFFF
927	seg_ioc_size = periph.pseg.size
928	ioc_channels = periph.channels
929	nb_ioc += 1
930
931	if self.use_ramdisk: continue
932
933	if ( periph.subtype == 'BDV' ): use_bdv = True
934	elif ( periph.subtype == 'HBA' ): use_hba = True
935	elif ( periph.subtype == 'SPI' ): use_spi = True
936
937	elif ( periph.ptype == 'MMC' ):
938	seg_mmc_base = periph.pseg.base & 0xFFFFFFFF
939	seg_mmc_size = periph.pseg.size
940	mmc_channels = periph.channels
941	nb_mmc +=1
942
943	elif ( periph.ptype == 'MWR' ):
944	seg_mwr_base = periph.pseg.base & 0xFFFFFFFF
945	seg_wmr_size = periph.pseg.size
946	mwr_channels = periph.channels
947	nb_mwr +=1
948
949	elif ( periph.ptype == 'ROM' ):
950	seg_rom_base = periph.pseg.base & 0xFFFFFFFF
951	seg_rom_size = periph.pseg.size
952	rom_channels = periph.channels
953	nb_rom +=1
954
955	elif ( periph.ptype == 'SIM' ):
956	seg_sim_base = periph.pseg.base & 0xFFFFFFFF
957	seg_sim_size = periph.pseg.size
958	sim_channels = periph.channels
959	nb_sim +=1
960
961	elif ( periph.ptype == 'NIC' ):
962	seg_nic_base = periph.pseg.base & 0xFFFFFFFF
963	seg_nic_size = periph.pseg.size
964	nic_channels = periph.channels
965	nb_nic +=1
966
967	elif ( periph.ptype == 'PIC' ):
968	seg_pic_base = periph.pseg.base & 0xFFFFFFFF
969	seg_pic_size = periph.pseg.size
970	pic_channels = periph.channels
971	nb_pic +=1
972
973	elif ( periph.ptype == 'TIM' ):
974	seg_tim_base = periph.pseg.base & 0xFFFFFFFF
975	seg_tim_size = periph.pseg.size
976	tim_channels = periph.channels
977	nb_tim +=1
978
979	elif ( periph.ptype == 'TTY' ):
980	seg_tty_base = periph.pseg.base & 0xFFFFFFFF
981	seg_tty_size = periph.pseg.size
982	tty_channels = periph.channels
983	nb_tty +=1
984
985	elif ( periph.ptype == 'XCU' ):
986	seg_xcu_base = periph.pseg.base & 0xFFFFFFFF
987	seg_xcu_size = periph.pseg.size
988	xcu_channels = periph.channels
989	xcu_arg = periph.arg
990	nb_xcu +=1
991
992	# don't mix ICU and XCU
993	assert ( nb_icu*nb_xcu == 0 )
994
995	# no more than two access to external peripherals
996	assert ( nb_fbf <= 2 )
997	assert ( nb_cma <= 2 )
998	assert ( nb_ioc <= 2 )
999	assert ( nb_nic <= 2 )
1000	assert ( nb_tim <= 2 )
1001	assert ( nb_tty <= 2 )
1002	assert ( nb_pic <= 2 )
1003
1004	# one and only one type of IOC controller
1005	nb_iocs = 0
1006	if use_hba : nb_iocs += 1
1007	if use_bdv : nb_iocs += 1
1008	if use_spi : nb_iocs += 1
1009	if self.use_ramdisk: nb_iocs += 1
1010	assert ( nb_iocs == 1 )
1011
1012	# Compute total number of processors
1013	for cluster in self.clusters:
1014	nb_total_procs += len( cluster.procs )
1015
1016	# Compute physical addresses for BOOT vsegs
1017	boot_mapping_found = False
1018	boot_code_found = False
1019	boot_data_found = False
1020	boot_stack_found = False
1021
1022	for vseg in self.globs:
1023	if ( vseg.name == 'seg_boot_mapping' ):
1024	boot_mapping_base = vseg.vbase
1025	boot_mapping_size = vseg.vobjs[0].length
1026	boot_mapping_identity = vseg.identity
1027	boot_mapping_found = True
1028
1029	if ( vseg.name == 'seg_boot_code' ):
1030	boot_code_base = vseg.vbase
1031	boot_code_size = vseg.vobjs[0].length
1032	boot_code_identity = vseg.identity
1033	boot_code_found = True
1034
1035	if ( vseg.name == 'seg_boot_data' ):
1036	boot_data_base = vseg.vbase
1037	boot_data_size = vseg.vobjs[0].length
1038	boot_data_identity = vseg.identity
1039	boot_data_found = True
1040
1041	if ( vseg.name == 'seg_boot_stack' ):
1042	boot_stack_base = vseg.vbase
1043	boot_stack_size = vseg.vobjs[0].length
1044	boot_stack_identity = vseg.identity
1045	boot_stack_found = True
1046
1047	# check that BOOT vsegs are found and identity mapping
1048	if ( (boot_mapping_found == False) or (boot_mapping_identity == False) ):
1049	print '[genmap error] in hard_config() : seg_boot_mapping missing or not ident'
1050	sys.exit()
1051
1052	if ( (boot_code_found == False) or (boot_code_identity == False) ):
1053	print '[genmap error] in hard_config() : seg_boot_code missing or not ident'
1054	sys.exit()
1055
1056	if ( (boot_data_found == False) or (boot_data_identity == False) ):
1057	print '[genmap error] in hard_config() : seg_boot_data missing or not ident'
1058	sys.exit()
1059
1060	if ( (boot_stack_found == False) or (boot_stack_identity == False) ):
1061	print '[genmap error] in giet_vsegs() : seg_boot_stack missing or not ident'
1062	sys.exit()
1063
1064	# Search RAMDISK global vseg if required
1065	seg_rdk_base = 0xFFFFFFFF
1066	seg_rdk_size = 0
1067	seg_rdk_found = False
1068
1069	if self.use_ramdisk:
1070	for vseg in self.globs:
1071	if ( vseg.name == 'seg_rdk' ):
1072	seg_rdk_base = vseg.vbase
1073	seg_rdk_size = vseg.vobjs[0].length
1074	seg_rdk_found = True
1075
1076	if ( seg_rdk_found == False ):
1077	print 'Error in hard_config() "seg_ramdisk" not found'
1078	sys.exit(1)
1079
1080	# build string
1081	s = '/* Generated by genmap for %s */\n' % self.name
1082	s += '\n'
1083	s += '#ifndef HARD_CONFIG_H\n'
1084	s += '#define HARD_CONFIG_H\n'
1085	s += '\n'
1086
1087	s += '/* General platform parameters */\n'
1088	s += '\n'
1089	s += '#define X_SIZE %d\n' % self.x_size
1090	s += '#define Y_SIZE %d\n' % self.y_size
1091	s += '#define X_WIDTH %d\n' % self.x_width
1092	s += '#define Y_WIDTH %d\n' % self.y_width
1093	s += '#define P_WIDTH %d\n' % self.p_width
1094	s += '#define X_IO %d\n' % self.x_io
1095	s += '#define Y_IO %d\n' % self.y_io
1096	s += '#define NB_PROCS_MAX %d\n' % self.procs_max
1097	s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc
1098	s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address
1099	s += '#define NB_TOTAL_PROCS %d\n' % nb_total_procs
1100	s += '\n'
1101
1102	s += '/* Peripherals */\n'
1103	s += '\n'
1104	s += '#define NB_TTY_CHANNELS %d\n' % tty_channels
1105	s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels
1106	s += '#define NB_NIC_CHANNELS %d\n' % nic_channels
1107	s += '#define NB_CMA_CHANNELS %d\n' % cma_channels
1108	s += '#define NB_TIM_CHANNELS %d\n' % tim_channels
1109	s += '#define NB_DMA_CHANNELS %d\n' % dma_channels
1110	s += '\n'
1111	s += '#define USE_XCU %d\n' % ( nb_xcu != 0 )
1112	s += '#define USE_IOB %d\n' % ( nb_iob != 0 )
1113	s += '#define USE_PIC %d\n' % ( nb_pic != 0 )
1114	s += '#define USE_FBF %d\n' % ( nb_fbf != 0 )
1115	s += '\n'
1116	s += '#define USE_IOC_BDV %d\n' % use_bdv
1117	s += '#define USE_IOC_SPI %d\n' % use_spi
1118	s += '#define USE_IOC_HBA %d\n' % use_hba
1119	s += '#define USE_IOC_RDK %d\n' % self.use_ramdisk
1120	s += '\n'
1121	s += '#define FBUF_X_SIZE %d\n' % fbf_arg
1122	s += '#define FBUF_Y_SIZE %d\n' % fbf_arg
1123	s += '\n'
1124	s += '#define XCU_NB_INPUTS %d\n' % xcu_arg
1125	s += '\n'
1126
1127	s += '/* base addresses and sizes for physical segments */\n'
1128	s += '\n'
1129	s += '#define SEG_RAM_BASE 0x%x\n' % self.ram_base
1130	s += '#define SEG_RAM_SIZE 0x%x\n' % self.ram_size
1131	s += '\n'
1132	s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base
1133	s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size
1134	s += '\n'
1135	s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base
1136	s += '#define SEG_DMA_SIZE 0x%x\n' % seg_dma_size
1137	s += '\n'
1138	s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base
1139	s += '#define SEG_FBF_SIZE 0x%x\n' % seg_fbf_size
1140	s += '\n'
1141	s += '#define SEG_ICU_BASE 0x%x\n' % seg_icu_base
1142	s += '#define SEG_ICU_SIZE 0x%x\n' % seg_icu_size
1143	s += '\n'
1144	s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base
1145	s += '#define SEG_IOB_SIZE 0x%x\n' % seg_iob_size
1146	s += '\n'
1147	s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base
1148	s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size
1149	s += '\n'
1150	s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base
1151	s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size
1152	s += '\n'
1153	s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base
1154	s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size
1155	s += '\n'
1156	s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base
1157	s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size
1158	s += '\n'
1159	s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base
1160	s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size
1161	s += '\n'
1162	s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base
1163	s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size
1164	s += '\n'
1165	s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base
1166	s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size
1167	s += '\n'
1168	s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base
1169	s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size
1170	s += '\n'
1171	s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base
1172	s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size
1173	s += '\n'
1174	s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base
1175	s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size
1176	s += '\n'
1177	s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base
1178	s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size
1179	s += '\n'
1180	s += '#define PERI_CLUSTER_INCREMENT 0x%x\n' % self.peri_increment
1181	s += '\n'
1182
1183	s += '/* physical base addresses for identity mapped vsegs */\n'
1184	s += '/* used by the GietVM OS */\n'
1185	s += '\n'
1186	s += '#define SEG_BOOT_MAPPING_BASE 0x%x\n' % boot_mapping_base
1187	s += '#define SEG_BOOT_MAPPING_SIZE 0x%x\n' % boot_mapping_size
1188	s += '\n'
1189	s += '#define SEG_BOOT_CODE_BASE 0x%x\n' % boot_code_base
1190	s += '#define SEG_BOOT_CODE_SIZE 0x%x\n' % boot_code_size
1191	s += '\n'
1192	s += '#define SEG_BOOT_DATA_BASE 0x%x\n' % boot_data_base
1193	s += '#define SEG_BOOT_DATA_SIZE 0x%x\n' % boot_data_size
1194	s += '\n'
1195	s += '#define SEG_BOOT_STACK_BASE 0x%x\n' % boot_stack_base
1196	s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size
1197	s += '#endif\n'
1198
1199	return s
1200
1201	# end of hard_config()
1202
1203	#######################
1204	def netbsd_dts( self ): # compute string for netbsd.dts file generation,
1205	# used for netbsd configuration
1206	# header
1207	s = '/dts-v1/;\n'
1208	s += '\n'
1209	s += '/{\n'
1210	s += ' #address-cells = <2>;\n'
1211	s += ' #size-cells = <1>;\n'
1212
1213	# cpus (for each cluster)
1214	s += ' cpus {\n'
1215	s += ' #address-cells = <1>;\n'
1216	s += ' #size-cells = <0>;\n'
1217
1218	for cluster in self.clusters:
1219	for proc in cluster.procs:
1220	proc_id = (((cluster.x << self.y_width) + cluster.y) << self.p_width) + proc.lpid
1221
1222	s += ' Mips,32@0x%x {\n' % proc_id
1223	s += ' device_type = "cpu";\n'
1224	s += ' icudev_type = "cpu:mips";\n'
1225	s += ' name = "Mips,32";\n'
1226	s += ' reg = <0x%x>;\n' % proc_id
1227	s += ' };\n'
1228	s += '\n'
1229
1230	s += ' };\n'
1231
1232	# rams (for each cluster)
1233	for cluster in self.clusters:
1234	for pseg in cluster.psegs:
1235
1236	if ( pseg.segtype == 'RAM' ):
1237	msb = pseg.base >> 32
1238	lsb = pseg.base & 0xFFFFFFFF
1239	size = pseg.size
1240
1241	s += ' %s@0x%x {\n' % (pseg.name, pseg.base)
1242	s += ' cached = <1>;\n'
1243	s += ' device_type = "memory";\n'
1244	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1245	s += ' };\n'
1246
1247	# peripherals (for each cluster)
1248	for cluster in self.clusters:
1249
1250	# research XCU component
1251	found_xcu = False
1252	for periph in cluster.periphs:
1253	if ( (periph.ptype == 'XCU') ):
1254	found_xcu = True
1255	xcu = periph
1256	msb = periph.pseg.base >> 32
1257	lsb = periph.pseg.base & 0xFFFFFFFF
1258	size = periph.pseg.size
1259
1260	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1261	s += ' device_type = "soclib:xicu:root";\n'
1262	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1263	s += ' input_lines = <%d>;\n' % periph.arg
1264	s += ' ipis = <%d>;\n' % periph.arg
1265	s += ' timers = <%d>;\n' % periph.arg
1266
1267	output_id = 0 # output index from XCU
1268	for lpid in xrange ( len(cluster.procs) ): # destination processor index
1269	for itid in xrange ( self.irq_per_proc ): # input irq index on processor
1270	cluster_xy = (cluster.x << self.y_width) + cluster.y
1271	proc_id = (cluster_xy << self.p_width) + lpid
1272	s += ' out@%d {\n' % output_id
1273	s += ' device_type = "soclib:xicu:filter";\n'
1274	s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid)
1275	s += ' output_line = <%d>;\n' % output_id
1276	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1277	s += ' };\n'
1278
1279	output_id += 1
1280
1281	s += ' };\n'
1282
1283	# research PIC component
1284	found_pic = False
1285	for periph in cluster.periphs:
1286	if ( periph.ptype == 'PIC' ):
1287	found_pic = True
1288	pic = periph
1289	msb = periph.pseg.base >> 32
1290	lsb = periph.pseg.base & 0xFFFFFFFF
1291	size = periph.pseg.size
1292
1293	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1294	s += ' device_type = "soclib:pic:root";\n'
1295	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1296	s += ' input_lines = <%d>;\n' % periph.channels
1297	s += ' };\n'
1298
1299	if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ):
1300	print '[genmap error] in netbsd_dts() : No XCU/PIC in cluster(%d,%d)' % (cluster.x, cluster.y)
1301	sys.exit(1)
1302
1303	if ( found_pic == True ): irq_tgt = pic
1304	else: irq_tgt = xcu
1305
1306	# get all others peripherals in cluster
1307	for periph in cluster.periphs:
1308	msb = periph.pseg.base >> 32
1309	lsb = periph.pseg.base & 0xFFFFFFFF
1310	size = periph.pseg.size
1311
1312	# research DMA component
1313	if ( periph.ptype == 'DMA' ):
1314
1315	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1316	s += ' device_type = "soclib:dma";\n'
1317	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1318	s += ' channel_count = <%d>;\n' % periph.channels
1319
1320	# multi-channels : get HWI index (to XCU) for each channel
1321	for channel in xrange( periph.channels ):
1322	hwi_id = 0xFFFFFFFF
1323	for irq in xcu.irqs:
1324	if ( (irq.isrtype == 'ISR_DMA') and (irq.channel == channel) ):
1325	hwi_id = irq.srcid
1326	if ( hwi_id == 0xFFFFFFFF ):
1327	print '[genmap error] in netbsd.dts() ISR_DMA channel %d not found' % channel
1328	sys.exit(1)
1329
1330	name = '%s@0x%x' % (xcu.pseg.name, xcu.pseg.base)
1331	s += ' irq@%d{\n' % channel
1332	s += ' device_type = "soclib:periph:irq";\n'
1333	s += ' output_line = <%d>;\n' % channel
1334	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1335	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1336	s += ' };\n'
1337
1338	s += ' };\n'
1339
1340	# research MMC component
1341	elif ( periph.ptype == 'MMC' ):
1342
1343	# get irq line index associated to MMC in XCU
1344	irq_in = 0xFFFFFFFF
1345	for irq in xcu.irqs:
1346	if ( irq.isrtype == 'ISR_MMC' ): irq_in = irq.srcid
1347	if ( irq_in == 0xFFFFFFFF ):
1348	print '[genmap error] in netbsd.dts() ISR_MMC not found'
1349	sys.exit(1)
1350
1351	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1352	s += ' device_type = "soclib:mmc";\n'
1353	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
1354	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1355	s += ' };\n'
1356
1357	# research FBF component
1358	elif ( periph.ptype == 'FBF' ):
1359
1360	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1361	s += ' device_type = "soclib:framebuffer";\n'
1362	s += ' mode = <32>;\n' # bits par pixel
1363	s += ' width = <%d>;\n' % periph.arg
1364	s += ' height = <%d>;\n' % periph.arg
1365	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1366	s += ' };\n'
1367
1368	# research IOC component
1369	elif ( periph.ptype == 'IOC' ):
1370
1371	if ( periph.subtype == 'BDV' ):
1372
1373	# get irq line index associated to bdv
1374	irq_in = 0xFFFFFFFF
1375	for irq in irq_tgt.irqs:
1376	if ( irq.isrtype == 'ISR_BDV' ): irq_in = irq.srcid
1377	if ( irq_in == 0xFFFFFFFF ):
1378	print '[genmap error] in netbsd.dts() ISR_BDV not found'
1379	sys.exit(1)
1380
1381	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1382	s += ' device_type = "soclib:blockdevice";\n'
1383	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
1384	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1385	s += ' };\n'
1386
1387	elif ( periph.subtype == 'HBA' ):
1388	print '[genmap error] in netbsd_dts() : HBA peripheral not supported by NetBSD'
1389	sys.exit(1)
1390
1391	elif ( periph.subtype == 'SPI' ):
1392
1393	# get irq line index associated to spi
1394	irq_in = 0xFFFFFFFF
1395	for irq in irq_tgt.irqs:
1396	if ( irq.isrtype == 'ISR_SPI' ): irq_in = irq.srcid
1397	if ( irq_in == 0xFFFFFFFF ):
1398	print '[genmap error] in netbsd.dts() ISR_SPI not found'
1399	sys.exit(1)
1400
1401	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1402	s += ' device_type = "soclib:spi";\n'
1403	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
1404	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1405	s += ' };\n'
1406
1407	# research ROM component
1408	elif ( periph.ptype == 'ROM' ):
1409
1410	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1411	s += ' device_type = "rom";\n'
1412	s += ' cached = <1>;\n'
1413	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1414	s += ' };\n'
1415
1416	# research SIM component
1417	elif ( periph.ptype == 'SIM' ):
1418
1419	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1420	s += ' device_type = "soclib:simhelper";\n'
1421	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1422	s += ' };\n'
1423
1424	# research TTY component
1425	elif ( periph.ptype == 'TTY' ):
1426
1427	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1428	s += ' device_type = "soclib:tty";\n'
1429	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1430	s += ' channel_count = < %d >;\n' % periph.channels
1431
1432	# multi-channels : get HWI index (to XCU or PIC) for each channel
1433	for channel in xrange( periph.channels ):
1434	hwi_id = 0xFFFFFFFF
1435	for irq in irq_tgt.irqs:
1436	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ):
1437	hwi_id = irq.srcid
1438	if ( hwi_id == 0xFFFFFFFF ):
1439	print '[genmap error] in netbsd.dts() ISR_TTY_RX channel %d not found' % channel
1440	sys.exit(1)
1441
1442	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1443	s += ' irq@%d{\n' % channel
1444	s += ' device_type = "soclib:periph:irq";\n'
1445	s += ' output_line = <%d>;\n' % channel
1446	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1447	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1448	s += ' };\n'
1449
1450	s += ' };\n'
1451
1452	# research IOB component
1453	elif ( periph.ptype == 'IOB' ):
1454
1455	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1456	s += ' device_type = "soclib:iob";\n'
1457	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1458	s += ' };\n'
1459
1460	# research NIC component
1461	elif ( periph.ptype == 'NIC' ):
1462
1463	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1464	s += ' device_type = "soclib:nic";\n'
1465	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1466	s += ' channel_count = < %d >;\n' % periph.channels
1467
1468	# multi-channels : get HWI index (to XCU or PIC) for RX & TX IRQs
1469	# RX IRQ : (2channel) / TX IRQs : (2channel + 1)
1470	for channel in xrange( periph.channels ):
1471	hwi_id = 0xFFFFFFFF
1472	for irq in irq_tgt.irqs:
1473	if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ):
1474	hwi_id = irq.srcid
1475	if ( hwi_id == 0xFFFFFFFF ):
1476	print '[genmap error] in netbsd.dts() ISR_NIC_RX channel %d not found' % channel
1477	sys.exit(1)
1478
1479	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1480	s += ' irq_rx@%d{\n' % channel
1481	s += ' device_type = "soclib:periph:irq";\n'
1482	s += ' output_line = <%d>;\n' % (2*channel)
1483	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1484	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1485	s += ' };\n'
1486
1487	hwi_id = 0xFFFFFFFF
1488	for irq in irq_tgt.irqs:
1489	if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ):
1490	hwi_id = irq.srcid
1491	if ( hwi_id == 0xFFFFFFFF ):
1492	print '[genmap error] in netbsd.dts() ISR_NIC_TX channel %d not found' % channel
1493	sys.exit(1)
1494
1495	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1496	s += ' irq_tx@%d{\n' % channel
1497	s += ' device_type = "soclib:periph:irq";\n'
1498	s += ' output_line = <%d>;\n' % (2*channel + 1)
1499	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1500	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1501	s += ' };\n'
1502
1503	s += ' };\n'
1504
1505	# research CMA component
1506	elif ( periph.ptype == 'CMA' ):
1507
1508	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1509	s += ' device_type = "soclib:cma";\n'
1510	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1511	s += ' channel_count = < %d >;\n' % periph.channels
1512
1513	# multi-channels : get HWI index (to XCU or PIC) for each channel
1514	for channel in xrange( periph.channels ):
1515	hwi_id = 0xFFFFFFFF
1516	for irq in irq_tgt.irqs:
1517	if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ):
1518	hwi_id = irq.srcid
1519	if ( hwi_id == 0xFFFFFFFF ):
1520	print '[genmap error] in netbsd.dts() ISR_CMA channel %d not found' % channel
1521	sys.exit(1)
1522
1523	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1524	s += ' irq@%d{\n' % channel
1525	s += ' device_type = "soclib:periph:irq";\n'
1526	s += ' output_line = <%d>;\n' % channel
1527	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1528	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1529	s += ' };\n'
1530
1531	s += ' };\n'
1532
1533	# research TIM component
1534	elif ( periph.ptype == 'TIM' ):
1535
1536	print '[genmap error] in netbsd_dts() : TIM peripheral not supported by NetBSD'
1537	sys.exit(1)
1538
1539	# research MWR component
1540	elif ( periph.ptype == 'MWR' ):
1541
1542	print '[genmap error] in netbsd_dts() : MWR peripheral not supported by NetBSD'
1543	sys.exit(1)
1544
1545	# research ICU component
1546	elif ( periph.ptype == 'ICU' ):
1547	print '[genmap error] in netbsd_dts() : ICU peripheral not supported by NetBSD'
1548	sys.exit(1)
1549
1550	# topology
1551	s += '\n'
1552	s += ' topology {\n'
1553	s += ' #address-cells = <2>;\n'
1554	s += ' #size-cells = <0>;\n'
1555	for cluster in self.clusters:
1556	s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y)
1557	s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y)
1558	s += ' devices = <\n'
1559
1560	offset = ((cluster.x << self.y_width) + cluster.y) << self.p_width
1561	for proc in cluster.procs:
1562	s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid)
1563	for periph in cluster.periphs:
1564	s += ' &{/%s@0x%x}\n' % (periph.pseg.name, periph.pseg.base)
1565
1566	s += ' >;\n'
1567	s += ' };\n'
1568	s += ' };\n'
1569	s += '};\n'
1570
1571	return s
1572	# end netbsd_dts( )
1573
1574	###########################
1575	def almos_archinfo( self ): # compute string for arch.info file generation,
1576	# used for almos configuration
1577	# header
1578	s = '# arch.info file generated by genmap for %s\n' % self.name
1579	s += '\n'
1580	s += '[HEADER]\n'
1581	s += ' REVISION=1\n'
1582	s += ' ARCH=%s\n' % self.name
1583	s += ' XMAX=%d\n' % self.x_size
1584	s += ' YMAX=%d\n' % self.y_size
1585	s += ' CPU_NR=%d\n' % self.procs_max
1586	s += '\n'
1587
1588	# clusters
1589	cluster_id = 0
1590	for cluster in self.clusters:
1591
1592	ram = None
1593	nb_cpus = len( cluster.procs )
1594	nb_devs = len( cluster.periphs )
1595	if ( len( cluster.coprocs ) != 0 ):
1596	print 'Error in almos_archinfo() coprocessors not supported yet'
1597	sys.exit(1)
1598
1599	# search a RAM
1600	for pseg in cluster.psegs:
1601	if ( pseg.segtype == 'RAM' ):
1602	ram = pseg
1603	nb_devs += 1
1604
1605	# search XCU to get IRQs indexes if cluster contains peripherals
1606	if ( len( cluster.periphs ) != 0 ):
1607	tty_irq_id = None
1608	bdv_irq_id = None
1609	dma_irq_id = None
1610
1611	for periph in cluster.periphs:
1612	if ( periph.ptype == 'XCU' ):
1613	# scan irqs
1614	for irq in periph.irqs:
1615	if ( irq.isrtype == 'ISR_TTY_RX' ) : tty_irq_id = irq.srcid
1616	if ( irq.isrtype == 'ISR_BDV' ) : bdv_irq_id = irq.srcid
1617	if ( irq.isrtype == 'ISR_DMA' ) : dma_irq_id = irq.srcid
1618
1619	# Build the cluster description
1620	s += '[CLUSTER]\n'
1621	s += ' CID=%d\n' % cluster_id
1622	s += ' ARCH_CID=0x%x\n' % ((cluster.x << self.y_width) + cluster.y)
1623	s += ' CPU_NR=%d\n' % nb_cpus
1624	s += ' DEV_NR=%d\n' % nb_devs
1625
1626
1627	# Handling RAM when cluster contain a RAM
1628	if (ram != None ):
1629	base = ram.base
1630	size = ram.size
1631	irqid = -1
1632	s += ' DEVID=RAM'
1633	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1634
1635	# Handling peripherals
1636	for periph in cluster.periphs:
1637	base = periph.pseg.base
1638	size = periph.pseg.size
1639
1640	if ( periph.ptype == 'XCU' ):
1641
1642	s += ' DEVID=XICU'
1643	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1644
1645	elif ( (periph.ptype == 'TTY')
1646	and (tty_irq_id != None) ):
1647
1648	s += ' DEVID=TTY'
1649	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, tty_irq_id )
1650
1651	elif ( (periph.ptype == 'DMA')
1652	and (dma_irq_id != None) ):
1653
1654	s += ' DEVID=DMA'
1655	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, dma_irq_id )
1656
1657	elif ( periph.ptype == 'FBF' ):
1658
1659	s += ' DEVID=FB'
1660	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1661
1662	elif ( (periph.ptype == 'IOC') and (periph.subtype == 'BDV')
1663	and (bdv_irq_id != None) ):
1664
1665	s += ' DEVID=BLKDEV'
1666	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, bdv_irq_id )
1667
1668	elif ( periph.ptype == 'PIC' ):
1669
1670	s += ' DEVID=IOPIC'
1671	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1672
1673	else:
1674	print '# Warning from almos_archinfo() in cluster[%d,%d]' \
1675	% (cluster.x, cluster.y)
1676	print '# peripheral type %s/%s not supported yet\n' \
1677	% ( periph.ptype, periph.subtype )
1678
1679	cluster_id += 1
1680
1681	return s
1682
1683	# end of almos_archinfo()
1684
1685
1686
1687
1688
1689
1690
1691
1692	###########################################################################################
1693	class Cluster ( object ):
1694	###########################################################################################
1695	def __init__( self,
1696	x,
1697	y ):
1698
1699	self.index = 0 # global index (set by Mapping constructor)
1700	self.x = x # x coordinate
1701	self.y = y # y coordinate
1702	self.psegs = [] # filled by addRam() or addPeriph()
1703	self.procs = [] # filled by addProc()
1704	self.coprocs = [] # filled by addCoproc()
1705	self.periphs = [] # filled by addPeriph()
1706
1707	return
1708
1709	################
1710	def xml( self ): # xml for a cluster
1711
1712	s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y)
1713	for pseg in self.psegs: s += pseg.xml()
1714	for proc in self.procs: s += proc.xml()
1715	for copr in self.coprocs: s += copr.xml()
1716	for peri in self.periphs: s += peri.xml()
1717	s += ' </cluster>\n'
1718
1719	return s
1720
1721	#############################################
1722	def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster
1723
1724	if ( verbose ):
1725	print '*** cbin for cluster [%d,%d]' % (self.x, self.y)
1726
1727	# check index
1728	if (self.index != expected):
1729	print '[genmap error] in Cluster.cbin() : cluster global index = %d / expected = %d' \
1730	% (self.index, expected )
1731	sys.exit(1)
1732
1733	# compute global index for first pseg
1734	if ( len(self.psegs) > 0 ):
1735	pseg_id = self.psegs[0].index
1736	else:
1737	pseg_id = 0
1738
1739	# compute global index for first proc
1740	if ( len(self.procs) > 0 ):
1741	proc_id = self.procs[0].index
1742	else:
1743	proc_id = 0
1744
1745	# compute global index for first coproc
1746	if ( len(self.coprocs) > 0 ):
1747	coproc_id = self.coprocs[0].index
1748	else:
1749	coproc_id = 0
1750
1751	# compute global index for first periph
1752	if ( len(self.periphs) > 0 ):
1753	periph_id = self.periphs[0].index
1754	else:
1755	periph_id = 0
1756
1757	byte_stream = bytearray()
1758	byte_stream += mapping.int2bytes( 4 , self.x ) # x coordinate
1759	byte_stream += mapping.int2bytes( 4 , self.y ) # x coordinate
1760	byte_stream += mapping.int2bytes( 4 , len( self.psegs ) ) # number of psegs in cluster
1761	byte_stream += mapping.int2bytes( 4 , pseg_id ) # first pseg global index
1762	byte_stream += mapping.int2bytes( 4 , len( self.procs ) ) # number of procs in cluster
1763	byte_stream += mapping.int2bytes( 4 , proc_id ) # first proc global index
1764	byte_stream += mapping.int2bytes( 4 , len( self.coprocs ) ) # number of coprocs in cluster
1765	byte_stream += mapping.int2bytes( 4 , coproc_id ) # first coproc global index
1766	byte_stream += mapping.int2bytes( 4 , len( self.periphs ) ) # number of periphs in cluster
1767	byte_stream += mapping.int2bytes( 4 , periph_id ) # first periph global index
1768
1769	if ( verbose ):
1770	print 'nb_psegs = %d' % len( self.psegs )
1771	print 'pseg_id = %d' % pseg_id
1772	print 'nb_procs = %d' % len( self.procs )
1773	print 'proc_id = %d' % proc_id
1774	print 'nb_coprocs = %d' % len( self.coprocs )
1775	print 'coproc_id = %d' % coproc_id
1776	print 'nb_periphs = %d' % len( self.periphs )
1777	print 'periph_id = %d' % periph_id
1778
1779	return byte_stream
1780
1781	###########################################################################################
1782	class Vspace( object ):
1783	###########################################################################################
1784	def __init__( self,
1785	name,
1786	startname ):
1787
1788	self.index = 0 # global index ( set by addVspace() )
1789	self.name = name # vspace name
1790	self.startname = startname # name of vobj containing the start_vector
1791	self.vsegs = []
1792	self.tasks = []
1793
1794	return
1795
1796	################
1797	def xml( self ): # xml for one vspace
1798
1799	s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname )
1800	for vseg in self.vsegs: s += vseg.xml()
1801	for task in self.tasks: s += task.xml()
1802	s += ' </vspace>\n'
1803
1804	return s
1805
1806	#############################################
1807	def cbin( self, mapping, verbose, expected ): # C binary structure for Vspace
1808
1809	if ( verbose ):
1810	print '*** cbin for vspace %s' % (self.name)
1811
1812	# check index
1813	if (self.index != expected):
1814	print '[genmap error] in Vspace.cbin() : vspace global index = %d / expected = %d' \
1815	% (self.index, expected )
1816	sys.exit(1)
1817
1818	# compute global index for vobj containing start_vector
1819	vobj_start_id = 0xFFFFFFFF
1820	for vseg in self.vsegs:
1821	if ( vseg.vobjs[0].name == self.startname ):
1822	vobj_start_id = vseg.vobjs[0].index
1823	if ( vobj_start_id == 0xFFFFFFFF ):
1824	print '[genmap error] in Vspace.cbin() : startname %s not found for vspace %s' \
1825	% ( self.startname, self.name )
1826	sys.exit(1)
1827
1828	# compute first vseg, vobj, task global index
1829	first_vseg_id = self.vsegs[0].index
1830	first_vobj_id = self.vsegs[0].vobjs[0].index
1831	first_task_id = self.tasks[0].index
1832
1833	# compute number of vobjs, tasks, vsegs
1834	nb_vsegs = len( self.vsegs )
1835	nb_tasks = len( self.tasks )
1836	nb_vobjs = 0
1837	for vseg in self.vsegs:
1838	nb_vobjs += len( vseg.vobjs )
1839
1840	byte_stream = bytearray()
1841	byte_stream += mapping.str2bytes( 32, self.name ) # vspace name
1842	byte_stream += mapping.int2bytes( 4, vobj_start_id ) # vobj start_vector
1843	byte_stream += mapping.int2bytes( 4, nb_vsegs ) # number of vsegs
1844	byte_stream += mapping.int2bytes( 4, nb_vobjs ) # number of vobjs
1845	byte_stream += mapping.int2bytes( 4, nb_tasks ) # number of tasks
1846	byte_stream += mapping.int2bytes( 4, first_vseg_id ) # first vseg global index
1847	byte_stream += mapping.int2bytes( 4, first_vobj_id ) # first vobj global index
1848	byte_stream += mapping.int2bytes( 4, first_task_id ) # first task global index
1849
1850	if ( verbose ):
1851	print 'start_id = %d' % vobj_start_id
1852	print 'nb_vsegs = %d' % nb_vsegs
1853	print 'nb_vobjs = %d' % nb_vobjs
1854	print 'nb_tasks = %d' % nb_tasks
1855	print 'vseg_id = %d' % first_vseg_id
1856	print 'vobj_id = %d' % first_vobj_id
1857	print 'task_id = %d' % first_task_id
1858
1859	return byte_stream
1860
1861	###########################################################################################
1862	class Task( object ):
1863	###########################################################################################
1864	def __init__( self,
1865	name,
1866	trdid,
1867	x,
1868	y,
1869	p,
1870	stackname,
1871	heapname,
1872	startid,
1873	usetty = False,
1874	usenic = False,
1875	usecma = False,
1876	usehba = False,
1877	usetim = False ):
1878
1879	self.index = 0 # global index value set by addTask()
1880	self.name = name # tsk name
1881	self.trdid = trdid # task index (unique in vspace)
1882	self.x = x # cluster x coordinate
1883	self.y = y # cluster y coordinate
1884	self.p = p # processor local index
1885	self.stackname = stackname # name of vobj containing the stack
1886	self.heapname = heapname # name of vobj containing the heap
1887	self.startid = startid # index in start_vector
1888	self.usetty = usetty # request a private TTY channel
1889	self.usenic = usenic # request a private NIC channel
1890	self.usecma = usecma # request a private CMA channel
1891	self.usehba = usehba # request a private HBA channel
1892	self.usetim = usetim # request a private TIM channel
1893	return
1894
1895	################
1896	def xml( self ): # xml for one task
1897
1898	s = ' <task name="%s"' % self.name
1899	s += ' trdid="%d"' % self.trdid
1900	s += ' x="%d"' % self.x
1901	s += ' y="%d"' % self.y
1902	s += ' p="%d"' % self.p
1903	s += ' stackname="%s"' % self.stackname
1904	s += ' heapname="%s"' % self.heapname
1905	s += ' startid="%d"' % self.startid
1906	if self.usetty != 0: s += ' usetty="1"'
1907	if self.usenic != 0: s += ' usenic="1"'
1908	if self.usecma != 0: s += ' usehba="1"'
1909	if self.usehba != 0: s += ' usehba="1"'
1910	if self.usetim != 0: s += ' usehba="1"'
1911	s += ' />\n'
1912
1913	return s
1914
1915	#####################################################
1916	def cbin( self, mapping, verbose, expected, vspace ): # C binary data structure for Task
1917
1918	if ( verbose ):
1919	print '*** cbin for task %s in vspace %s' % (self.name, vspace.name)
1920
1921	# check index
1922	if (self.index != expected):
1923	print '[genmap error] in Task.cbin() : task global index = %d / expected = %d' \
1924	% (self.index, expected )
1925	sys.exit(1)
1926
1927	# compute cluster global index
1928	cluster_id = (self.x * mapping.y_size) + self.y
1929
1930	# compute vobj local index for stack
1931	vobj_stack_id = 0xFFFFFFFF
1932	for vseg in vspace.vsegs:
1933	if ( vseg.vobjs[0].name == self.stackname ):
1934	vobj_stack_id = vseg.vobjs[0].index
1935	if ( vobj_stack_id == 0xFFFFFFFF ):
1936	print '[genmap error] in Task.cbin() : stackname %s not found for task %s in vspace %s' \
1937	% ( self.stackname, self.name, vspace.name )
1938	sys.exit(1)
1939
1940	# compute vobj local index for heap
1941	vobj_heap_id = 0xFFFFFFFF
1942	for vseg in vspace.vsegs:
1943	if ( vseg.vobjs[0].name == self.heapname ):
1944	vobj_heap_id = vseg.vobjs[0].index
1945	if ( vobj_heap_id == 0xFFFFFFFF ):
1946	print '[genmap error] in Task.cbin() : heapname %s not found for task %s in vspace %s' \
1947	% ( self.heapname, self.name, vspace.name )
1948	sys.exit(1)
1949
1950	byte_stream = bytearray()
1951	byte_stream += mapping.str2bytes( 32, self.name ) # task name in vspace
1952	byte_stream += mapping.int2bytes( 4, cluster_id ) # cluster global index
1953	byte_stream += mapping.int2bytes( 4, self.p ) # processor local index in cluster
1954	byte_stream += mapping.int2bytes( 4, self.trdid ) # thread local index in vspace
1955	byte_stream += mapping.int2bytes( 4, vobj_stack_id ) # stack vobj local index
1956	byte_stream += mapping.int2bytes( 4, vobj_heap_id ) # heap vobj local index
1957	byte_stream += mapping.int2bytes( 4, self.startid ) # index in start vector
1958	byte_stream += mapping.int2bytes( 4, self.usetty ) # TTY channel required
1959	byte_stream += mapping.int2bytes( 4, self.usenic ) # NIC channel required
1960	byte_stream += mapping.int2bytes( 4, self.usecma ) # CMA channel required
1961	byte_stream += mapping.int2bytes( 4, self.usehba ) # IOC channel required
1962	byte_stream += mapping.int2bytes( 4, self.usetim ) # TIM channel required
1963
1964	if ( verbose ):
1965	print 'clusterid = %d' % cluster_id
1966	print 'lpid = %d' % self.p
1967	print 'trdid = %d' % self.trdid
1968	print 'stackid = %d' % vobj_stack_id
1969	print 'heapid = %d' % vobj_heap_id
1970	print 'startid = %d' % self.startid
1971
1972	return byte_stream
1973
1974	###########################################################################################
1975	class Vseg( object ):
1976	###########################################################################################
1977	def __init__( self,
1978	name,
1979	vbase,
1980	mode,
1981	x,
1982	y,
1983	psegname,
1984	identity = False,
1985	local = False ):
1986
1987	assert mode in VSEGMODES
1988
1989	self.index = 0 # global index ( set by addVseg() )
1990	self.name = name # vseg name
1991	self.vbase = vbase & 0xFFFFFFFF # virtual base address in vspace
1992	self.mode = mode # CXWU access rights
1993	self.x = x # x coordinate of destination cluster
1994	self.y = y # y coordinate of destination cluster
1995	self.psegname = psegname # name of pseg in destination cluster
1996	self.identity = identity # identity mapping required
1997	self.local = local # one copy per cluster
1998	self.vobjs = []
1999	return
2000
2001	################
2002	def xml( self ): # xml for one vseg
2003
2004	s = ' <vseg name="%s" vbase="0x%x" mode="%s" x="%d" y="%d" psegname="%s"' \
2005	% ( self.name, self.vbase, self.mode, self.x, self.y, self.psegname )
2006	if ( self.identity ): s += ' ident="1"'
2007	if ( self.local ): s += ' local="1"'
2008	s += ' >\n'
2009	for vobj in self.vobjs: s += vobj.xml()
2010	s += ' </vseg>\n'
2011
2012	return s
2013
2014	#############################################
2015	def cbin( self, mapping, verbose, expected ): # C binary structure for Vseg
2016
2017	if ( verbose ):
2018	print '*** cbin for vseg[%d] %s' % (self.index, self.name)
2019
2020	# check index
2021	if (self.index != expected):
2022	print '[genmap error] in Vseg.cbin() : vseg global index = %d / expected = %d' \
2023	% (self.index, expected )
2024	sys.exit(1)
2025
2026	# compute pseg_id
2027	pseg_id = 0xFFFFFFFF
2028	cluster_id = (self.x * mapping.y_size) + self.y
2029	cluster = mapping.clusters[cluster_id]
2030	for pseg in cluster.psegs:
2031	if (self.psegname == pseg.name):
2032	pseg_id = pseg.index
2033	if (pseg_id == 0xFFFFFFFF):
2034	print '[genmap error] in Vseg.cbin() : psegname %s not found for vseg %s in cluster %d' \
2035	% ( self.psegname, self.name, cluster_id )
2036	sys.exit(1)
2037
2038	# compute numerical value for mode
2039	mode_id = 0xFFFFFFFF
2040	for x in xrange( len(VSEGMODES) ):
2041	if ( self.mode == VSEGMODES[x] ):
2042	mode_id = x
2043	if ( mode_id == 0xFFFFFFFF ):
2044	print '[genmap error] in Vseg.cbin() : undefined vseg mode %s' % self.mode
2045	sys.exit(1)
2046
2047	# compute vobj_id
2048	vobj_id = self.vobjs[0].index
2049
2050	byte_stream = bytearray()
2051	byte_stream += mapping.str2bytes( 32, self.name ) # vseg name
2052	byte_stream += mapping.int2bytes( 4, self.vbase ) # virtual base address
2053	byte_stream += mapping.int2bytes( 8, 0 ) # physical base address
2054	byte_stream += mapping.int2bytes( 4, 0 ) # vseg size (bytes)
2055	byte_stream += mapping.int2bytes( 4, pseg_id ) # physical segment global index
2056	byte_stream += mapping.int2bytes( 4, mode_id ) # CXWU flags
2057	byte_stream += mapping.int2bytes( 4, len(self.vobjs) ) # number of vobjs in vseg
2058	byte_stream += mapping.int2bytes( 4, vobj_id ) # first vobj global index
2059	byte_stream += mapping.int2bytes( 4, 0 ) # linked list of vsegs on same pseg
2060	byte_stream += mapping.int2bytes( 1, 0 ) # mapped when non zero
2061	byte_stream += mapping.int2bytes( 1, self.identity ) # identity mapping when non zero
2062	byte_stream += mapping.int2bytes( 1, self.local ) # non shared if non zero
2063	byte_stream += mapping.int2bytes( 1, 0 ) # reserved (padding)
2064
2065	if ( verbose ):
2066	print 'vbase = %x' % self.vbase
2067	print 'pseg_id = %d' % pseg_id
2068	print 'mode = %s' % self.mode
2069	print 'nb_vobjs = %d' % len(self.vobjs)
2070	print 'vobj_id = %d' % vobj_id
2071
2072	return byte_stream
2073
2074	###########################################################################################
2075	class Vobj( object ):
2076	###########################################################################################
2077	def __init__( self,
2078	name,
2079	length,
2080	vtype,
2081	binpath = '',
2082	align = 0,
2083	init = 0 ):
2084
2085	assert vtype in ['ELF','BLOB','PTAB','PERI','MWMR','LOCK', \
2086	'BUFFER','BARRIER','CONST','MEMSPACE','SCHED']
2087
2088	assert (vtype != 'ELF') or (binpath != '')
2089
2090	self.index = 0 # global index ( set by addVobj() )
2091	self.name = name # vobj name (unique in vspace)
2092	self.vtype = vtype # vobj type (defined in mapping_info.h)
2093	self.length = length # vobj size (bytes)
2094	self.binpath = binpath # pathname for (ELF type)
2095	self.align = align # required alignment (logarithm of 2)
2096	self.init = init # initialisation value (for BARRIER or MWMR types)
2097
2098	return
2099
2100	################
2101	def xml( self ): # xml for a vobj
2102
2103	s = ' <vobj name="%s" type="%s" length="0x%x"' \
2104	% ( self.name, self.vtype, self.length )
2105	if (self.binpath != ''): s += ' binpath="%s"' % (self.binpath)
2106	if (self.align != 0 ): s += ' align="%d"' % (self.align)
2107	if (self.init != 0 ): s += ' init="%d"' % (self.init)
2108	s += ' />\n'
2109
2110	return s
2111
2112	#############################################
2113	def cbin( self, mapping, verbose, expected ): # C binary structure for Vobj
2114
2115	# check index
2116	if (self.index != expected):
2117	print '[genmap error] in Vobj.cbin() : vobj global index = %d / expected = %d' \
2118	% (self.index, expected )
2119	sys.exit(1)
2120	elif ( verbose ):
2121	print '*** cbin for vobj[%d] %s' % (self.index, self.name)
2122
2123	# compute numerical value for vtype
2124	vtype_int = 0xFFFFFFFF
2125	for x in xrange( len(VOBJTYPES) ):
2126	if ( self.vtype == VOBJTYPES[x] ):
2127	vtype_int = x
2128	if ( vtype_int == 0xFFFFFFFF ):
2129	print '[genmap error] in Vobj.cbin() : undefined vobj type %s' % self.vtype
2130	sys.exit(1)
2131
2132	byte_stream = bytearray()
2133	byte_stream += mapping.str2bytes( 32, self.name ) # vobj name
2134	byte_stream += mapping.str2bytes( 64, self.binpath ) # pathname for .elf file
2135	byte_stream += mapping.int2bytes( 4 , vtype_int ) # vobj type
2136	byte_stream += mapping.int2bytes( 4 , self.length ) # vobj size
2137	byte_stream += mapping.int2bytes( 4 , self.align ) # required alignment
2138	byte_stream += mapping.int2bytes( 4 , 0 ) # virtual base address
2139	byte_stream += mapping.int2bytes( 8 , 0 ) # physical base address
2140	byte_stream += mapping.int2bytes( 4 , self.init ) # init value
2141
2142	if ( verbose ):
2143	print 'binpath = %s' % self.binpath
2144	print 'type = %s' % self.vtype
2145	print 'length = %x' % self.length
2146
2147	return byte_stream
2148
2149	###########################################################################################
2150	class Processor ( object ):
2151	###########################################################################################
2152	def __init__( self,
2153	x,
2154	y,
2155	lpid ):
2156
2157	self.index = 0 # global index ( set by addProc() )
2158	self.x = x # x cluster coordinate
2159	self.y = y # y cluster coordinate
2160	self.lpid = lpid # processor local index
2161
2162	return
2163
2164	################
2165	def xml( self ): # xml for a processor
2166	return ' <proc index="%d" />\n' % (self.lpid)
2167
2168	#############################################
2169	def cbin( self, mapping, verbose, expected ): # C binary structure for Proc
2170
2171	if ( verbose ):
2172	print '*** cbin for proc %d in cluster (%d,%d)' % (self.lpid, self.x, self.y)
2173
2174	# check index
2175	if (self.index != expected):
2176	print '[genmap error] in Proc.cbin() : proc global index = %d / expected = %d' \
2177	% (self.index, expected )
2178	sys.exit(1)
2179
2180	byte_stream = bytearray()
2181	byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index
2182
2183	return byte_stream
2184
2185	###########################################################################################
2186	class Pseg ( object ):
2187	###########################################################################################
2188	def __init__( self,
2189	name,
2190	base,
2191	size,
2192	x,
2193	y,
2194	segtype ):
2195
2196	assert( segtype in PSEGTYPES )
2197
2198	self.index = 0 # global index ( set by addPseg() )
2199	self.name = name # pseg name (unique in cluster)
2200	self.base = base # physical base address
2201	self.size = size # segment size (bytes)
2202	self.x = x # cluster x coordinate
2203	self.y = y # cluster y coordinate
2204	self.segtype = segtype # RAM / PERI (defined in mapping_info.h)
2205
2206	return
2207
2208	################
2209	def xml( self ): # xml for a pseg
2210
2211	return ' <pseg name="%s" type="%s" base="0x%x" length="0x%x" />\n' \
2212	% (self.name, self.segtype, self.base, self.size)
2213
2214	######################################################
2215	def cbin( self, mapping, verbose, expected, cluster ): # C binary structure for Pseg
2216
2217	if ( verbose ):
2218	print '*** cbin for pseg[%d] %s in cluster[%d,%d]' \
2219	% (self.index, self.name, cluster.x, cluster.y)
2220
2221	# check index
2222	if (self.index != expected):
2223	print '[genmap error] in Pseg.cbin() : pseg global index = %d / expected = %d' \
2224	% (self.index, expected )
2225	sys.exit(1)
2226
2227	# compute numerical value for segtype
2228	segtype_int = 0xFFFFFFFF
2229	for x in xrange( len(PSEGTYPES) ):
2230	if ( self.segtype == PSEGTYPES[x] ):
2231	segtype_int = x
2232	if ( segtype_int == 0xFFFFFFFF ):
2233	print '[genmap error] in Pseg.cbin() : undefined segment type %s' % self.segtype
2234	sys.exit(1)
2235
2236	byte_stream = bytearray()
2237	byte_stream += mapping.str2bytes( 32, self.name ) # pseg name
2238	byte_stream += mapping.int2bytes( 8 , self.base ) # physical base address
2239	byte_stream += mapping.int2bytes( 8 , self.size ) # segment length
2240	byte_stream += mapping.int2bytes( 4 , segtype_int ) # segment type
2241	byte_stream += mapping.int2bytes( 4 , cluster.index ) # cluster global index
2242	byte_stream += mapping.int2bytes( 4 , 0 ) # linked list of vsegs
2243
2244	if ( verbose ):
2245	print 'pbase = %x' % self.base
2246	print 'size = %x' % self.size
2247	print 'type = %s' % self.segtype
2248
2249	return byte_stream
2250
2251	###########################################################################################
2252	class Periph ( object ):
2253	###########################################################################################
2254	def __init__( self,
2255	pseg, # associated pseg
2256	ptype, # peripheral type
2257	subtype = 'NONE', # peripheral subtype
2258	channels = 1, # for multi-channels peripherals
2259	arg = 0 ): # optional argument (semantic depends on ptype)
2260
2261	assert ptype in PERIPHTYPES
2262
2263	assert subtype in PERIPHSUBTYPES
2264
2265	self.index = 0 # global index ( set by addPeriph() )
2266	self.channels = channels
2267	self.ptype = ptype
2268	self.subtype = subtype
2269	self.arg = arg
2270	self.pseg = pseg
2271	self.irqs = []
2272	return
2273
2274	################
2275	def xml( self ): # xml for a periph
2276
2277	s = ' <periph type="%s"' % self.ptype
2278	s += ' subtype="%s"' % self.subtype
2279	s += ' psegname="%s"' % self.pseg.name
2280	s += ' channels="%d"' % self.channels
2281	s += ' arg="%d" >\n' % self.arg
2282	if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') or (self.ptype == 'ICU') ):
2283	for irq in self.irqs: s += irq.xml()
2284	s += ' </periph>\n'
2285
2286	return s
2287
2288	#############################################
2289	def cbin( self, mapping, verbose, expected ): # C binary structure for Periph
2290
2291	if ( verbose ):
2292	print '*** cbin for periph %s in cluster [%d,%d]' \
2293	% (self.ptype, self.pseg.x, self.pseg.y)
2294
2295	# check index
2296	if (self.index != expected):
2297	print '[genmap error] in Periph.cbin() : periph global index = %d / expected = %d' \
2298	% (self.index, expected )
2299	sys.exit(1)
2300
2301	# compute pseg global index
2302	pseg_id = self.pseg.index
2303
2304	# compute first irq global index
2305	if ( len(self.irqs) > 0 ):
2306	irq_id = self.irqs[0].index
2307	else:
2308	irq_id = 0
2309
2310	# compute numerical value for ptype
2311	ptype_id = 0xFFFFFFFF
2312	for x in xrange( len(PERIPHTYPES) ):
2313	if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x
2314	if ( ptype_id == 0xFFFFFFFF ):
2315	print '[genmap error] in Periph.cbin() : undefined peripheral type %s' % self.ptype
2316	sys.exit(1)
2317
2318	# compute numerical value for subtype
2319	subtype_id = 0xFFFFFFFF
2320	for x in xrange( len(PERIPHSUBTYPES) ):
2321	if ( self.subtype == PERIPHSUBTYPES[x] ): subtype_id = x
2322
2323	# compute
2324	byte_stream = bytearray()
2325	byte_stream += mapping.int2bytes( 4 , ptype_id ) # peripheral type
2326	byte_stream += mapping.int2bytes( 4 , subtype_id ) # peripheral subtype
2327	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
2328	byte_stream += mapping.int2bytes( 4 , self.channels ) # number of channels
2329	byte_stream += mapping.int2bytes( 4 , self.arg ) # optionnal argument
2330	byte_stream += mapping.int2bytes( 4 , len( self.irqs ) ) # number of input irqs
2331	byte_stream += mapping.int2bytes( 4 , irq_id ) # first irq global index
2332
2333	if ( verbose ):
2334	print 'ptype = %d' % ptype_id
2335	print 'pseg_id = %d' % pseg_id
2336	print 'nb_irqs = %d' % len( self.irqs )
2337	print 'irq_id = %d' % irq_id
2338	return byte_stream
2339
2340	###########################################################################################
2341	class Irq ( object ):
2342	###########################################################################################
2343	def __init__( self,
2344	irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only)
2345	srcid, # input IRQ index (for XCU or PIC)
2346	isrtype, # Type of ISR to be executed
2347	channel = 0 ): # channel index for multi-channel ISR
2348
2349	assert irqtype in IRQTYPES
2350	assert isrtype in ISRTYPES
2351	assert srcid < 32
2352
2353	self.index = 0 # global index ( set by addIrq() )
2354	self.irqtype = irqtype # IRQ type
2355	self.srcid = srcid # source IRQ index
2356	self.isrtype = isrtype # ISR type
2357	self.channel = channel # channel index (for multi-channels ISR)
2358	return
2359
2360	################
2361	def xml( self ): # xml for Irq
2362
2363	return ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" />\n' \
2364	% ( self.irqtype, self.srcid, self.isrtype, self.channel )
2365
2366	#############################################
2367	def cbin( self, mapping, verbose, expected ): # C binary structure for Irq
2368
2369	if ( verbose ):
2370	print '*** cbin for irq[%d]' % (self.index)
2371
2372	# check index
2373	if (self.index != expected):
2374	print '[genmap error] in Irq.cbin() : irq global index = %d / expected = %d' \
2375	% (self.index, expected )
2376	sys.exit(1)
2377
2378	# compute numerical value for irqtype
2379	irqtype_id = 0xFFFFFFFF
2380	for x in xrange( len(IRQTYPES) ):
2381	if ( self.irqtype == IRQTYPES[x] ):
2382	irqtype_id = x
2383	if ( irqtype_id == 0xFFFFFFFF ):
2384	print '[genmap error] in Irq.cbin() : undefined irqtype %s' % self.irqtype
2385	sys.exit(1)
2386
2387	# compute numerical value for isrtype
2388	isrtype_id = 0xFFFFFFFF
2389	for x in xrange( len(ISRTYPES) ):
2390	if ( self.isrtype == ISRTYPES[x] ):
2391	isrtype_id = x
2392	if ( isrtype_id == 0xFFFFFFFF ):
2393	print '[genmap error] in Irq.cbin() : undefined isrtype %s' % self.isrtype
2394	sys.exit(1)
2395
2396	byte_stream = bytearray()
2397	byte_stream += mapping.int2bytes( 4, irqtype_id )
2398	byte_stream += mapping.int2bytes( 4, self.srcid )
2399	byte_stream += mapping.int2bytes( 4, isrtype_id )
2400	byte_stream += mapping.int2bytes( 4, self.channel )
2401	byte_stream += mapping.int2bytes( 4, 0 )
2402	byte_stream += mapping.int2bytes( 4, 0 )
2403
2404	if ( verbose ):
2405	print 'irqtype = %s' % self.irqtype
2406	print 'srcid = %d' % self.srcid
2407	print 'isrtype = %s' % self.isrtype
2408	print 'channel = %d' % self.channel
2409
2410	return byte_stream
2411
2412	###########################################################################################
2413	class Coproc ( object ):
2414	###########################################################################################
2415	def __init__( self,
2416	pseg ): # associated pseg
2417
2418	self.index = 0 # global index value set by addCoproc()
2419	self.pseg = pseg
2420	self.ports = []
2421
2422	return
2423
2424	################
2425	def xml( self ): # xml for Coproc
2426
2427	print '[genmap error] in Coproc.xml() : not defined yet'
2428	sys.exit(1)
2429
2430	return
2431
2432	#############################################
2433	def cbin( self, mapping, verbose, expected ): # C binary structure for Coproc
2434
2435	if ( verbose ):
2436	print '*** cbin for coproc in cluster (%d,%d)' % (self.pseg.x, self.pseg.y)
2437
2438	# check index
2439	if (self.index != expected):
2440	print '[genmap error] in Coproc.cbin() : coproc global index = %d / expected = %d' \
2441	% (self.index, expected )
2442	sys.exit(1)
2443
2444	# compute pseg global index
2445	pseg_id = self.pseg.index
2446
2447	# compute first port global index
2448	port_id = self.ports[0].index
2449
2450	byte_stream = bytearray()
2451	byte_stream += mapping.str2bytes( 32, self.pseg.name ) # probablement inutile (AG)
2452	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
2453	byte_stream += mapping.int2bytes( 4 , len( self.ports ) ) # number of input irqs
2454	byte_stream += mapping.int2bytes( 4 , port_id ) # first port global index
2455
2456	if ( verbose ):
2457	print 'irqtype = %s' % self.irqtype
2458	print 'pseg_id = %d' % pseg_id
2459	print 'nb_ports = %d' % len( self.ports )
2460	print 'port_id %d' % port_id
2461
2462	return byte_stream
2463
2464	###########################################################################################
2465	class Cpport ( object ):
2466	###########################################################################################
2467	def __init__( self,
2468	direction,
2469	vspacename,
2470	mwmrname ):
2471
2472	self.index = 0 # global index ( set by addCpport() )
2473	self.direction = direction # TO_COPROC / FROM_COPROC
2474	self.vspacename = vspacename # name of vspace containing mwmr channel
2475	self.mwmrname = mwmrname # name of vobj defining mwmr channel
2476
2477	return
2478
2479	################
2480	def xml( self ): # xml for Cpport
2481
2482	print '[genmap error] in Cpport.xml() : not defined yet'
2483	sys.exit(1)
2484
2485	return
2486
2487	#############################################
2488	def cbin( self, mapping, verbose, expected ): # C binary structure for Cpport
2489
2490	if ( verbose ):
2491	print '*** cbin for cpport[%d]' % (self.index)
2492
2493	# check index
2494	if ( self.index != expected ):
2495	print '[genmap error] in Cpport.cbin() : port global index = %d / expected = %d' \
2496	% ( self.index, expected )
2497	sys.exit(1)
2498
2499	# compute numerical value for direction
2500	if ( self.direction == 'TO_COPROC' ):
2501	dir_int = 0
2502	else:
2503	dir_int = 1
2504
2505	# compute vspace global index
2506	vspace_id = 0xFFFFFFFF
2507	for vspace in mapping.vspaces:
2508	if ( self.vspacename == vspace.name ):
2509	vspace_id = vspace.index
2510	if (vspace_id == 0xFFFFFFFF):
2511	print '[genmap error] in Cpport.cbin() : vspace name %s not found' \
2512	% ( self.vspacename )
2513	sys.exit(1)
2514
2515	# compute mwmr global index
2516	mwmr_id = 0xFFFFFFFF
2517	for vseg in mapping.vspace[vspace_id].vsegs:
2518	for vobj in vseg.vobjs:
2519	if (self.mwmrname == vobj.name):
2520	mwmr_id = vobj.index
2521	if (mwmr_id == 0xFFFFFFFF):
2522	print '[genmap error] in Cpport.cbin() : mwmr vobj name %s not found in vspace %s' \
2523	% ( self.mwmrname, self.vspacename )
2524	sys.exit(1)
2525
2526	byte_stream = bytearray()
2527	byte_stream += mapping.int2bytes( 4 , dir_int ) # pseg global index
2528	byte_stream += mapping.int2bytes( 4 , vspace_id ) # vspace global index
2529	byte_stream += mapping.int2bytes( 4 , mwmr_id ) # mwmr vobj global index
2530
2531	if ( verbose ):
2532	print 'direction = %s' % self.direction
2533	print 'vspace_id = %d' % vspace_id
2534	print 'mwmr_id = %d' % mwmr_id
2535
2536	return byte_stream
2537
2538
2539	# Local Variables:
2540	# tab-width: 4;
2541	# c-basic-offset: 4;
2542	# c-file-offsets:((innamespace . 0)(inline-open . 0));
2543	# indent-tabs-mode: nil;
2544	# End:
2545	#
2546	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
2547

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