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source: soft/giet_vm/giet_python/mapping.py @ 548

Last change on this file since 548 was 546, checked in by alain, 10 years ago
Replace the "SPI" name by "SDC" for the third disk controller type (beside BDV and HBA).
Property svn:executable set to ``*
File size: 100.0 KB

Line
1	#!/usr/bin/env python
2
3	import sys
4
5	###################################################################################
6	# file : giet_mapping.py
7	# date : april 2014
8	# author : Alain Greiner
9	###################################################################################
10	# This file contains the classes required to define a mapping for the GIET_VM.
11	# - A 'Mapping' contains a set of 'Cluster' (hardware architecture)
12	# a set of 'Vseg' (kernel glogals virtual segments)
13	# a set of 'Vspace' (one or several user applications)
14	# - A 'Cluster' contains a set of 'Pseg' (physical segments in cluster)
15	# a set of 'Proc' (processors in cluster)
16	# a set of 'Periph' (peripherals in cluster)
17	# - A 'Vspace' contains a set of 'Vseg' (user virtual segments)
18	# a set of 'Task' (user parallel tasks)
19	# - A 'Periph' contains a set of 'Irq' (only for XCU and PIC types )
20	###################################################################################
21	# Implementation Note
22	# The objects used to describe a mapping are distributed in the PYTHON structure:
23	# For example the psegs set is split in several subsets (one subset per cluster),
24	# or the tasks set is split in several subsets (one subset per vspace), etc...
25	# In the C binary data structure used by the giet_vm, all objects of same type
26	# are stored in a linear array (one single array for all psegs for example).
27	# For all objects, we compute and store in the PYTHON object a "global index"
28	# corresponding to the index in this global array, and this index can be used as
29	# a pseudo-pointer to identify a specific object of a given type.
30	###################################################################################
31
32	###################################################################################
33	# Various constants
34	###################################################################################
35
36	PADDR_WIDTH = 40 # number of bits for physical address
37	X_WIDTH = 4 # number of bits encoding x coordinate
38	Y_WIDTH = 4 # number of bits encoding y coordinate
39	P_WIDTH = 4 # number of bits encoding local proc_id
40	VPN_ANTI_MASK = 0x00000FFF # mask vaddr to get offset in small page
41	BPN_MASK = 0xFFE00000 # mask vaddr to get the BPN in big page
42	PERI_INCREMENT = 0x10000 # virtual address increment for replicated vsegs
43	RESET_ADDRESS = 0xBFC00000 # Processor wired boot_address
44	MAPPING_SIGNATURE = 0xDACE2014 # Magic number indicating a valid C BLOB
45
46	###################################################################################
47	# These lists must be consistent with values defined in
48	# mapping_info.h / xml_driver.c /xml_parser.c
49	###################################################################################
50	PERIPHTYPES = [
51	'CMA',
52	'DMA',
53	'FBF',
54	'IOB',
55	'IOC',
56	'MMC',
57	'MWR',
58	'NIC',
59	'ROM',
60	'SIM',
61	'TIM',
62	'TTY',
63	'XCU',
64	'PIC',
65	'DROM',
66	]
67
68	IOCSUBTYPES = [
69	'BDV',
70	'HBA',
71	'SDC',
72	]
73
74	MWRSUBTYPES = [
75	'GCD',
76	'DCT',
77	]
78
79	###################################################################################
80	# These lists must be consistent with values defined in
81	# irq_handler.c / irq_handler.h / xml_driver.c / xml_parser.c
82	###################################################################################
83	IRQTYPES = [
84	'HWI',
85	'WTI',
86	'PTI',
87	]
88
89	ISRTYPES = [
90	'ISR_DEFAULT',
91	'ISR_TICK',
92	'ISR_TTY_RX',
93	'ISR_TTY_TX',
94	'ISR_BDV',
95	'ISR_TIMER',
96	'ISR_WAKUP',
97	'ISR_NIC_RX',
98	'ISR_NIC_TX',
99	'ISR_CMA',
100	'ISR_MMC',
101	'ISR_DMA',
102	'ISR_SDC',
103	'ISR_MWR',
104	'ISR_HBA',
105	]
106
107	VSEGTYPES = [
108	'ELF',
109	'BLOB',
110	'PTAB',
111	'PERI',
112	'BUFFER',
113	'SCHED',
114	'HEAP',
115	]
116
117	VSEGMODES = [
118	'____',
119	'___U',
120	'__W_',
121	'__WU',
122	'_X__',
123	'_X_U',
124	'_XW_',
125	'_XWU',
126	'C___',
127	'C__U',
128	'C_W_',
129	'C_WU',
130	'CX__',
131	'CX_U',
132	'CXW_',
133	'CXWU',
134	]
135
136	PSEGTYPES = [
137	'RAM',
138	'PERI',
139	]
140
141	###################################################################################
142	class Mapping( object ):
143	###################################################################################
144	def __init__( self,
145	name, # mapping name
146	x_size, # number of clusters in a row
147	y_size, # number of clusters in a column
148	nprocs, # max number of processors per cluster
149	x_width = X_WIDTH, # number of bits encoding x coordinate
150	y_width = Y_WIDTH, # number of bits encoding y coordinate
151	p_width = P_WIDTH, # number of bits encoding lpid
152	paddr_width = PADDR_WIDTH, # number of bits for physical address
153	coherence = 1, # hardware cache coherence if non-zero
154	irq_per_proc = 1, # number or IRQs from XCU to processor
155	use_ramdisk = False, # use ramdisk when true
156	x_io = 0, # cluster_io x coordinate
157	y_io = 0, # cluster_io y coordinate
158	peri_increment = PERI_INCREMENT, # address increment for globals
159	reset_address = RESET_ADDRESS, # Processor wired boot_address
160	ram_base = 0, # RAM physical base in cluster[0,0]
161	ram_size = 0 ): # RAM size per cluster (bytes)
162
163	assert ( x_size <= (1<<X_WIDTH) )
164	assert ( y_size <= (1<<Y_WIDTH) )
165	assert ( nprocs <= (1<<P_WIDTH) )
166
167	self.signature = MAPPING_SIGNATURE
168	self.name = name
169	self.name = name
170	self.paddr_width = paddr_width
171	self.coherence = coherence
172	self.x_size = x_size
173	self.y_size = y_size
174	self.nprocs = nprocs
175	self.x_width = x_width
176	self.y_width = y_width
177	self.p_width = p_width
178	self.irq_per_proc = irq_per_proc
179	self.use_ramdisk = use_ramdisk
180	self.x_io = x_io
181	self.y_io = y_io
182	self.peri_increment = peri_increment
183	self.reset_address = reset_address
184	self.ram_base = ram_base
185	self.ram_size = ram_size
186
187	self.total_vspaces = 0
188	self.total_globals = 0
189	self.total_psegs = 0
190	self.total_vsegs = 0
191	self.total_tasks = 0
192	self.total_procs = 0
193	self.total_irqs = 0
194	self.total_periphs = 0
195
196	self.clusters = []
197	self.globs = []
198	self.vspaces = []
199
200	for x in xrange( self.x_size ):
201	for y in xrange( self.y_size ):
202	cluster = Cluster( x , y )
203	cluster.index = (x * self.y_size) + y
204	self.clusters.append( cluster )
205
206	return
207
208	########################## add a ram pseg in a cluster
209	def addRam( self,
210	name, # pseg name
211	base, # pseg base address
212	size ): # pseg length (bytes)
213
214	# computes cluster index and coordinates from the base address
215	paddr_lsb_width = self.paddr_width - self.x_width - self.y_width
216	cluster_xy = base >> paddr_lsb_width
217	x = cluster_xy >> (self.y_width);
218	y = cluster_xy & ((1 << self.y_width) - 1)
219	cluster_id = (x * self.y_size) + y
220
221	assert (base & VPN_ANTI_MASK) == 0
222
223	assert (x < self.x_size) and (y < self.y_size)
224
225	assert ( (base & ((1<<paddr_lsb_width)-1)) == self.ram_base )
226
227	assert ( size == self.ram_size )
228
229	# add one pseg in the mapping
230	pseg = Pseg( name, base, size, x, y, 'RAM' )
231	self.clusters[cluster_id].psegs.append( pseg )
232	pseg.index = self.total_psegs
233	self.total_psegs += 1
234
235	return pseg
236
237	########################## add a peripheral and the associated pseg in a cluster
238	def addPeriph( self,
239	name, # associated pseg name
240	base, # associated pseg base address
241	size, # associated pseg length (bytes)
242	ptype, # peripheral type
243	subtype = 'NONE', # peripheral subtype
244	channels = 1, # number of channels
245	arg0 = 0, # optional argument (semantic depends on ptype)
246	arg1 = 0, # optional argument (semantic depends on ptype)
247	arg2 = 0, # optional argument (semantic depends on ptype)
248	arg3 = 0 ): # optional argument (semantic depends on ptype)
249
250	# computes cluster index and coordinates from the base address
251	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
252	x = cluster_xy >> (self.y_width);
253	y = cluster_xy & ((1 << self.y_width) - 1)
254	cluster_id = (x * self.y_size) + y
255
256	assert (x < self.x_size) and (y < self.y_size)
257
258	assert (base & VPN_ANTI_MASK) == 0
259
260	assert ptype in PERIPHTYPES
261
262	if (ptype == 'IOC'): assert subtype in IOCSUBTYPES
263	if (ptype == 'MWR'): assert subtype in MWRSUBTYPES
264
265	# add one pseg into mapping
266	pseg = Pseg( name, base, size, x, y, 'PERI' )
267	self.clusters[cluster_id].psegs.append( pseg )
268	pseg.index = self.total_psegs
269	self.total_psegs += 1
270
271	# add one periph into mapping
272	periph = Periph( pseg, ptype, subtype, channels, arg0, arg1, arg2, arg3 )
273	self.clusters[cluster_id].periphs.append( periph )
274	periph.index = self.total_periphs
275	self.total_periphs += 1
276
277	return periph
278
279	################################ add an IRQ in a peripheral
280	def addIrq( self,
281	periph, # peripheral containing IRQ (PIC or XCU)
282	index, # peripheral input port index
283	isrtype, # ISR type
284	channel = 0 ): # channel for multi-channels ISR
285
286	assert isrtype in ISRTYPES
287
288	assert index < 32
289
290	# add one irq into mapping
291	irq = Irq( 'HWI', index , isrtype, channel )
292	periph.irqs.append( irq )
293	irq.index = self.total_irqs
294	self.total_irqs += 1
295
296	return irq
297
298	########################## add a processor in a cluster
299	def addProc( self,
300	x, # cluster x coordinate
301	y, # cluster y coordinate
302	lpid ): # processor local index
303
304	assert (x < self.x_size) and (y < self.y_size)
305
306	cluster_id = (x * self.y_size) + y
307
308	# add one proc into mapping
309	proc = Processor( x, y, lpid )
310	self.clusters[cluster_id].procs.append( proc )
311	proc.index = self.total_procs
312	self.total_procs += 1
313
314	return proc
315
316	############################ add one global vseg into mapping
317	def addGlobal( self,
318	name, # vseg name
319	vbase, # virtual base address
320	length, # vseg length (bytes)
321	mode, # CXWU flags
322	vtype, # vseg type
323	x, # destination x coordinate
324	y, # destination y coordinate
325	pseg, # destination pseg name
326	identity = False, # identity mapping required if true
327	local = False, # only mapped in local PTAB if true
328	big = False, # to be mapped in a big physical page
329	binpath = '' ): # pathname for binary code if required
330
331	# two global vsegs must not overlap if they have different names
332	for prev in self.globs:
333	if ( ((prev.vbase + prev.length) > vbase ) and
334	((vbase + length) > prev.vbase) and
335	(prev.name[0:15] != name[0:15]) ):
336	print '[genmap error] in addGlobal()'
337	print ' global vseg %s overlap %s' % (name, prev.name)
338	print ' %s : base = %x / size = %x' %(name, vbase, length)
339	print ' %s : base = %x / size = %x' %(prev.name, prev.vbase, prev.length)
340	sys.exit(1)
341
342	# add one vseg into mapping
343	vseg = Vseg( name, vbase, length, mode, vtype, x, y, pseg,
344	identity = identity, local = local, big = big, binpath = binpath )
345
346	self.globs.append( vseg )
347	self.total_globals += 1
348	vseg.index = self.total_vsegs
349	self.total_vsegs += 1
350
351	return
352
353	################################ add a vspace into mapping
354	def addVspace( self,
355	name, # vspace name
356	startname ): # name of vseg containing start_vector
357
358	# add one vspace into mapping
359	vspace = Vspace( name, startname )
360	self.vspaces.append( vspace )
361	vspace.index = self.total_vspaces
362	self.total_vspaces += 1
363
364	return vspace
365
366	################################# add a private vseg in a vspace
367	def addVseg( self,
368	vspace, # vspace containing the vseg
369	name, # vseg name
370	vbase, # virtual base address
371	length, # vseg length (bytes)
372	mode, # CXWU flags
373	vtype, # vseg type
374	x, # destination x coordinate
375	y, # destination y coordinate
376	pseg, # destination pseg name
377	local = False, # only mapped in local PTAB if true
378	big = False, # to be mapped in a big physical page
379	binpath = '' ): # pathname for binary code
380
381	assert mode in VSEGMODES
382
383	assert vtype in VSEGTYPES
384
385	assert (x < self.x_size) and (y < self.y_size)
386
387	# add one vseg into mapping
388	vseg = Vseg( name, vbase, length, mode, vtype, x, y, pseg,
389	identity = False, local = local, big = big, binpath = binpath )
390	vspace.vsegs.append( vseg )
391	vseg.index = self.total_vsegs
392	self.total_vsegs += 1
393
394	return vseg
395
396	################################ add a task in a vspace
397	def addTask( self,
398	vspace, # vspace containing task
399	name, # task name
400	trdid, # task index in vspace
401	x, # destination x coordinate
402	y, # destination y coordinate
403	lpid, # destination processor local index
404	stackname, # name of vseg containing stack
405	heapname, # name of vseg containing heap
406	startid ): # index in start_vector
407
408	assert (x < self.x_size) and (y < self.y_size)
409	assert lpid < self.nprocs
410
411	# add one task into mapping
412	task = Task( name, trdid, x, y, lpid, stackname, heapname, startid )
413	vspace.tasks.append( task )
414	task.index = self.total_tasks
415	self.total_tasks += 1
416
417	return task
418
419	#################################
420	def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array
421
422	byte_stream = bytearray()
423	length = len( s )
424	if length < (nbytes - 1):
425	for b in s:
426	byte_stream.append( b )
427	for x in xrange(nbytes-length):
428	byte_stream.append( '\0' )
429	else:
430	print '[genmap error] in str2bytes()'
431	print ' string %s too long' % s
432	sys.exit(1)
433
434	return byte_stream
435
436	###################################
437	def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array
438
439	byte_stream = bytearray()
440	for n in xrange( nbytes ):
441	byte_stream.append( (val >> (n<<3)) & 0xFF )
442
443	return byte_stream
444
445	################
446	def xml( self ): # compute string for map.xml file generation
447
448	s = '<?xml version="1.0"?>\n\n'
449	s += '<mapping_info signature = "0x%x"\n' % (self.signature)
450	s += ' name = "%s"\n' % (self.name)
451	s += ' x_size = "%d"\n' % (self.x_size)
452	s += ' y_size = "%d"\n' % (self.y_size)
453	s += ' x_width = "%d"\n' % (self.x_width)
454	s += ' y_width = "%d"\n' % (self.y_width)
455	s += ' irq_per_proc = "%d"\n' % (self.irq_per_proc)
456	s += ' use_ramdisk = "%d"\n' % (self.use_ramdisk)
457	s += ' x_io = "%d"\n' % (self.x_io)
458	s += ' y_io = "%d" >\n' % (self.y_io)
459	s += '\n'
460
461	s += ' <clusterset>\n'
462	for x in xrange ( self.x_size ):
463	for y in xrange ( self.y_size ):
464	cluster_id = (x * self.y_size) + y
465	s += self.clusters[cluster_id].xml()
466	s += ' </clusterset>\n'
467	s += '\n'
468
469	s += ' <globalset>\n'
470	for vseg in self.globs: s += vseg.xml()
471	s += ' </globalset>\n'
472	s += '\n'
473
474	s += ' <vspaceset>\n'
475	for vspace in self.vspaces: s += vspace.xml()
476	s += ' </vspaceset>\n'
477
478	s += '</mapping_info>\n'
479	return s
480
481	##########################
482	def cbin( self, verbose ): # C binary structure for map.bin file generation
483
484	byte_stream = bytearray()
485
486	# header
487	byte_stream += self.int2bytes(4, self.signature)
488	byte_stream += self.int2bytes(4, self.x_size)
489	byte_stream += self.int2bytes(4, self.y_size)
490	byte_stream += self.int2bytes(4, self.x_width)
491	byte_stream += self.int2bytes(4, self.y_width)
492	byte_stream += self.int2bytes(4, self.x_io)
493	byte_stream += self.int2bytes(4, self.y_io)
494	byte_stream += self.int2bytes(4, self.irq_per_proc)
495	byte_stream += self.int2bytes(4, self.use_ramdisk)
496	byte_stream += self.int2bytes(4, self.total_globals)
497	byte_stream += self.int2bytes(4, self.total_vspaces)
498	byte_stream += self.int2bytes(4, self.total_psegs)
499	byte_stream += self.int2bytes(4, self.total_vsegs)
500	byte_stream += self.int2bytes(4, self.total_tasks)
501	byte_stream += self.int2bytes(4, self.total_procs)
502	byte_stream += self.int2bytes(4, self.total_irqs)
503	byte_stream += self.int2bytes(4, self.total_periphs)
504	byte_stream += self.str2bytes(64, self.name)
505
506	if ( verbose ):
507	print '\n'
508	print 'name = %s' % self.name
509	print 'signature = %x' % self.signature
510	print 'x_size = %d' % self.x_size
511	print 'y_size = %d' % self.y_size
512	print 'x_width = %d' % self.x_width
513	print 'y_width = %d' % self.y_width
514	print 'x_io = %d' % self.x_io
515	print 'y_io = %d' % self.y_io
516	print 'irq_per_proc = %d' % self.irq_per_proc
517	print 'use_ramdisk = %d' % self.use_ramdisk
518	print 'total_globals = %d' % self.total_globals
519	print 'total_psegs = %d' % self.total_psegs
520	print 'total_vsegs = %d' % self.total_vsegs
521	print 'total_tasks = %d' % self.total_tasks
522	print 'total_procs = %d' % self.total_procs
523	print 'total_irqs = %d' % self.total_irqs
524	print 'total_periphs = %d' % self.total_periphs
525	print '\n'
526
527	# clusters array
528	index = 0
529	for cluster in self.clusters:
530	byte_stream += cluster.cbin( self, verbose, index )
531	index += 1
532
533	if ( verbose ): print '\n'
534
535	# psegs array
536	index = 0
537	for cluster in self.clusters:
538	for pseg in cluster.psegs:
539	byte_stream += pseg.cbin( self, verbose, index, cluster )
540	index += 1
541
542	if ( verbose ): print '\n'
543
544	# vspaces array
545	index = 0
546	for vspace in self.vspaces:
547	byte_stream += vspace.cbin( self, verbose, index )
548	index += 1
549
550	if ( verbose ): print '\n'
551
552	# vsegs array
553	index = 0
554	for vseg in self.globs:
555	byte_stream += vseg.cbin( self, verbose, index )
556	index += 1
557	for vspace in self.vspaces:
558	for vseg in vspace.vsegs:
559	byte_stream += vseg.cbin( self, verbose, index )
560	index += 1
561
562	if ( verbose ): print '\n'
563
564	# tasks array
565	index = 0
566	for vspace in self.vspaces:
567	for task in vspace.tasks:
568	byte_stream += task.cbin( self, verbose, index, vspace )
569	index += 1
570
571	if ( verbose ): print '\n'
572
573	# procs array
574	index = 0
575	for cluster in self.clusters:
576	for proc in cluster.procs:
577	byte_stream += proc.cbin( self, verbose, index )
578	index += 1
579
580	if ( verbose ): print '\n'
581
582	# irqs array
583	index = 0
584	for cluster in self.clusters:
585	for periph in cluster.periphs:
586	for irq in periph.irqs:
587	byte_stream += irq.cbin( self, verbose, index )
588	index += 1
589
590	if ( verbose ): print '\n'
591
592	# periphs array
593	index = 0
594	for cluster in self.clusters:
595	for periph in cluster.periphs:
596	byte_stream += periph.cbin( self, verbose, index )
597	index += 1
598
599	return byte_stream
600	# end of cbin()
601
602	#######################################################################
603	def giet_vsegs( self ): # compute string for giet_vsegs.ld file
604	# required by giet_vm compilation
605
606	# search the vsegs required for the giet_vsegs.ld
607	boot_code_found = False
608	boot_data_found = False
609	kernel_uncdata_found = False
610	kernel_data_found = False
611	kernel_code_found = False
612	kernel_init_found = False
613	for vseg in self.globs:
614
615	if ( vseg.name[0:13] == 'seg_boot_code' ):
616	boot_code_vbase = vseg.vbase
617	boot_code_size = vseg.length
618	boot_code_found = True
619
620	if ( vseg.name[0:13] == 'seg_boot_data' ):
621	boot_data_vbase = vseg.vbase
622	boot_data_size = vseg.length
623	boot_data_found = True
624
625	if ( vseg.name[0:15] == 'seg_kernel_data' ):
626	kernel_data_vbase = vseg.vbase
627	kernel_data_size = vseg.length
628	kernel_data_found = True
629
630	if ( vseg.name[0:15] == 'seg_kernel_code' ):
631	kernel_code_vbase = vseg.vbase
632	kernel_code_size = vseg.length
633	kernel_code_found = True
634
635	if ( vseg.name[0:15] == 'seg_kernel_init' ):
636	kernel_init_vbase = vseg.vbase
637	kernel_init_size = vseg.length
638	kernel_init_found = True
639
640	# check if all required vsegs have been found
641	if ( boot_code_found == False ):
642	print '[genmap error] in giet_vsegs()'
643	print ' seg_boot_code vseg missing'
644	sys.exit()
645
646	if ( boot_data_found == False ):
647	print '[genmap error] in giet_vsegs()'
648	print ' seg_boot_data vseg missing'
649	sys.exit()
650
651	if ( kernel_data_found == False ):
652	print '[genmap error] in giet_vsegs()'
653	print ' seg_kernel_data vseg missing'
654	sys.exit()
655
656	if ( kernel_code_found == False ):
657	print '[genmap error] in giet_vsegs()'
658	print ' seg_kernel_code vseg missing'
659	sys.exit()
660
661	if ( kernel_init_found == False ):
662	print '[genmap error] in giet_vsegs()'
663	print ' seg_kernel_init vseg missing'
664	sys.exit()
665
666	# build string
667	s = '/* Generated by genmap for %s */\n' % self.name
668	s += '\n'
669
670	s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase
671	s += 'boot_code_size = 0x%x;\n' % boot_code_size
672	s += '\n'
673	s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase
674	s += 'boot_data_size = 0x%x;\n' % boot_data_size
675	s += '\n'
676	s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase
677	s += 'kernel_code_size = 0x%x;\n' % kernel_code_size
678	s += '\n'
679	s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase
680	s += 'kernel_data_size = 0x%x;\n' % kernel_data_size
681	s += '\n'
682	s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase
683	s += 'kernel_init_size = 0x%x;\n' % kernel_init_size
684	s += '\n'
685
686	return s
687
688	######################################################################
689	def hard_config( self ): # compute string for hard_config.h file
690	# required by
691	# - top.cpp compilation
692	# - giet_vm compilation
693	# - tsar_preloader compilation
694
695	nb_total_procs = 0
696
697	# for each peripheral type, define default values
698	# for pbase address, size, number of components, and channels
699	nb_cma = 0
700	cma_channels = 0
701	seg_cma_base = 0xFFFFFFFF
702	seg_cma_size = 0
703
704	nb_dma = 0
705	dma_channels = 0
706	seg_dma_base = 0xFFFFFFFF
707	seg_dma_size = 0
708
709	nb_fbf = 0
710	fbf_channels = 0
711	seg_fbf_base = 0xFFFFFFFF
712	seg_fbf_size = 0
713	fbf_arg0 = 0
714	fbf_arg1 = 0
715
716	nb_iob = 0
717	iob_channels = 0
718	seg_iob_base = 0xFFFFFFFF
719	seg_iob_size = 0
720
721	nb_ioc = 0
722	ioc_channels = 0
723	seg_ioc_base = 0xFFFFFFFF
724	seg_ioc_size = 0
725
726	nb_mmc = 0
727	mmc_channels = 0
728	seg_mmc_base = 0xFFFFFFFF
729	seg_mmc_size = 0
730
731	nb_mwr = 0
732	mwr_channels = 0
733	seg_mwr_base = 0xFFFFFFFF
734	seg_mwr_size = 0
735	mwr_arg0 = 0
736	mwr_arg1 = 0
737	mwr_arg2 = 0
738	mwr_arg3 = 0
739
740	nb_nic = 0
741	nic_channels = 0
742	seg_nic_base = 0xFFFFFFFF
743	seg_nic_size = 0
744
745	nb_pic = 0
746	pic_channels = 0
747	seg_pic_base = 0xFFFFFFFF
748	seg_pic_size = 0
749
750	nb_rom = 0
751	rom_channels = 0
752	seg_rom_base = 0xFFFFFFFF
753	seg_rom_size = 0
754
755	nb_sim = 0
756	sim_channels = 0
757	seg_sim_base = 0xFFFFFFFF
758	seg_sim_size = 0
759
760	nb_tim = 0
761	tim_channels = 0
762	seg_tim_base = 0xFFFFFFFF
763	seg_tim_size = 0
764
765	nb_tty = 0
766	tty_channels = 0
767	seg_tty_base = 0xFFFFFFFF
768	seg_tty_size = 0
769
770	nb_xcu = 0
771	xcu_channels = 0
772	seg_xcu_base = 0xFFFFFFFF
773	seg_xcu_size = 0
774	xcu_arg0 = 0
775
776	nb_drom = 0
777	drom_channels = 0
778	seg_drom_base = 0xFFFFFFFF
779	seg_drom_size = 0
780
781	use_bdv = False
782	use_sdc = False
783	use_hba = False
784
785	# get peripherals attributes
786	for cluster in self.clusters:
787	for periph in cluster.periphs:
788	if ( periph.ptype == 'CMA' ):
789	seg_cma_base = periph.pseg.base & 0xFFFFFFFF
790	seg_cma_size = periph.pseg.size
791	cma_channels = periph.channels
792	nb_cma +=1
793
794	elif ( periph.ptype == 'DMA' ):
795	seg_dma_base = periph.pseg.base & 0xFFFFFFFF
796	seg_dma_size = periph.pseg.size
797	dma_channels = periph.channels
798	nb_dma +=1
799
800	elif ( periph.ptype == 'FBF' ):
801	seg_fbf_base = periph.pseg.base & 0xFFFFFFFF
802	seg_fbf_size = periph.pseg.size
803	fbf_channels = periph.channels
804	fbf_arg0 = periph.arg0
805	fbf_arg1 = periph.arg1
806	nb_fbf +=1
807
808	elif ( periph.ptype == 'IOB' ):
809	seg_iob_base = periph.pseg.base & 0xFFFFFFFF
810	seg_iob_size = periph.pseg.size
811	iob_channels = periph.channels
812	nb_iob +=1
813
814	elif ( periph.ptype == 'IOC' ):
815	seg_ioc_base = periph.pseg.base & 0xFFFFFFFF
816	seg_ioc_size = periph.pseg.size
817	ioc_channels = periph.channels
818	nb_ioc += 1
819
820	if self.use_ramdisk: continue
821
822	if ( periph.subtype == 'BDV' ): use_bdv = True
823	elif ( periph.subtype == 'HBA' ): use_hba = True
824	elif ( periph.subtype == 'SDC' ): use_sdc = True
825
826	elif ( periph.ptype == 'MMC' ):
827	seg_mmc_base = periph.pseg.base & 0xFFFFFFFF
828	seg_mmc_size = periph.pseg.size
829	mmc_channels = periph.channels
830	nb_mmc +=1
831
832	elif ( periph.ptype == 'MWR' ):
833	seg_mwr_base = periph.pseg.base & 0xFFFFFFFF
834	seg_mwr_size = periph.pseg.size
835	mwr_channels = periph.channels
836	mwr_arg0 = periph.arg0
837	mwr_arg1 = periph.arg1
838	mwr_arg2 = periph.arg2
839	mwr_arg3 = periph.arg3
840	nb_mwr +=1
841
842	elif ( periph.ptype == 'ROM' ):
843	seg_rom_base = periph.pseg.base & 0xFFFFFFFF
844	seg_rom_size = periph.pseg.size
845	rom_channels = periph.channels
846	nb_rom +=1
847
848	elif ( periph.ptype == 'DROM' ):
849	seg_drom_base = periph.pseg.base & 0xFFFFFFFF
850	seg_drom_size = periph.pseg.size
851	drom_channels = periph.channels
852	nb_drom +=1
853
854	elif ( periph.ptype == 'SIM' ):
855	seg_sim_base = periph.pseg.base & 0xFFFFFFFF
856	seg_sim_size = periph.pseg.size
857	sim_channels = periph.channels
858	nb_sim +=1
859
860	elif ( periph.ptype == 'NIC' ):
861	seg_nic_base = periph.pseg.base & 0xFFFFFFFF
862	seg_nic_size = periph.pseg.size
863	nic_channels = periph.channels
864	nb_nic +=1
865
866	elif ( periph.ptype == 'PIC' ):
867	seg_pic_base = periph.pseg.base & 0xFFFFFFFF
868	seg_pic_size = periph.pseg.size
869	pic_channels = periph.channels
870	nb_pic +=1
871
872	elif ( periph.ptype == 'TIM' ):
873	seg_tim_base = periph.pseg.base & 0xFFFFFFFF
874	seg_tim_size = periph.pseg.size
875	tim_channels = periph.channels
876	nb_tim +=1
877
878	elif ( periph.ptype == 'TTY' ):
879	seg_tty_base = periph.pseg.base & 0xFFFFFFFF
880	seg_tty_size = periph.pseg.size
881	tty_channels = periph.channels
882	nb_tty +=1
883
884	elif ( periph.ptype == 'XCU' ):
885	seg_xcu_base = periph.pseg.base & 0xFFFFFFFF
886	seg_xcu_size = periph.pseg.size
887	xcu_channels = periph.channels
888	xcu_arg0 = periph.arg0
889	xcu_arg1 = periph.arg1
890	xcu_arg2 = periph.arg2
891	nb_xcu +=1
892
893	# no more than two access to external peripherals
894	assert ( nb_fbf <= 2 )
895	assert ( nb_cma <= 2 )
896	assert ( nb_ioc <= 2 )
897	assert ( nb_nic <= 2 )
898	assert ( nb_tim <= 2 )
899	assert ( nb_tty <= 2 )
900	assert ( nb_pic <= 2 )
901
902	# one and only one type of IOC controller
903	nb_iocs = 0
904	if use_hba : nb_iocs += 1
905	if use_bdv : nb_iocs += 1
906	if use_sdc : nb_iocs += 1
907	if self.use_ramdisk: nb_iocs += 1
908	assert ( nb_iocs == 1 )
909
910	# Compute total number of processors
911	for cluster in self.clusters:
912	nb_total_procs += len( cluster.procs )
913
914	# Compute physical addresses for BOOT vsegs
915	boot_mapping_found = False
916	boot_code_found = False
917	boot_data_found = False
918	boot_stack_found = False
919
920	for vseg in self.globs:
921	if ( vseg.name == 'seg_boot_mapping' ):
922	boot_mapping_base = vseg.vbase
923	boot_mapping_size = vseg.length
924	boot_mapping_identity = vseg.identity
925	boot_mapping_found = True
926
927	if ( vseg.name == 'seg_boot_code' ):
928	boot_code_base = vseg.vbase
929	boot_code_size = vseg.length
930	boot_code_identity = vseg.identity
931	boot_code_found = True
932
933	if ( vseg.name == 'seg_boot_data' ):
934	boot_data_base = vseg.vbase
935	boot_data_size = vseg.length
936	boot_data_identity = vseg.identity
937	boot_data_found = True
938
939	if ( vseg.name == 'seg_boot_stack' ):
940	boot_stack_base = vseg.vbase
941	boot_stack_size = vseg.length
942	boot_stack_identity = vseg.identity
943	boot_stack_found = True
944
945	# check that BOOT vsegs are found and identity mapping
946	if ( (boot_mapping_found == False) or (boot_mapping_identity == False) ):
947	print '[genmap error] in hard_config()'
948	print ' seg_boot_mapping missing or not identity mapping'
949	sys.exit()
950
951	if ( (boot_code_found == False) or (boot_code_identity == False) ):
952	print '[genmap error] in hard_config()'
953	print ' seg_boot_code missing or not identity mapping'
954	sys.exit()
955
956	if ( (boot_data_found == False) or (boot_data_identity == False) ):
957	print '[genmap error] in hard_config()'
958	print ' seg_boot_data missing or not identity mapping'
959	sys.exit()
960
961	if ( (boot_stack_found == False) or (boot_stack_identity == False) ):
962	print '[genmap error] in giet_vsegs()'
963	print ' seg_boot_stask missing or not identity mapping'
964	sys.exit()
965
966	# Search RAMDISK global vseg if required
967	seg_rdk_base = 0xFFFFFFFF
968	seg_rdk_size = 0
969	seg_rdk_found = False
970
971	if self.use_ramdisk:
972	for vseg in self.globs:
973	if ( vseg.name == 'seg_ramdisk' ):
974	seg_rdk_base = vseg.vbase
975	seg_rdk_size = vseg.length
976	seg_rdk_found = True
977
978	if ( seg_rdk_found == False ):
979	print 'Error in hard_config() "seg_ramdisk" not found'
980	sys.exit(1)
981
982	# build string
983	s = '/* Generated by genmap for %s */\n' % self.name
984	s += '\n'
985	s += '#ifndef HARD_CONFIG_H\n'
986	s += '#define HARD_CONFIG_H\n'
987	s += '\n'
988
989	s += '/* General platform parameters */\n'
990	s += '\n'
991	s += '#define X_SIZE %d\n' % self.x_size
992	s += '#define Y_SIZE %d\n' % self.y_size
993	s += '#define X_WIDTH %d\n' % self.x_width
994	s += '#define Y_WIDTH %d\n' % self.y_width
995	s += '#define P_WIDTH %d\n' % self.p_width
996	s += '#define X_IO %d\n' % self.x_io
997	s += '#define Y_IO %d\n' % self.y_io
998	s += '#define NB_PROCS_MAX %d\n' % self.nprocs
999	s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc
1000	s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address
1001	s += '#define NB_TOTAL_PROCS %d\n' % nb_total_procs
1002	s += '\n'
1003
1004	s += '/* Peripherals */\n'
1005	s += '\n'
1006	s += '#define NB_TTY_CHANNELS %d\n' % tty_channels
1007	s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels
1008	s += '#define NB_NIC_CHANNELS %d\n' % nic_channels
1009	s += '#define NB_CMA_CHANNELS %d\n' % cma_channels
1010	s += '#define NB_TIM_CHANNELS %d\n' % tim_channels
1011	s += '#define NB_DMA_CHANNELS %d\n' % dma_channels
1012	s += '\n'
1013	s += '#define USE_XCU %d\n' % ( nb_xcu != 0 )
1014	s += '#define USE_IOB %d\n' % ( nb_iob != 0 )
1015	s += '#define USE_PIC %d\n' % ( nb_pic != 0 )
1016	s += '#define USE_FBF %d\n' % ( nb_fbf != 0 )
1017	s += '#define USE_NIC %d\n' % ( nb_nic != 0 )
1018	s += '\n'
1019	s += '#define USE_IOC_BDV %d\n' % use_bdv
1020	s += '#define USE_IOC_SDC %d\n' % use_sdc
1021	s += '#define USE_IOC_HBA %d\n' % use_hba
1022	s += '#define USE_IOC_RDK %d\n' % self.use_ramdisk
1023	s += '\n'
1024	s += '#define FBUF_X_SIZE %d\n' % fbf_arg0
1025	s += '#define FBUF_Y_SIZE %d\n' % fbf_arg1
1026	s += '\n'
1027	s += '#define XCU_NB_HWI %d\n' % xcu_arg0
1028	s += '#define XCU_NB_PTI %d\n' % xcu_arg1
1029	s += '#define XCU_NB_WTI %d\n' % xcu_arg2
1030	s += '#define XCU_NB_OUT %d\n' % xcu_channels
1031	s += '\n'
1032	s += '#define MWR_TO_COPROC %d\n' % mwr_arg0
1033	s += '#define MWR_FROM_COPROC %d\n' % mwr_arg1
1034	s += '#define MWR_CONFIG %d\n' % mwr_arg2
1035	s += '#define MWR_STATUS %d\n' % mwr_arg3
1036	s += '\n'
1037
1038	s += '/* base addresses and sizes for physical segments */\n'
1039	s += '\n'
1040	s += '#define SEG_RAM_BASE 0x%x\n' % self.ram_base
1041	s += '#define SEG_RAM_SIZE 0x%x\n' % self.ram_size
1042	s += '\n'
1043	s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base
1044	s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size
1045	s += '\n'
1046	s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base
1047	s += '#define SEG_DMA_SIZE 0x%x\n' % seg_dma_size
1048	s += '\n'
1049	s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base
1050	s += '#define SEG_FBF_SIZE 0x%x\n' % seg_fbf_size
1051	s += '\n'
1052	s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base
1053	s += '#define SEG_IOB_SIZE 0x%x\n' % seg_iob_size
1054	s += '\n'
1055	s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base
1056	s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size
1057	s += '\n'
1058	s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base
1059	s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size
1060	s += '\n'
1061	s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base
1062	s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size
1063	s += '\n'
1064	s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base
1065	s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size
1066	s += '\n'
1067	s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base
1068	s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size
1069	s += '\n'
1070	s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base
1071	s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size
1072	s += '\n'
1073	s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base
1074	s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size
1075	s += '\n'
1076	s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base
1077	s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size
1078	s += '\n'
1079	s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base
1080	s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size
1081	s += '\n'
1082	s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base
1083	s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size
1084	s += '\n'
1085	s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base
1086	s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size
1087	s += '\n'
1088	s += '#define SEG_DROM_BASE 0x%x\n' % seg_drom_base
1089	s += '#define SEG_DROM_SIZE 0x%x\n' % seg_drom_size
1090	s += '\n'
1091	s += '#define PERI_CLUSTER_INCREMENT 0x%x\n' % self.peri_increment
1092	s += '\n'
1093
1094	s += '/* physical base addresses for identity mapped vsegs */\n'
1095	s += '/* used by the GietVM OS */\n'
1096	s += '\n'
1097	s += '#define SEG_BOOT_MAPPING_BASE 0x%x\n' % boot_mapping_base
1098	s += '#define SEG_BOOT_MAPPING_SIZE 0x%x\n' % boot_mapping_size
1099	s += '\n'
1100	s += '#define SEG_BOOT_CODE_BASE 0x%x\n' % boot_code_base
1101	s += '#define SEG_BOOT_CODE_SIZE 0x%x\n' % boot_code_size
1102	s += '\n'
1103	s += '#define SEG_BOOT_DATA_BASE 0x%x\n' % boot_data_base
1104	s += '#define SEG_BOOT_DATA_SIZE 0x%x\n' % boot_data_size
1105	s += '\n'
1106	s += '#define SEG_BOOT_STACK_BASE 0x%x\n' % boot_stack_base
1107	s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size
1108	s += '#endif\n'
1109
1110	return s
1111
1112	# end of hard_config()
1113
1114	#################################################################
1115	def linux_dts( self ): # compute string for linux.dts file
1116	# used for linux configuration
1117	# header
1118	s = '/dts-v1/;\n'
1119	s += '\n'
1120	s += '/{\n'
1121	s += ' compatible = "tsar,%s";\n' % self.name
1122	s += ' #address-cells = <2>;\n' # physical address on 64 bits
1123	s += ' #size-cells = <1>;\n' # segment size on 32 bits
1124	s += ' model = "%s";\n' % self.name
1125	s += '\n'
1126
1127	# linux globals arguments
1128	s += ' chosen {\n'
1129	s += ' linux,stdout-path = &tty;\n'
1130	s += ' bootargs = "console=tty0 console=ttyVTTY0 earlyprintk";\n'
1131	s += ' };\n\n'
1132
1133	# cpus (for each cluster)
1134	s += ' cpus {\n'
1135	s += ' #address-cells = <1>;\n'
1136	s += ' #size-cells = <0>;\n'
1137
1138	for cluster in self.clusters:
1139	for proc in cluster.procs:
1140	x = cluster.x
1141	y = cluster.y
1142	l = proc.lpid
1143	proc_id = (((x << self.y_width) + y) << self.p_width) + l
1144	s += ' cpu@%d_%d_%d {\n' %(x,y,l)
1145	s += ' device_type = "cpu";\n'
1146	s += ' compatible = "soclib,mips32el";\n'
1147	s += ' reg = <0x%x>;\n' % proc_id
1148	s += ' };\n'
1149	s += '\n'
1150
1151	s += ' };\n\n'
1152
1153	# devices (ram or peripheral) are grouped per cluster
1154	# the "compatible" attribute links a peripheral device
1155	# to one or several drivers identified by ("major","minor")
1156
1157	for cluster in self.clusters:
1158	x = cluster.x
1159	y = cluster.y
1160	found_xcu = False
1161	found_pic = False
1162
1163	s += ' /* cluster[%d,%d] */\n\n' % (x,y)
1164
1165	# scan all psegs to find RAM in current cluster
1166	for pseg in cluster.psegs:
1167	if ( pseg.segtype == 'RAM' ):
1168	msb = pseg.base >> 32
1169	lsb = pseg.base & 0xFFFFFFFF
1170	size = pseg.size
1171
1172	s += ' ram_%d_%d: ram@0x%x {\n' % (x, y, pseg.base)
1173	s += ' device_type = "memory";\n'
1174	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1175	s += ' };\n\n'
1176
1177	# scan all periphs to find XCU or PIC in current cluster
1178	for periph in cluster.periphs:
1179	msb = periph.pseg.base >> 32
1180	lsb = periph.pseg.base & 0xFFFFFFFF
1181	size = periph.pseg.size
1182
1183	# search XCU (can be replicated)
1184	if ( (periph.ptype == 'XCU') ):
1185	found_xcu = True
1186	xcu = periph
1187	irq_ctrl_name = 'xcu_%d_%d' % (x, y)
1188
1189	s += ' %s: xcu@0x%x {\n' % (irq_ctrl_name, periph.pseg.base)
1190	s += ' compatible = "soclib,vci_xicu","soclib,vci_xicu_timer";\n'
1191	s += ' interrupt-controller;\n'
1192	s += ' #interrupt-cells = <1>;\n'
1193	s += ' clocks = <&freq>;\n' # XCU contains a timer
1194	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1195	s += ' };\n\n'
1196
1197	# search PIC (non replicated)
1198	if ( periph.ptype == 'PIC' ):
1199	found_pic = True
1200	pic = periph
1201	irq_ctrl_name = 'pic'
1202
1203	s += ' %s: pic@0x%x {\n' % (irq_ctrl_name, periph.pseg.base)
1204	s += ' compatible = "soclib,vci_iopic";\n'
1205	s += ' interrupt-controller;\n'
1206	s += ' #interrupt-cells = <1>;\n'
1207	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1208	s += ' };\n\n'
1209
1210	# we need one interrupt controler in any cluster containing peripherals
1211	if ( (found_xcu == False) and
1212	(found_pic == False) and
1213	(len(cluster.periphs) > 0) ):
1214	print '[genmap error] in linux_dts()'
1215	print ' No XCU/PIC in cluster(%d,%d)' % (x,y)
1216	sys.exit(1)
1217
1218	if ( found_pic == True ): irq_ctrl = pic
1219	else: irq_ctrl = xcu
1220
1221	# scan all periphs to find TTY and IOC in current cluster
1222	for periph in cluster.periphs:
1223	msb = periph.pseg.base >> 32
1224	lsb = periph.pseg.base & 0xFFFFFFFF
1225	size = periph.pseg.size
1226
1227	# search TTY (non replicated)
1228	if ( periph.ptype == 'TTY' ):
1229
1230	# get HWI index to XCU or PIC (only TTY0 is used by Linux)
1231	hwi_id = 0xFFFFFFFF
1232	for irq in irq_ctrl.irqs:
1233	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == 0) ):
1234	hwi_id = irq.srcid
1235
1236	if ( hwi_id == 0xFFFFFFFF ):
1237	print '[genmap error] in linux.dts()'
1238	print ' IRQ_TTY_RX not found'
1239	sys.exit(1)
1240
1241	s += ' tty: tty@0x%x {\n' % (periph.pseg.base)
1242	s += ' compatible = "soclib,vci_multi_tty";\n'
1243	s += ' interrupt-parent = <&%s>;\n' % (irq_ctrl_name)
1244	s += ' interrupts = <%d>;\n' % hwi_id
1245	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1246	s += ' };\n\n'
1247
1248	# search IOC (non replicated)
1249	elif ( periph.ptype == 'IOC' ):
1250
1251	if ( periph.subtype == 'BDV' ):
1252
1253	# get irq line index associated to bdv
1254	hwi_id = 0xFFFFFFFF
1255	for irq in irq_ctrl.irqs:
1256	if ( irq.isrtype == 'ISR_BDV' ): hwi_id = irq.srcid
1257
1258	if ( hwi_id == 0xFFFFFFFF ):
1259	print '[genmap error] in linux.dts()'
1260	print ' ISR_BDV not found'
1261	sys.exit(1)
1262
1263	s += ' bdv: bdv@0x%x {\n' % (periph.pseg.base)
1264	s += ' compatible = "tsar,vci_block_device";\n'
1265	s += ' interrupt-parent = <&%s>;\n' % (irq_ctrl_name)
1266	s += ' interrupts = <%d>;\n' % hwi_id
1267	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1268	s += ' };\n\n'
1269
1270	else:
1271	print '[genmap warning] in linux_dts() : '
1272	print ' %s' % (periph.subtype),
1273	print 'peripheral not supported by LINUX'
1274
1275	# XCU or PIC have been already parsed
1276	elif ( periph.ptype == 'XCU' ) or ( periph.ptype == 'PIC' ):
1277	pass
1278
1279	# other peripherals
1280	else:
1281	print '[genmap warning] in linux_dts() : '
1282	print ' %s peripheral not supported by LINUX' % (periph.ptype)
1283
1284	# clocks
1285	s += ' /* clocks */\n\n'
1286	s += ' clocks {\n'
1287	s += ' freq: freq@50MHZ {\n'
1288	s += ' #clock-cells = <0>;\n'
1289	s += ' compatible = "fixed-clock";\n'
1290	s += ' clock-frequency = <50000000>;\n'
1291	s += ' };\n'
1292	s += ' };\n\n'
1293	s += ' cpuclk {\n'
1294	s += ' compatible = "soclib,mips32_clksrc";\n'
1295	s += ' clocks = <&freq>;\n'
1296	s += ' };\n'
1297	s += '};\n'
1298
1299	return s
1300	# end linux_dts()
1301
1302
1303	#################################################################
1304	def netbsd_dts( self ): # compute string for netbsd.dts file
1305	# used for netbsd configuration
1306	# header
1307	s = '/dts-v1/;\n'
1308	s += '\n'
1309	s += '/{\n'
1310	s += ' #address-cells = <2>;\n'
1311	s += ' #size-cells = <1>;\n'
1312
1313	# cpus (for each cluster)
1314	s += ' cpus {\n'
1315	s += ' #address-cells = <1>;\n'
1316	s += ' #size-cells = <0>;\n'
1317
1318	for cluster in self.clusters:
1319	for proc in cluster.procs:
1320	proc_id = (((cluster.x << self.y_width) + cluster.y)
1321	<< self.p_width) + proc.lpid
1322
1323	s += ' Mips,32@0x%x {\n' % proc_id
1324	s += ' device_type = "cpu";\n'
1325	s += ' icudev_type = "cpu:mips";\n'
1326	s += ' name = "Mips,32";\n'
1327	s += ' reg = <0x%x>;\n' % proc_id
1328	s += ' };\n'
1329	s += '\n'
1330
1331	s += ' };\n'
1332
1333	# physical memory banks (for each cluster)
1334	for cluster in self.clusters:
1335	for pseg in cluster.psegs:
1336
1337	if ( pseg.segtype == 'RAM' ):
1338	msb = pseg.base >> 32
1339	lsb = pseg.base & 0xFFFFFFFF
1340	size = pseg.size
1341
1342	s += ' %s@0x%x {\n' % (pseg.name, pseg.base)
1343	s += ' cached = <1>;\n'
1344	s += ' device_type = "memory";\n'
1345	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb,lsb,size)
1346	s += ' };\n'
1347
1348	# peripherals (for each cluster)
1349	for cluster in self.clusters:
1350	x = cluster.x
1351	y = cluster.y
1352
1353	# research XCU component
1354	found_xcu = False
1355	for periph in cluster.periphs:
1356	if ( (periph.ptype == 'XCU') ):
1357	found_xcu = True
1358	xcu = periph
1359	msb = periph.pseg.base >> 32
1360	lsb = periph.pseg.base & 0xFFFFFFFF
1361	size = periph.pseg.size
1362
1363	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1364	s += ' device_type = "soclib:xicu:root";\n'
1365	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb,lsb,size)
1366	s += ' input_lines = <%d>;\n' % periph.arg
1367	s += ' ipis = <%d>;\n' % periph.arg
1368	s += ' timers = <%d>;\n' % periph.arg
1369
1370	output_id = 0 # output index from XCU
1371	for lpid in xrange ( len(cluster.procs) ): # destination processor index
1372	for itid in xrange ( self.irq_per_proc ): # input irq index on processor
1373	cluster_xy = (cluster.x << self.y_width) + cluster.y
1374	proc_id = (cluster_xy << self.p_width) + lpid
1375	s += ' out@%d {\n' % output_id
1376	s += ' device_type = "soclib:xicu:filter";\n'
1377	s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid)
1378	s += ' output_line = <%d>;\n' % output_id
1379	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1380	s += ' };\n'
1381
1382	output_id += 1
1383
1384	s += ' };\n'
1385
1386	# research PIC component
1387	found_pic = False
1388	for periph in cluster.periphs:
1389	if ( periph.ptype == 'PIC' ):
1390	found_pic = True
1391	pic = periph
1392	msb = periph.pseg.base >> 32
1393	lsb = periph.pseg.base & 0xFFFFFFFF
1394	size = periph.pseg.size
1395
1396	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1397	s += ' device_type = "soclib:pic:root";\n'
1398	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1399	s += ' input_lines = <%d>;\n' % periph.channels
1400	s += ' };\n'
1401
1402	# at least one interrupt controller
1403	if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ):
1404	print '[genmap error] in netbsd_dts()'
1405	print ' No XCU/PIC in cluster(%d,%d)' % (x,y)
1406	sys.exit(1)
1407
1408	if ( found_pic == True ): irq_tgt = pic
1409	else: irq_tgt = xcu
1410
1411	# get all others peripherals in cluster
1412	for periph in cluster.periphs:
1413	msb = periph.pseg.base >> 32
1414	lsb = periph.pseg.base & 0xFFFFFFFF
1415	size = periph.pseg.size
1416
1417	# research DMA component
1418	if ( periph.ptype == 'DMA' ):
1419
1420	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1421	s += ' device_type = "soclib:dma";\n'
1422	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1423	s += ' channel_count = <%d>;\n' % periph.channels
1424
1425	# multi-channels : get HWI index (to XCU) for each channel
1426	for channel in xrange( periph.channels ):
1427	hwi_id = 0xFFFFFFFF
1428	for irq in xcu.irqs:
1429	if ( (irq.isrtype == 'ISR_DMA') and
1430	(irq.channel == channel) ):
1431	hwi_id = irq.srcid
1432
1433	if ( hwi_id == 0xFFFFFFFF ):
1434	print '[genmap error] in netbsd.dts()'
1435	print ' ISR_DMA channel %d not found' % channel
1436	sys.exit(1)
1437
1438	name = '%s@0x%x' % (xcu.pseg.name, xcu.pseg.base)
1439	s += ' irq@%d{\n' % channel
1440	s += ' device_type = "soclib:periph:irq";\n'
1441	s += ' output_line = <%d>;\n' % channel
1442	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1443	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1444	s += ' };\n'
1445
1446	s += ' };\n'
1447
1448	# research MMC component
1449	elif ( periph.ptype == 'MMC' ):
1450
1451	# get irq line index associated to MMC in XCU
1452	irq_in = 0xFFFFFFFF
1453	for irq in xcu.irqs:
1454	if ( irq.isrtype == 'ISR_MMC' ): irq_in = irq.srcid
1455
1456	if ( irq_in == 0xFFFFFFFF ):
1457	print '[genmap error] in netbsd.dts()'
1458	print ' ISR_MMC not found'
1459	sys.exit(1)
1460
1461	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1462	s += ' device_type = "soclib:mmc";\n'
1463	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
1464	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1465	s += ' };\n'
1466
1467	# research FBF component
1468	elif ( periph.ptype == 'FBF' ):
1469
1470	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1471	s += ' device_type = "soclib:framebuffer";\n'
1472	s += ' mode = <32>;\n' # bits par pixel
1473	s += ' width = <%d>;\n' % periph.arg
1474	s += ' height = <%d>;\n' % periph.arg
1475	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1476	s += ' };\n'
1477
1478	# research IOC component
1479	elif ( periph.ptype == 'IOC' ):
1480
1481	if ( periph.subtype == 'BDV' ):
1482
1483	# get irq line index associated to bdv
1484	irq_in = 0xFFFFFFFF
1485	for irq in irq_tgt.irqs:
1486	if ( irq.isrtype == 'ISR_BDV' ): irq_in = irq.srcid
1487	if ( irq_in == 0xFFFFFFFF ):
1488	print '[genmap error] in netbsd.dts()'
1489	print ' ISR_BDV not found'
1490	sys.exit(1)
1491
1492	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1493	s += ' device_type = "soclib:blockdevice";\n'
1494	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name,irq_tgt.pseg.base,irq_in)
1495	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1496	s += ' };\n'
1497
1498	elif ( periph.subtype == 'HBA' ):
1499	print '[genmap error] in netbsd_dts()'
1500	print ' HBA peripheral not supported by NetBSD'
1501	sys.exit(1)
1502
1503	elif ( periph.subtype == 'SDC' ):
1504
1505	# get irq line index associated to sdc
1506	irq_in = 0xFFFFFFFF
1507	for irq in irq_tgt.irqs:
1508	if ( irq.isrtype == 'ISR_SDC' ): irq_in = irq.srcid
1509	if ( irq_in == 0xFFFFFFFF ):
1510	print '[genmap error] in netbsd.dts()'
1511	print ' ISR_SDC not found'
1512	sys.exit(1)
1513
1514	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1515	s += ' device_type = "soclib:sdc";\n'
1516	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name,irq_tgt.pseg.base,irq_in)
1517	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1518	s += ' };\n'
1519
1520	# research ROM component
1521	elif ( periph.ptype == 'ROM' ):
1522
1523	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1524	s += ' device_type = "rom";\n'
1525	s += ' cached = <1>;\n'
1526	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1527	s += ' };\n'
1528
1529	# research SIM component
1530	elif ( periph.ptype == 'SIM' ):
1531
1532	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1533	s += ' device_type = "soclib:simhelper";\n'
1534	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1535	s += ' };\n'
1536
1537	# research TTY component
1538	elif ( periph.ptype == 'TTY' ):
1539
1540	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1541	s += ' device_type = "soclib:tty";\n'
1542	s += ' channel_count = < %d >;\n' % periph.channels
1543	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1544
1545	# multi-channels : get HWI index (to XCU or PIC) for each channel
1546	for channel in xrange( periph.channels ):
1547	hwi_id = 0xFFFFFFFF
1548	for irq in irq_tgt.irqs:
1549	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ):
1550	hwi_id = irq.srcid
1551	if ( hwi_id == 0xFFFFFFFF ):
1552	print '[genmap error] in netbsd.dts()'
1553	print ' ISR_TTY_RX channel %d not found' % channel
1554	sys.exit(1)
1555
1556	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1557	s += ' irq@%d{\n' % channel
1558	s += ' device_type = "soclib:periph:irq";\n'
1559	s += ' output_line = <%d>;\n' % channel
1560	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1561	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1562	s += ' };\n'
1563
1564	s += ' };\n'
1565
1566	# research IOB component
1567	elif ( periph.ptype == 'IOB' ):
1568
1569	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1570	s += ' device_type = "soclib:iob";\n'
1571	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1572	s += ' };\n'
1573
1574	# research NIC component
1575	elif ( periph.ptype == 'NIC' ):
1576
1577	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1578	s += ' device_type = "soclib:nic";\n'
1579	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1580	s += ' channel_count = < %d >;\n' % periph.channels
1581
1582	# multi-channels : get HWI index (to XCU or PIC) for RX & TX IRQs
1583	# RX IRQ : (2channel) / TX IRQs : (2channel + 1)
1584	for channel in xrange( periph.channels ):
1585	hwi_id = 0xFFFFFFFF
1586	for irq in irq_tgt.irqs:
1587	if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ):
1588	hwi_id = irq.srcid
1589	if ( hwi_id == 0xFFFFFFFF ):
1590	print '[genmap error] in netbsd.dts()'
1591	print ' ISR_NIC_RX channel %d not found' % channel
1592	sys.exit(1)
1593
1594	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1595	s += ' irq_rx@%d{\n' % channel
1596	s += ' device_type = "soclib:periph:irq";\n'
1597	s += ' output_line = <%d>;\n' % (2*channel)
1598	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1599	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1600	s += ' };\n'
1601
1602	hwi_id = 0xFFFFFFFF
1603	for irq in irq_tgt.irqs:
1604	if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ):
1605	hwi_id = irq.srcid
1606	if ( hwi_id == 0xFFFFFFFF ):
1607	print '[genmap error] in netbsd.dts()'
1608	print ' ISR_NIC_TX channel %d not found' % channel
1609	sys.exit(1)
1610
1611	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1612	s += ' irq_tx@%d{\n' % channel
1613	s += ' device_type = "soclib:periph:irq";\n'
1614	s += ' output_line = <%d>;\n' % (2*channel + 1)
1615	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1616	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1617	s += ' };\n'
1618
1619	s += ' };\n'
1620
1621	# research CMA component
1622	elif ( periph.ptype == 'CMA' ):
1623
1624	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1625	s += ' device_type = "soclib:cma";\n'
1626	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1627	s += ' channel_count = < %d >;\n' % periph.channels
1628
1629	# multi-channels : get HWI index (to XCU or PIC) for each channel
1630	for channel in xrange( periph.channels ):
1631	hwi_id = 0xFFFFFFFF
1632	for irq in irq_tgt.irqs:
1633	if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ):
1634	hwi_id = irq.srcid
1635
1636	if ( hwi_id == 0xFFFFFFFF ):
1637	print '[genmap error] in netbsd.dts()'
1638	print ' ISR_CMA channel %d not found' % channel
1639	sys.exit(1)
1640
1641	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1642	s += ' irq@%d{\n' % channel
1643	s += ' device_type = "soclib:periph:irq";\n'
1644	s += ' output_line = <%d>;\n' % channel
1645	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1646	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1647	s += ' };\n'
1648
1649	s += ' };\n'
1650
1651	# research TIM component
1652	elif ( periph.ptype == 'TIM' ):
1653
1654	print '[genmap error] in netbsd_dts()'
1655	print ' TIM peripheral not supported by NetBSD'
1656	sys.exit(1)
1657
1658	# research MWR component
1659	elif ( periph.ptype == 'MWR' ):
1660
1661	print '[genmap error] in netbsd_dts()'
1662	print ' MWR peripheral not supported by NetBSD'
1663	sys.exit(1)
1664
1665	# topology
1666	s += '\n'
1667	s += ' topology {\n'
1668	s += ' #address-cells = <2>;\n'
1669	s += ' #size-cells = <0>;\n'
1670	for cluster in self.clusters:
1671	s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y)
1672	s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y)
1673	s += ' devices = <\n'
1674
1675	offset = ((cluster.x << self.y_width) + cluster.y) << self.p_width
1676	for proc in cluster.procs:
1677	s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid)
1678	for periph in cluster.periphs:
1679	s += ' &{/%s@0x%x}\n' % (periph.pseg.name, periph.pseg.base)
1680	for pseg in cluster.psegs:
1681	if ( pseg.segtype == 'RAM' ):
1682	s += ' &{/%s@0x%x}\n' % (pseg.name, pseg.base)
1683
1684	s += ' >;\n'
1685	s += ' };\n'
1686	s += ' };\n'
1687	s += '};\n'
1688
1689	return s
1690	# end netbsd_dts()
1691
1692	######################################################################
1693	def almos_archinfo( self ): # compute string for arch.info file
1694	# used for almos configuration
1695	# header
1696	s = '# arch.info file generated by genmap for %s\n' % self.name
1697	s += '\n'
1698	s += '[HEADER]\n'
1699	s += ' REVISION=1\n'
1700	s += ' ARCH=%s\n' % self.name
1701	s += ' XMAX=%d\n' % self.x_size
1702	s += ' YMAX=%d\n' % self.y_size
1703	s += ' CPU_NR=%d\n' % self.nprocs
1704	s += '\n'
1705
1706	# clusters
1707	cluster_id = 0
1708	for cluster in self.clusters:
1709
1710	ram = None
1711	nb_cpus = len( cluster.procs )
1712	nb_devs = len( cluster.periphs )
1713
1714	# search a RAM
1715	for pseg in cluster.psegs:
1716	if ( pseg.segtype == 'RAM' ):
1717	ram = pseg
1718	nb_devs += 1
1719
1720	# search XCU to get IRQs indexes if cluster contains peripherals
1721	if ( len( cluster.periphs ) != 0 ):
1722	tty_irq_id = None
1723	bdv_irq_id = None
1724	dma_irq_id = None
1725
1726	for periph in cluster.periphs:
1727	if ( periph.ptype == 'XCU' ):
1728	# scan irqs
1729	for irq in periph.irqs:
1730	if (irq.isrtype=='ISR_TTY_RX'): tty_irq_id = irq.srcid
1731	if (irq.isrtype=='ISR_BDV' ): bdv_irq_id = irq.srcid
1732	if (irq.isrtype=='ISR_DMA' ): dma_irq_id = irq.srcid
1733
1734	# Build the cluster description
1735	s += '[CLUSTER]\n'
1736	s += ' CID=%d\n' % cluster_id
1737	s += ' ARCH_CID=0x%x\n' % ((cluster.x<<self.y_width)+cluster.y)
1738	s += ' CPU_NR=%d\n' % nb_cpus
1739	s += ' DEV_NR=%d\n' % nb_devs
1740
1741
1742	# Handling RAM when cluster contain a RAM
1743	if (ram != None ):
1744	base = ram.base
1745	size = ram.size
1746	irqid = -1
1747	s += ' DEVID=RAM'
1748	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % (base,size)
1749
1750	# Handling peripherals
1751	for periph in cluster.periphs:
1752	base = periph.pseg.base
1753	size = periph.pseg.size
1754
1755	if ( periph.ptype == 'XCU' ):
1756
1757	s += ' DEVID=XICU'
1758	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' %(base,size)
1759
1760	elif ( (periph.ptype == 'TTY')
1761	and (tty_irq_id != None) ):
1762
1763	s += ' DEVID=TTY'
1764	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' %(base,size,tty_irq_id)
1765
1766	elif ( (periph.ptype == 'DMA')
1767	and (dma_irq_id != None) ):
1768
1769	s += ' DEVID=DMA'
1770	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' %(base,size,dma_irq_id)
1771
1772	elif ( periph.ptype == 'FBF' ):
1773
1774	s += ' DEVID=FB'
1775	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' %(base,size )
1776
1777	elif ( (periph.ptype == 'IOC') and (periph.subtype == 'BDV')
1778	and (bdv_irq_id != None) ):
1779
1780	s += ' DEVID=BLKDEV'
1781	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' %(base,size,bdv_irq_id)
1782
1783	elif ( periph.ptype == 'PIC' ):
1784
1785	s += ' DEVID=IOPIC'
1786	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' %(base,size)
1787
1788	else:
1789	print '# Warning from almos_archinfo() in cluster[%d,%d]' \
1790	% (cluster.x, cluster.y)
1791	print '# peripheral type %s/%s not supported yet\n' \
1792	% ( periph.ptype, periph.subtype )
1793
1794	cluster_id += 1
1795
1796	return s
1797
1798	# end of almos_archinfo()
1799
1800
1801
1802
1803
1804
1805
1806
1807	###################################################################################
1808	class Cluster ( object ):
1809	###################################################################################
1810	def __init__( self,
1811	x,
1812	y ):
1813
1814	self.index = 0 # global index (set by Mapping constructor)
1815	self.x = x # x coordinate
1816	self.y = y # y coordinate
1817	self.psegs = [] # filled by addRam() or addPeriph()
1818	self.procs = [] # filled by addProc()
1819	self.periphs = [] # filled by addPeriph()
1820
1821	return
1822
1823	################
1824	def xml( self ): # xml for a cluster
1825
1826	s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y)
1827	for pseg in self.psegs: s += pseg.xml()
1828	for proc in self.procs: s += proc.xml()
1829	for peri in self.periphs: s += peri.xml()
1830	s += ' </cluster>\n'
1831
1832	return s
1833
1834	#############################################
1835	def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster
1836
1837	if ( verbose ):
1838	print '*** cbin for cluster [%d,%d]' % (self.x, self.y)
1839
1840	# check index
1841	if (self.index != expected):
1842	print '[genmap error] in Cluster.cbin()'
1843	print ' cluster global index = %d / expected = %d' \
1844	% (self.index,expected)
1845	sys.exit(1)
1846
1847	# compute global index for first pseg
1848	if ( len(self.psegs) > 0 ):
1849	pseg_id = self.psegs[0].index
1850	else:
1851	pseg_id = 0
1852
1853	# compute global index for first proc
1854	if ( len(self.procs) > 0 ):
1855	proc_id = self.procs[0].index
1856	else:
1857	proc_id = 0
1858
1859	# compute global index for first periph
1860	if ( len(self.periphs) > 0 ):
1861	periph_id = self.periphs[0].index
1862	else:
1863	periph_id = 0
1864
1865	byte_stream = bytearray()
1866	byte_stream += mapping.int2bytes(4,self.x) # x coordinate
1867	byte_stream += mapping.int2bytes(4,self.y) # x coordinate
1868	byte_stream += mapping.int2bytes(4,len(self.psegs)) # psegs in cluster
1869	byte_stream += mapping.int2bytes(4,pseg_id ) # global index
1870	byte_stream += mapping.int2bytes(4,len(self.procs)) # procs in cluster
1871	byte_stream += mapping.int2bytes(4,proc_id ) # global index
1872	byte_stream += mapping.int2bytes(4,len(self.periphs)) # periphs in cluster
1873	byte_stream += mapping.int2bytes(4, periph_id ) # global index
1874
1875	if ( verbose ):
1876	print 'nb_psegs = %d' % len( self.psegs )
1877	print 'pseg_id = %d' % pseg_id
1878	print 'nb_procs = %d' % len( self.procs )
1879	print 'proc_id = %d' % proc_id
1880	print 'nb_periphs = %d' % len( self.periphs )
1881	print 'periph_id = %d' % periph_id
1882
1883	return byte_stream
1884
1885	##################################################################################
1886	class Vspace( object ):
1887	##################################################################################
1888	def __init__( self,
1889	name,
1890	startname ):
1891
1892	self.index = 0 # global index ( set by addVspace() )
1893	self.name = name # vspace name
1894	self.startname = startname # name of vseg containing the start_vector
1895	self.vsegs = []
1896	self.tasks = []
1897
1898	return
1899
1900	################
1901	def xml( self ): # xml for one vspace
1902
1903	s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname )
1904	for vseg in self.vsegs: s += vseg.xml()
1905	for task in self.tasks: s += task.xml()
1906	s += ' </vspace>\n'
1907
1908	return s
1909
1910	#############################################
1911	def cbin( self, mapping, verbose, expected ): # C binary for Vspace
1912
1913	if ( verbose ):
1914	print '*** cbin for vspace %s' % (self.name)
1915
1916	# check index
1917	if (self.index != expected):
1918	print '[genmap error] in Vspace.cbin()'
1919	print ' vspace global index = %d / expected = %d' \
1920	%(self.index,expected)
1921	sys.exit(1)
1922
1923	# compute global index for vseg containing start_vector
1924	vseg_start_id = 0xFFFFFFFF
1925	for vseg in self.vsegs:
1926	if ( vseg.name == self.startname ): vseg_start_id = vseg.index
1927
1928	if ( vseg_start_id == 0xFFFFFFFF ):
1929	print '[genmap error] in Vspace.cbin()'
1930	print ' startname %s not found for vspace %s' \
1931	%(self.startname,self.name)
1932	sys.exit(1)
1933
1934	# compute first vseg and first task global index
1935	first_vseg_id = self.vsegs[0].index
1936	first_task_id = self.tasks[0].index
1937
1938	# compute number of tasks and number of vsegs
1939	nb_vsegs = len( self.vsegs )
1940	nb_tasks = len( self.tasks )
1941
1942	byte_stream = bytearray()
1943	byte_stream += mapping.str2bytes(32,self.name) # vspace name
1944	byte_stream += mapping.int2bytes(4, vseg_start_id) # vseg start_vector
1945	byte_stream += mapping.int2bytes(4, nb_vsegs) # number of vsegs
1946	byte_stream += mapping.int2bytes(4, nb_tasks) # number of tasks
1947	byte_stream += mapping.int2bytes(4, first_vseg_id) # global index
1948	byte_stream += mapping.int2bytes(4, first_task_id) # global index
1949
1950	if ( verbose ):
1951	print 'start_id = %d' % vseg_start_id
1952	print 'nb_vsegs = %d' % nb_vsegs
1953	print 'nb_tasks = %d' % nb_tasks
1954	print 'vseg_id = %d' % first_vseg_id
1955	print 'task_id = %d' % first_task_id
1956
1957	return byte_stream
1958
1959	##################################################################################
1960	class Task( object ):
1961	##################################################################################
1962	def __init__( self,
1963	name,
1964	trdid,
1965	x,
1966	y,
1967	p,
1968	stackname,
1969	heapname,
1970	startid ):
1971
1972	self.index = 0 # global index value set by addTask()
1973	self.name = name # tsk name
1974	self.trdid = trdid # task index (unique in vspace)
1975	self.x = x # cluster x coordinate
1976	self.y = y # cluster y coordinate
1977	self.p = p # processor local index
1978	self.stackname = stackname # name of vseg containing the stack
1979	self.heapname = heapname # name of vseg containing the heap
1980	self.startid = startid # index in start_vector
1981	return
1982
1983	######################################
1984	def xml( self ): # xml for one task
1985
1986	s = ' <task name="%s"' % self.name
1987	s += ' trdid="%d"' % self.trdid
1988	s += ' x="%d"' % self.x
1989	s += ' y="%d"' % self.y
1990	s += ' p="%d"' % self.p
1991	s += '\n '
1992	s += ' stackname="%s"' % self.stackname
1993	s += ' heapname="%s"' % self.heapname
1994	s += ' startid="%d"' % self.startid
1995	s += ' />\n'
1996
1997	return s
1998
1999	##########################################################################
2000	def cbin( self, mapping, verbose, expected, vspace ): # C binary for Task
2001
2002	if ( verbose ):
2003	print '*** cbin for task %s in vspace %s' \
2004	% (self.name, vspace.name)
2005
2006	# check index
2007	if (self.index != expected):
2008	print '[genmap error] in Task.cbin()'
2009	print ' task global index = %d / expected = %d' \
2010	%(self.index,expected)
2011	sys.exit(1)
2012
2013	# compute cluster global index
2014	cluster_id = (self.x * mapping.y_size) + self.y
2015
2016	# compute vseg index for stack
2017	vseg_stack_id = 0xFFFFFFFF
2018	for vseg in vspace.vsegs:
2019	if ( vseg.name == self.stackname ): vseg_stack_id = vseg.index
2020
2021	if ( vseg_stack_id == 0xFFFFFFFF ):
2022	print '[genmap error] in Task.cbin()'
2023	print ' stackname %s not found for task %s in vspace %s' \
2024	% ( self.stackname, self.name, vspace.name )
2025	sys.exit(1)
2026
2027	# compute vseg index for heap
2028	if ( self.heapname == '' ):
2029	vseg_heap_id = 0
2030	else:
2031	vseg_heap_id = 0xFFFFFFFF
2032	for vseg in vspace.vsegs:
2033	if ( vseg.name == self.heapname ): vseg_heap_id = vseg.index
2034
2035	if ( vseg_heap_id == 0xFFFFFFFF ):
2036	print '[genmap error] in Task.cbin()'
2037	print ' heapname %s not found for task %s in vspace %s' \
2038	% ( self.heapname, self.name, vspace.name )
2039	sys.exit(1)
2040
2041	byte_stream = bytearray()
2042	byte_stream += mapping.str2bytes(32,self.name) # task name in vspace
2043	byte_stream += mapping.int2bytes(4, cluster_id) # cluster global index
2044	byte_stream += mapping.int2bytes(4, self.p) # processor local index
2045	byte_stream += mapping.int2bytes(4, self.trdid) # thread index in vspace
2046	byte_stream += mapping.int2bytes(4, vseg_stack_id) # stack vseg local index
2047	byte_stream += mapping.int2bytes(4, vseg_heap_id) # heap vseg local index
2048	byte_stream += mapping.int2bytes(4, self.startid) # index in start vector
2049
2050	if ( verbose ):
2051	print 'clusterid = %d' % cluster_id
2052	print 'lpid = %d' % self.p
2053	print 'trdid = %d' % self.trdid
2054	print 'stackid = %d' % vseg_stack_id
2055	print 'heapid = %d' % vseg_heap_id
2056	print 'startid = %d' % self.startid
2057
2058	return byte_stream
2059
2060	##################################################################################
2061	class Vseg( object ):
2062	##################################################################################
2063	def __init__( self,
2064	name,
2065	vbase,
2066	length,
2067	mode,
2068	vtype,
2069	x,
2070	y,
2071	pseg,
2072	identity = False,
2073	local = False,
2074	big = False,
2075	binpath = '' ):
2076
2077	assert (vbase & 0xFFFFFFFF) == vbase
2078
2079	assert (length & 0xFFFFFFFF) == length
2080
2081	assert mode in VSEGMODES
2082
2083	assert vtype in VSEGTYPES
2084
2085	assert (vtype != 'ELF') or (binpath != '')
2086
2087	self.index = 0 # global index ( set by addVseg() )
2088	self.name = name # vseg name (unique in vspace)
2089	self.vbase = vbase # virtual base address in vspace
2090	self.length = length # vseg length (bytes)
2091	self.vtype = vtype # vseg type (defined in VSEGTYPES)
2092	self.mode = mode # CXWU access rights
2093	self.x = x # x coordinate of destination cluster
2094	self.y = y # y coordinate of destination cluster
2095	self.psegname = pseg # name of pseg in destination cluster
2096	self.identity = identity # identity mapping required
2097	self.local = local # only mapped in local PTAB when true
2098	self.big = big # to be mapped in a big physical page
2099	self.binpath = binpath # pathname for binary file (ELF or BLOB)
2100
2101	return
2102
2103	##################################
2104	def xml( self ): # xml for a vseg
2105
2106	s = ' <vseg name="%s"' %(self.name)
2107	s += ' vbase="0x%x"' %(self.vbase)
2108	s += ' length="0x%x"' %(self.length)
2109	s += ' type="%s"' %(self.vtype)
2110	s += ' mode="%s"' %(self.mode)
2111	s += '\n '
2112	s += ' x="%d"' %(self.x)
2113	s += ' y="%d"' %(self.y)
2114	s += ' psegname="%s"' %(self.psegname)
2115	if ( self.identity ): s += ' ident="1"'
2116	if ( self.local ): s += ' local="1"'
2117	if ( self.big ): s += ' big="1"'
2118	if ( self.binpath != '' ): s += ' binpath="%s"' %(self.binpath)
2119	s += ' />\n'
2120
2121	return s
2122
2123	#####################################################################
2124	def cbin( self, mapping, verbose, expected ): # C binary for Vseg
2125
2126	if ( verbose ):
2127	print '*** cbin for vseg[%d] %s' % (self.index, self.name)
2128
2129	# check index
2130	if (self.index != expected):
2131	print '[genmap error] in Vseg.cbin()'
2132	print ' vseg global index = %d / expected = %d' \
2133	% (self.index, expected )
2134	sys.exit(1)
2135
2136	# compute pseg_id
2137	pseg_id = 0xFFFFFFFF
2138	cluster_id = (self.x * mapping.y_size) + self.y
2139	cluster = mapping.clusters[cluster_id]
2140	for pseg in cluster.psegs:
2141	if (self.psegname == pseg.name):
2142	pseg_id = pseg.index
2143	if (pseg_id == 0xFFFFFFFF):
2144	print '[genmap error] in Vseg.cbin() : '
2145	print ' psegname %s not found for vseg %s in cluster %d' \
2146	% ( self.psegname, self.name, cluster_id )
2147	sys.exit(1)
2148
2149	# compute numerical value for mode
2150	mode_id = 0xFFFFFFFF
2151	for x in xrange( len(VSEGMODES) ):
2152	if ( self.mode == VSEGMODES[x] ):
2153	mode_id = x
2154	if ( mode_id == 0xFFFFFFFF ):
2155	print '[genmap error] in Vseg.cbin() : '
2156	print ' undefined vseg mode %s' % self.mode
2157	sys.exit(1)
2158
2159	# compute numerical value for vtype
2160	vtype_id = 0xFFFFFFFF
2161	for x in xrange( len(VSEGTYPES) ):
2162	if ( self.vtype == VSEGTYPES[x] ):
2163	vtype_id = x
2164	if ( vtype_id == 0xFFFFFFFF ):
2165	print '[genmap error] in Vseg.cbin()'
2166	print ' undefined vseg type %s' % self.vtype
2167	sys.exit(1)
2168
2169	byte_stream = bytearray()
2170	byte_stream += mapping.str2bytes(32,self.name ) # vseg name
2171	byte_stream += mapping.str2bytes(64,self.binpath ) # binpath
2172	byte_stream += mapping.int2bytes(4, self.vbase ) # virtual base address
2173	byte_stream += mapping.int2bytes(8, 0 ) # physical base address
2174	byte_stream += mapping.int2bytes(4, self.length ) # vseg size (bytes)
2175	byte_stream += mapping.int2bytes(4, pseg_id ) # pseg global index
2176	byte_stream += mapping.int2bytes(4, mode_id ) # CXWU flags
2177	byte_stream += mapping.int2bytes(4, vtype_id ) # vseg type
2178	byte_stream += mapping.int2bytes(1, 0 ) # mapped when non zero
2179	byte_stream += mapping.int2bytes(1, self.identity ) # identity mapping
2180	byte_stream += mapping.int2bytes(1, self.local ) # only in local PTAB
2181	byte_stream += mapping.int2bytes(1, self.big ) # to be mapped in BPP
2182
2183	if ( verbose ):
2184	print 'binpath = %s' % self.binpath
2185	print 'vbase = %x' % self.vbase
2186	print 'pbase = 0'
2187	print 'length = %x' % self.length
2188	print 'pseg_id = %d' % pseg_id
2189	print 'mode = %d' % mode_id
2190	print 'type = %d' % vtype_id
2191	print 'mapped = 0'
2192	print 'ident = %d' % self.identity
2193	print 'local = %d' % self.local
2194	print 'big = %d' % self.big
2195
2196	return byte_stream
2197
2198	##################################################################################
2199	class Processor ( object ):
2200	##################################################################################
2201	def __init__( self,
2202	x,
2203	y,
2204	lpid ):
2205
2206	self.index = 0 # global index ( set by addProc() )
2207	self.x = x # x cluster coordinate
2208	self.y = y # y cluster coordinate
2209	self.lpid = lpid # processor local index
2210
2211	return
2212
2213	########################################
2214	def xml( self ): # xml for a processor
2215	return ' <proc index="%d" />\n' % (self.lpid)
2216
2217	####################################################################
2218	def cbin( self, mapping, verbose, expected ): # C binary for Proc
2219
2220	if ( verbose ):
2221	print '*** cbin for proc %d in cluster (%d,%d)' \
2222	% (self.lpid, self.x, self.y)
2223
2224	# check index
2225	if (self.index != expected):
2226	print '[genmap error] in Proc.cbin()'
2227	print ' proc global index = %d / expected = %d' \
2228	% (self.index,expected)
2229	sys.exit(1)
2230
2231	byte_stream = bytearray()
2232	byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index
2233
2234	return byte_stream
2235
2236	##################################################################################
2237	class Pseg ( object ):
2238	##################################################################################
2239	def __init__( self,
2240	name,
2241	base,
2242	size,
2243	x,
2244	y,
2245	segtype ):
2246
2247	assert( segtype in PSEGTYPES )
2248
2249	self.index = 0 # global index ( set by addPseg() )
2250	self.name = name # pseg name (unique in cluster)
2251	self.base = base # physical base address
2252	self.size = size # segment size (bytes)
2253	self.x = x # cluster x coordinate
2254	self.y = y # cluster y coordinate
2255	self.segtype = segtype # RAM / PERI (defined in mapping_info.h)
2256
2257	return
2258
2259	###################################
2260	def xml( self ): # xml for a pseg
2261
2262	s = ' <pseg name="%s" type="%s" base="0x%x" length="0x%x" />\n' \
2263	% (self.name, self.segtype, self.base, self.size)
2264	return s
2265
2266	###########################################################################
2267	def cbin( self, mapping, verbose, expected, cluster ): # C binary for Pseg
2268
2269	if ( verbose ):
2270	print '*** cbin for pseg[%d] %s in cluster[%d,%d]' \
2271	% (self.index, self.name, cluster.x, cluster.y)
2272
2273	# check index
2274	if (self.index != expected):
2275	print '[genmap error] in Pseg.cbin()'
2276	print ' pseg global index = %d / expected = %d' \
2277	% (self.index,expected)
2278	sys.exit(1)
2279
2280	# compute numerical value for segtype
2281	segtype_int = 0xFFFFFFFF
2282	for x in xrange( len(PSEGTYPES) ):
2283	if ( self.segtype == PSEGTYPES[x] ): segtype_int = x
2284
2285	if ( segtype_int == 0xFFFFFFFF ):
2286	print '[genmap error] in Pseg.cbin()'
2287	print ' undefined segment type %s' % self.segtype
2288	sys.exit(1)
2289
2290	byte_stream = bytearray()
2291	byte_stream += mapping.str2bytes(32,self.name) # pseg name
2292	byte_stream += mapping.int2bytes(8 ,self.base) # physical base address
2293	byte_stream += mapping.int2bytes(8 ,self.size) # segment length
2294	byte_stream += mapping.int2bytes(4 ,segtype_int) # segment type
2295	byte_stream += mapping.int2bytes(4 ,cluster.index) # cluster global index
2296	byte_stream += mapping.int2bytes(4 ,0) # linked list of vsegs
2297
2298	if ( verbose ):
2299	print 'pbase = %x' % self.base
2300	print 'size = %x' % self.size
2301	print 'type = %s' % self.segtype
2302
2303	return byte_stream
2304
2305	##################################################################################
2306	class Periph ( object ):
2307	##################################################################################
2308	def __init__( self,
2309	pseg, # associated pseg
2310	ptype, # peripheral type
2311	subtype = 'NONE', # peripheral subtype
2312	channels = 1, # for multi-channels peripherals
2313	arg0 = 0, # optional (semantic depends on ptype)
2314	arg1 = 0, # optional (semantic depends on ptype)
2315	arg2 = 0, # optional (semantic depends on ptype)
2316	arg3 = 0 ): # optional (semantic depends on ptype)
2317
2318	self.index = 0 # global index ( set by addPeriph() )
2319	self.channels = channels
2320	self.ptype = ptype
2321	self.subtype = subtype
2322	self.arg0 = arg0
2323	self.arg1 = arg1
2324	self.arg2 = arg2
2325	self.arg3 = arg3
2326	self.pseg = pseg
2327	self.irqs = []
2328	return
2329
2330	######################################
2331	def xml( self ): # xml for a periph
2332
2333	s = ' <periph type="%s"' % self.ptype
2334	s += ' subtype="%s"' % self.subtype
2335	s += ' psegname="%s"' % self.pseg.name
2336	s += ' channels="%d"' % self.channels
2337	s += ' arg0="%d"' % self.arg0
2338	s += ' arg1="%d"' % self.arg1
2339	s += ' arg2="%d"' % self.arg2
2340	s += ' arg3="%d"' % self.arg3
2341	if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') ):
2342	s += ' >\n'
2343	for irq in self.irqs: s += irq.xml()
2344	s += ' </periph>\n'
2345	else:
2346	s += ' />\n'
2347	return s
2348
2349	######################################################################
2350	def cbin( self, mapping, verbose, expected ): # C binary for Periph
2351
2352	if ( verbose ):
2353	print '*** cbin for periph %s in cluster [%d,%d]' \
2354	% (self.ptype, self.pseg.x, self.pseg.y)
2355
2356	# check index
2357	if (self.index != expected):
2358	print '[genmap error] in Periph.cbin()'
2359	print ' periph global index = %d / expected = %d' \
2360	% (self.index,expected)
2361	sys.exit(1)
2362
2363	# compute pseg global index
2364	pseg_id = self.pseg.index
2365
2366	# compute first irq global index
2367	if ( len(self.irqs) > 0 ):
2368	irq_id = self.irqs[0].index
2369	else:
2370	irq_id = 0
2371
2372	# compute numerical value for ptype
2373	ptype_id = 0xFFFFFFFF
2374	for x in xrange( len(PERIPHTYPES) ):
2375	if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x
2376
2377	if ( ptype_id == 0xFFFFFFFF ):
2378	print '[genmap error] in Periph.cbin()'
2379	print ' undefined peripheral type %s' % self.ptype
2380	sys.exit(1)
2381
2382	# compute numerical value for subtype
2383	subtype_id = 0xFFFFFFFF
2384	if (self.ptype == 'IOC'):
2385	for x in xrange( len(IOCSUBTYPES) ):
2386	if ( self.subtype == IOCSUBTYPES[x] ): subtype_id = x
2387	if (self.ptype == 'MWR'):
2388	for x in xrange( len(MWRSUBTYPES) ):
2389	if ( self.subtype == MWRSUBTYPES[x] ): subtype_id = x
2390
2391	byte_stream = bytearray()
2392	byte_stream += mapping.int2bytes(4,ptype_id) # peripheral type
2393	byte_stream += mapping.int2bytes(4,subtype_id) # peripheral subtype
2394	byte_stream += mapping.int2bytes(4,pseg_id) # pseg global index
2395	byte_stream += mapping.int2bytes(4,self.channels) # number of channels
2396	byte_stream += mapping.int2bytes(4,self.arg0) # optionnal arg0
2397	byte_stream += mapping.int2bytes(4,self.arg1) # optionnal arg1
2398	byte_stream += mapping.int2bytes(4,self.arg2) # optionnal arg2
2399	byte_stream += mapping.int2bytes(4,self.arg3) # optionnal arg3
2400	byte_stream += mapping.int2bytes(4,len(self.irqs)) # number of input irqs
2401	byte_stream += mapping.int2bytes( 4 , irq_id ) # global index
2402
2403	if ( verbose ):
2404	print 'ptype = %d' % ptype_id
2405	print 'subtype = %d' % subtype_id
2406	print 'pseg_id = %d' % pseg_id
2407	print 'nb_irqs = %d' % len( self.irqs )
2408	print 'irq_id = %d' % irq_id
2409	return byte_stream
2410
2411	##################################################################################
2412	class Irq ( object ):
2413	##################################################################################
2414	def __init__( self,
2415	irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only)
2416	srcid, # input IRQ index (for XCU or PIC)
2417	isrtype, # Type of ISR to be executed
2418	channel = 0 ): # channel index for multi-channel ISR
2419
2420	assert irqtype in IRQTYPES
2421	assert isrtype in ISRTYPES
2422	assert srcid < 32
2423
2424	self.index = 0 # global index ( set by addIrq() )
2425	self.irqtype = irqtype # IRQ type
2426	self.srcid = srcid # source IRQ index
2427	self.isrtype = isrtype # ISR type
2428	self.channel = channel # channel index (for multi-channels ISR)
2429	return
2430
2431	################################
2432	def xml( self ): # xml for Irq
2433
2434	s = ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" />\n' \
2435	% ( self.irqtype, self.srcid, self.isrtype, self.channel )
2436	return s
2437
2438	####################################################################
2439	def cbin( self, mapping, verbose, expected ): # C binary for Irq
2440
2441	if ( verbose ):
2442	print '*** cbin for irq[%d]' % (self.index)
2443
2444	# check index
2445	if (self.index != expected):
2446	print '[genmap error] in Irq.cbin()'
2447	print ' irq global index = %d / expected = %d' \
2448	% (self.index,expected)
2449	sys.exit(1)
2450
2451	# compute numerical value for irqtype
2452	irqtype_id = 0xFFFFFFFF
2453	for x in xrange( len(IRQTYPES) ):
2454	if ( self.irqtype == IRQTYPES[x] ): irqtype_id = x
2455
2456	if ( irqtype_id == 0xFFFFFFFF ):
2457	print '[genmap error] in Irq.cbin()'
2458	print ' undefined irqtype %s' % self.irqtype
2459	sys.exit(1)
2460
2461	# compute numerical value for isrtype
2462	isrtype_id = 0xFFFFFFFF
2463	for x in xrange( len(ISRTYPES) ):
2464	if ( self.isrtype == ISRTYPES[x] ): isrtype_id = x
2465
2466	if ( isrtype_id == 0xFFFFFFFF ):
2467	print '[genmap error] in Irq.cbin()'
2468	print ' undefined isrtype %s' % self.isrtype
2469	sys.exit(1)
2470
2471	byte_stream = bytearray()
2472	byte_stream += mapping.int2bytes( 4, irqtype_id )
2473	byte_stream += mapping.int2bytes( 4, self.srcid )
2474	byte_stream += mapping.int2bytes( 4, isrtype_id )
2475	byte_stream += mapping.int2bytes( 4, self.channel )
2476	byte_stream += mapping.int2bytes( 4, 0 )
2477	byte_stream += mapping.int2bytes( 4, 0 )
2478
2479	if ( verbose ):
2480	print 'irqtype = %s' % self.irqtype
2481	print 'srcid = %d' % self.srcid
2482	print 'isrtype = %s' % self.isrtype
2483	print 'channel = %d' % self.channel
2484
2485	return byte_stream
2486
2487	# Local Variables:
2488	# tab-width: 4;
2489	# c-basic-offset: 4;
2490	# c-file-offsets:((innamespace . 0)(inline-open . 0));
2491	# indent-tabs-mode: nil;
2492	# End:
2493	#
2494	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
2495

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