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source: soft/giet_vm/giet_python/mapping.py @ 641

Last change on this file since 641 was 633, checked in by alain, 9 years ago
Introduce support for the new field "ltid" in the "mapping_task_t" structure.
Property svn:executable set to ``*
File size: 101.4 KB

Line
1	#!/usr/bin/env python
2
3	import sys
4
5	###################################################################################
6	# file : giet_mapping.py
7	# date : april 2014
8	# author : Alain Greiner
9	###################################################################################
10	# This file contains the classes required to define a mapping for the GIET_VM.
11	# - A 'Mapping' contains a set of 'Cluster' (hardware architecture)
12	# a set of 'Vseg' (kernel glogals virtual segments)
13	# a set of 'Vspace' (one or several user applications)
14	# - A 'Cluster' contains a set of 'Pseg' (physical segments in cluster)
15	# a set of 'Proc' (processors in cluster)
16	# a set of 'Periph' (peripherals in cluster)
17	# - A 'Vspace' contains a set of 'Vseg' (user virtual segments)
18	# a set of 'Task' (user parallel tasks)
19	# - A 'Periph' contains a set of 'Irq' (only for XCU and PIC types )
20	###################################################################################
21	# Implementation Note
22	# The objects used to describe a mapping are distributed in the PYTHON structure:
23	# For example the psegs set is split in several subsets (one subset per cluster),
24	# or the tasks set is split in several subsets (one subset per vspace), etc...
25	# In the C binary data structure used by the giet_vm, all objects of same type
26	# are stored in a linear array (one single array for all psegs for example).
27	# For all objects, we compute and store in the PYTHON object a "global index"
28	# corresponding to the index in this global array, and this index can be used as
29	# a pseudo-pointer to identify a specific object of a given type.
30	###################################################################################
31
32	###################################################################################
33	# Various constants
34	###################################################################################
35
36	PADDR_WIDTH = 40 # number of bits for physical address
37	X_WIDTH = 4 # number of bits encoding x coordinate
38	Y_WIDTH = 4 # number of bits encoding y coordinate
39	P_WIDTH = 4 # number of bits encoding local proc_id
40	VPN_ANTI_MASK = 0x00000FFF # mask vaddr to get offset in small page
41	BPN_MASK = 0xFFE00000 # mask vaddr to get the BPN in big page
42	PERI_INCREMENT = 0x10000 # virtual address increment for replicated vsegs
43	RESET_ADDRESS = 0xBFC00000 # Processor wired boot_address
44	MAPPING_SIGNATURE = 0xDACE2014 # Magic number indicating a valid C BLOB
45
46	###################################################################################
47	# These lists must be consistent with values defined in
48	# mapping_info.h / xml_driver.c /xml_parser.c
49	###################################################################################
50	PERIPHTYPES = [
51	'CMA',
52	'DMA',
53	'FBF',
54	'IOB',
55	'IOC',
56	'MMC',
57	'MWR',
58	'NIC',
59	'ROM',
60	'SIM',
61	'TIM',
62	'TTY',
63	'XCU',
64	'PIC',
65	'DROM',
66	]
67
68	IOCSUBTYPES = [
69	'BDV',
70	'HBA',
71	'SDC',
72	'SPI',
73	]
74
75	MWRSUBTYPES = [
76	'GCD',
77	'DCT',
78	'CPY',
79	]
80
81	###################################################################################
82	# These lists must be consistent with values defined in
83	# irq_handler.c / irq_handler.h / xml_driver.c / xml_parser.c
84	###################################################################################
85	IRQTYPES = [
86	'HWI',
87	'WTI',
88	'PTI',
89	]
90
91	ISRTYPES = [
92	'ISR_DEFAULT',
93	'ISR_TICK',
94	'ISR_TTY_RX',
95	'ISR_TTY_TX',
96	'ISR_BDV',
97	'ISR_TIMER',
98	'ISR_WAKUP',
99	'ISR_NIC_RX',
100	'ISR_NIC_TX',
101	'ISR_CMA',
102	'ISR_MMC',
103	'ISR_DMA',
104	'ISR_SDC',
105	'ISR_MWR',
106	'ISR_HBA',
107	'ISR_SPI',
108	]
109
110	VSEGTYPES = [
111	'ELF',
112	'BLOB',
113	'PTAB',
114	'PERI',
115	'BUFFER',
116	'SCHED',
117	'HEAP',
118	]
119
120	VSEGMODES = [
121	'____',
122	'___U',
123	'__W_',
124	'__WU',
125	'_X__',
126	'_X_U',
127	'_XW_',
128	'_XWU',
129	'C___',
130	'C__U',
131	'C_W_',
132	'C_WU',
133	'CX__',
134	'CX_U',
135	'CXW_',
136	'CXWU',
137	]
138
139	PSEGTYPES = [
140	'RAM',
141	'PERI',
142	]
143
144	###################################################################################
145	class Mapping( object ):
146	###################################################################################
147	def __init__( self,
148	name, # mapping name
149	x_size, # number of clusters in a row
150	y_size, # number of clusters in a column
151	nprocs, # max number of processors per cluster
152	x_width = X_WIDTH, # number of bits encoding x coordinate
153	y_width = Y_WIDTH, # number of bits encoding y coordinate
154	p_width = P_WIDTH, # number of bits encoding lpid
155	paddr_width = PADDR_WIDTH, # number of bits for physical address
156	coherence = 1, # hardware cache coherence if non-zero
157	irq_per_proc = 1, # number or IRQs from XCU to processor
158	use_ramdisk = False, # use ramdisk when true
159	x_io = 0, # cluster_io x coordinate
160	y_io = 0, # cluster_io y coordinate
161	peri_increment = PERI_INCREMENT, # address increment for globals
162	reset_address = RESET_ADDRESS, # Processor wired boot_address
163	ram_base = 0, # RAM physical base in cluster[0,0]
164	ram_size = 0 ): # RAM size per cluster (bytes)
165
166	assert ( x_size <= (1<<X_WIDTH) )
167	assert ( y_size <= (1<<Y_WIDTH) )
168	assert ( nprocs <= (1<<P_WIDTH) )
169
170	self.signature = MAPPING_SIGNATURE
171	self.name = name
172	self.name = name
173	self.paddr_width = paddr_width
174	self.coherence = coherence
175	self.x_size = x_size
176	self.y_size = y_size
177	self.nprocs = nprocs
178	self.x_width = x_width
179	self.y_width = y_width
180	self.p_width = p_width
181	self.irq_per_proc = irq_per_proc
182	self.use_ramdisk = use_ramdisk
183	self.x_io = x_io
184	self.y_io = y_io
185	self.peri_increment = peri_increment
186	self.reset_address = reset_address
187	self.ram_base = ram_base
188	self.ram_size = ram_size
189
190	self.total_vspaces = 0
191	self.total_globals = 0
192	self.total_psegs = 0
193	self.total_vsegs = 0
194	self.total_tasks = 0
195	self.total_procs = 0
196	self.total_irqs = 0
197	self.total_periphs = 0
198
199	self.clusters = []
200	self.globs = []
201	self.vspaces = []
202
203	for x in xrange( self.x_size ):
204	for y in xrange( self.y_size ):
205	cluster = Cluster( x , y )
206	cluster.index = (x * self.y_size) + y
207	self.clusters.append( cluster )
208
209	return
210
211	########################## add a ram pseg in a cluster
212	def addRam( self,
213	name, # pseg name
214	base, # pseg base address
215	size ): # pseg length (bytes)
216
217	# computes cluster index and coordinates from the base address
218	paddr_lsb_width = self.paddr_width - self.x_width - self.y_width
219	cluster_xy = base >> paddr_lsb_width
220	x = cluster_xy >> (self.y_width);
221	y = cluster_xy & ((1 << self.y_width) - 1)
222	cluster_id = (x * self.y_size) + y
223
224	assert (base & VPN_ANTI_MASK) == 0
225
226	assert (x < self.x_size) and (y < self.y_size)
227
228	assert ( (base & ((1<<paddr_lsb_width)-1)) == self.ram_base )
229
230	assert ( size == self.ram_size )
231
232	# add one pseg in the mapping
233	pseg = Pseg( name, base, size, x, y, 'RAM' )
234	self.clusters[cluster_id].psegs.append( pseg )
235	pseg.index = self.total_psegs
236	self.total_psegs += 1
237
238	return pseg
239
240	########################## add a peripheral and the associated pseg in a cluster
241	def addPeriph( self,
242	name, # associated pseg name
243	base, # associated pseg base address
244	size, # associated pseg length (bytes)
245	ptype, # peripheral type
246	subtype = 'NONE', # peripheral subtype
247	channels = 1, # number of channels
248	arg0 = 0, # optional argument (semantic depends on ptype)
249	arg1 = 0, # optional argument (semantic depends on ptype)
250	arg2 = 0, # optional argument (semantic depends on ptype)
251	arg3 = 0 ): # optional argument (semantic depends on ptype)
252
253	# computes cluster index and coordinates from the base address
254	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
255	x = cluster_xy >> (self.y_width);
256	y = cluster_xy & ((1 << self.y_width) - 1)
257	cluster_id = (x * self.y_size) + y
258
259	assert (x < self.x_size) and (y < self.y_size)
260
261	assert (base & VPN_ANTI_MASK) == 0
262
263	assert ptype in PERIPHTYPES
264
265	if (ptype == 'IOC'): assert subtype in IOCSUBTYPES
266	if (ptype == 'MWR'): assert subtype in MWRSUBTYPES
267
268	# add one pseg into mapping
269	pseg = Pseg( name, base, size, x, y, 'PERI' )
270	self.clusters[cluster_id].psegs.append( pseg )
271	pseg.index = self.total_psegs
272	self.total_psegs += 1
273
274	# add one periph into mapping
275	periph = Periph( pseg, ptype, subtype, channels, arg0, arg1, arg2, arg3 )
276	self.clusters[cluster_id].periphs.append( periph )
277	periph.index = self.total_periphs
278	self.total_periphs += 1
279
280	return periph
281
282	################################ add an IRQ in a peripheral
283	def addIrq( self,
284	periph, # peripheral containing IRQ (PIC or XCU)
285	index, # peripheral input port index
286	src, # interrupt source peripheral
287	isrtype, # ISR type
288	channel = 0 ): # channel for multi-channels ISR
289
290	assert isrtype in ISRTYPES
291
292	assert index < 32
293
294	# add one irq into mapping
295	irq = Irq( 'HWI', index , isrtype, channel )
296	periph.irqs.append( irq )
297	irq.index = self.total_irqs
298	self.total_irqs += 1
299
300	# pointer from the source to the interrupt controller peripheral
301	if src.irq_ctrl == None: src.irq_ctrl = periph
302	if src.irq_ctrl != periph:
303	print '[genmap error] in addIrq():'
304	print ' two different interrupt controller for the same peripheral'
305	sys.exit(1)
306
307	return irq
308
309	########################## add a processor in a cluster
310	def addProc( self,
311	x, # cluster x coordinate
312	y, # cluster y coordinate
313	lpid ): # processor local index
314
315	assert (x < self.x_size) and (y < self.y_size)
316
317	cluster_id = (x * self.y_size) + y
318
319	# add one proc into mapping
320	proc = Processor( x, y, lpid )
321	self.clusters[cluster_id].procs.append( proc )
322	proc.index = self.total_procs
323	self.total_procs += 1
324
325	return proc
326
327	############################ add one global vseg into mapping
328	def addGlobal( self,
329	name, # vseg name
330	vbase, # virtual base address
331	length, # vseg length (bytes)
332	mode, # CXWU flags
333	vtype, # vseg type
334	x, # destination x coordinate
335	y, # destination y coordinate
336	pseg, # destination pseg name
337	identity = False, # identity mapping required if true
338	local = False, # only mapped in local PTAB if true
339	big = False, # to be mapped in a big physical page
340	binpath = '' ): # pathname for binary code if required
341
342	# two global vsegs must not overlap if they have different names
343	for prev in self.globs:
344	if ( ((prev.vbase + prev.length) > vbase ) and
345	((vbase + length) > prev.vbase) and
346	(prev.name[0:15] != name[0:15]) ):
347	print '[genmap error] in addGlobal()'
348	print ' global vseg %s overlap %s' % (name, prev.name)
349	print ' %s : base = %x / size = %x' %(name, vbase, length)
350	print ' %s : base = %x / size = %x' %(prev.name, prev.vbase, prev.length)
351	sys.exit(1)
352
353	# add one vseg into mapping
354	vseg = Vseg( name, vbase, length, mode, vtype, x, y, pseg,
355	identity = identity, local = local, big = big, binpath = binpath )
356
357	self.globs.append( vseg )
358	self.total_globals += 1
359	vseg.index = self.total_vsegs
360	self.total_vsegs += 1
361
362	return
363
364	################################ add a vspace into mapping
365	def addVspace( self,
366	name, # vspace name
367	startname ): # name of vseg containing start_vector
368
369	# add one vspace into mapping
370	vspace = Vspace( name, startname )
371	self.vspaces.append( vspace )
372	vspace.index = self.total_vspaces
373	self.total_vspaces += 1
374
375	return vspace
376
377	################################# add a private vseg in a vspace
378	def addVseg( self,
379	vspace, # vspace containing the vseg
380	name, # vseg name
381	vbase, # virtual base address
382	length, # vseg length (bytes)
383	mode, # CXWU flags
384	vtype, # vseg type
385	x, # destination x coordinate
386	y, # destination y coordinate
387	pseg, # destination pseg name
388	local = False, # only mapped in local PTAB if true
389	big = False, # to be mapped in a big physical page
390	binpath = '' ): # pathname for binary code
391
392	assert mode in VSEGMODES
393
394	assert vtype in VSEGTYPES
395
396	assert (x < self.x_size) and (y < self.y_size)
397
398	# add one vseg into mapping
399	vseg = Vseg( name, vbase, length, mode, vtype, x, y, pseg,
400	identity = False, local = local, big = big, binpath = binpath )
401	vspace.vsegs.append( vseg )
402	vseg.index = self.total_vsegs
403	self.total_vsegs += 1
404
405	return vseg
406
407	################################ add a task in a vspace
408	def addTask( self,
409	vspace, # vspace containing task
410	name, # task name
411	trdid, # task index in vspace
412	x, # destination x coordinate
413	y, # destination y coordinate
414	lpid, # destination processor local index
415	stackname, # name of vseg containing stack
416	heapname, # name of vseg containing heap
417	startid ): # index in start_vector
418
419	assert (x < self.x_size) and (y < self.y_size)
420	assert lpid < self.nprocs
421
422	# add one task into mapping
423	task = Task( name, trdid, x, y, lpid, stackname, heapname, startid )
424	vspace.tasks.append( task )
425	task.index = self.total_tasks
426	self.total_tasks += 1
427
428	return task
429
430	#################################
431	def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array
432
433	byte_stream = bytearray()
434	length = len( s )
435	if length < (nbytes - 1):
436	for b in s:
437	byte_stream.append( b )
438	for x in xrange(nbytes-length):
439	byte_stream.append( '\0' )
440	else:
441	print '[genmap error] in str2bytes()'
442	print ' string %s too long' % s
443	sys.exit(1)
444
445	return byte_stream
446
447	###################################
448	def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array
449
450	byte_stream = bytearray()
451	for n in xrange( nbytes ):
452	byte_stream.append( (val >> (n<<3)) & 0xFF )
453
454	return byte_stream
455
456	################
457	def xml( self ): # compute string for map.xml file generation
458
459	s = '<?xml version="1.0"?>\n\n'
460	s += '<mapping_info signature = "0x%x"\n' % (self.signature)
461	s += ' name = "%s"\n' % (self.name)
462	s += ' x_size = "%d"\n' % (self.x_size)
463	s += ' y_size = "%d"\n' % (self.y_size)
464	s += ' x_width = "%d"\n' % (self.x_width)
465	s += ' y_width = "%d"\n' % (self.y_width)
466	s += ' irq_per_proc = "%d"\n' % (self.irq_per_proc)
467	s += ' use_ramdisk = "%d"\n' % (self.use_ramdisk)
468	s += ' x_io = "%d"\n' % (self.x_io)
469	s += ' y_io = "%d" >\n' % (self.y_io)
470	s += '\n'
471
472	s += ' <clusterset>\n'
473	for x in xrange ( self.x_size ):
474	for y in xrange ( self.y_size ):
475	cluster_id = (x * self.y_size) + y
476	s += self.clusters[cluster_id].xml()
477	s += ' </clusterset>\n'
478	s += '\n'
479
480	s += ' <globalset>\n'
481	for vseg in self.globs: s += vseg.xml()
482	s += ' </globalset>\n'
483	s += '\n'
484
485	s += ' <vspaceset>\n'
486	for vspace in self.vspaces: s += vspace.xml()
487	s += ' </vspaceset>\n'
488
489	s += '</mapping_info>\n'
490	return s
491
492	##########################
493	def cbin( self, verbose ): # C binary structure for map.bin file generation
494
495	byte_stream = bytearray()
496
497	# header
498	byte_stream += self.int2bytes(4, self.signature)
499	byte_stream += self.int2bytes(4, self.x_size)
500	byte_stream += self.int2bytes(4, self.y_size)
501	byte_stream += self.int2bytes(4, self.x_width)
502	byte_stream += self.int2bytes(4, self.y_width)
503	byte_stream += self.int2bytes(4, self.x_io)
504	byte_stream += self.int2bytes(4, self.y_io)
505	byte_stream += self.int2bytes(4, self.irq_per_proc)
506	byte_stream += self.int2bytes(4, self.use_ramdisk)
507	byte_stream += self.int2bytes(4, self.total_globals)
508	byte_stream += self.int2bytes(4, self.total_vspaces)
509	byte_stream += self.int2bytes(4, self.total_psegs)
510	byte_stream += self.int2bytes(4, self.total_vsegs)
511	byte_stream += self.int2bytes(4, self.total_tasks)
512	byte_stream += self.int2bytes(4, self.total_procs)
513	byte_stream += self.int2bytes(4, self.total_irqs)
514	byte_stream += self.int2bytes(4, self.total_periphs)
515	byte_stream += self.str2bytes(64, self.name)
516
517	if ( verbose ):
518	print '\n'
519	print 'name = %s' % self.name
520	print 'signature = %x' % self.signature
521	print 'x_size = %d' % self.x_size
522	print 'y_size = %d' % self.y_size
523	print 'x_width = %d' % self.x_width
524	print 'y_width = %d' % self.y_width
525	print 'x_io = %d' % self.x_io
526	print 'y_io = %d' % self.y_io
527	print 'irq_per_proc = %d' % self.irq_per_proc
528	print 'use_ramdisk = %d' % self.use_ramdisk
529	print 'total_globals = %d' % self.total_globals
530	print 'total_psegs = %d' % self.total_psegs
531	print 'total_vsegs = %d' % self.total_vsegs
532	print 'total_tasks = %d' % self.total_tasks
533	print 'total_procs = %d' % self.total_procs
534	print 'total_irqs = %d' % self.total_irqs
535	print 'total_periphs = %d' % self.total_periphs
536	print '\n'
537
538	# clusters array
539	index = 0
540	for cluster in self.clusters:
541	byte_stream += cluster.cbin( self, verbose, index )
542	index += 1
543
544	if ( verbose ): print '\n'
545
546	# psegs array
547	index = 0
548	for cluster in self.clusters:
549	for pseg in cluster.psegs:
550	byte_stream += pseg.cbin( self, verbose, index, cluster )
551	index += 1
552
553	if ( verbose ): print '\n'
554
555	# vspaces array
556	index = 0
557	for vspace in self.vspaces:
558	byte_stream += vspace.cbin( self, verbose, index )
559	index += 1
560
561	if ( verbose ): print '\n'
562
563	# vsegs array
564	index = 0
565	for vseg in self.globs:
566	byte_stream += vseg.cbin( self, verbose, index )
567	index += 1
568	for vspace in self.vspaces:
569	for vseg in vspace.vsegs:
570	byte_stream += vseg.cbin( self, verbose, index )
571	index += 1
572
573	if ( verbose ): print '\n'
574
575	# tasks array
576	index = 0
577	for vspace in self.vspaces:
578	for task in vspace.tasks:
579	byte_stream += task.cbin( self, verbose, index, vspace )
580	index += 1
581
582	if ( verbose ): print '\n'
583
584	# procs array
585	index = 0
586	for cluster in self.clusters:
587	for proc in cluster.procs:
588	byte_stream += proc.cbin( self, verbose, index )
589	index += 1
590
591	if ( verbose ): print '\n'
592
593	# irqs array
594	index = 0
595	for cluster in self.clusters:
596	for periph in cluster.periphs:
597	for irq in periph.irqs:
598	byte_stream += irq.cbin( self, verbose, index )
599	index += 1
600
601	if ( verbose ): print '\n'
602
603	# periphs array
604	index = 0
605	for cluster in self.clusters:
606	for periph in cluster.periphs:
607	byte_stream += periph.cbin( self, verbose, index )
608	index += 1
609
610	return byte_stream
611	# end of cbin()
612
613	#######################################################################
614	def giet_vsegs( self ): # compute string for giet_vsegs.ld file
615	# required by giet_vm compilation
616
617	# search the vsegs required for the giet_vsegs.ld
618	boot_code_found = False
619	boot_data_found = False
620	kernel_uncdata_found = False
621	kernel_data_found = False
622	kernel_code_found = False
623	kernel_init_found = False
624	for vseg in self.globs:
625
626	if ( vseg.name[0:13] == 'seg_boot_code' ):
627	boot_code_vbase = vseg.vbase
628	boot_code_size = vseg.length
629	boot_code_found = True
630
631	if ( vseg.name[0:13] == 'seg_boot_data' ):
632	boot_data_vbase = vseg.vbase
633	boot_data_size = vseg.length
634	boot_data_found = True
635
636	if ( vseg.name[0:15] == 'seg_kernel_data' ):
637	kernel_data_vbase = vseg.vbase
638	kernel_data_size = vseg.length
639	kernel_data_found = True
640
641	if ( vseg.name[0:15] == 'seg_kernel_code' ):
642	kernel_code_vbase = vseg.vbase
643	kernel_code_size = vseg.length
644	kernel_code_found = True
645
646	if ( vseg.name[0:15] == 'seg_kernel_init' ):
647	kernel_init_vbase = vseg.vbase
648	kernel_init_size = vseg.length
649	kernel_init_found = True
650
651	# check if all required vsegs have been found
652	if ( boot_code_found == False ):
653	print '[genmap error] in giet_vsegs()'
654	print ' seg_boot_code vseg missing'
655	sys.exit()
656
657	if ( boot_data_found == False ):
658	print '[genmap error] in giet_vsegs()'
659	print ' seg_boot_data vseg missing'
660	sys.exit()
661
662	if ( kernel_data_found == False ):
663	print '[genmap error] in giet_vsegs()'
664	print ' seg_kernel_data vseg missing'
665	sys.exit()
666
667	if ( kernel_code_found == False ):
668	print '[genmap error] in giet_vsegs()'
669	print ' seg_kernel_code vseg missing'
670	sys.exit()
671
672	if ( kernel_init_found == False ):
673	print '[genmap error] in giet_vsegs()'
674	print ' seg_kernel_init vseg missing'
675	sys.exit()
676
677	# build string
678	s = '/* Generated by genmap for %s */\n' % self.name
679	s += '\n'
680
681	s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase
682	s += 'boot_code_size = 0x%x;\n' % boot_code_size
683	s += '\n'
684	s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase
685	s += 'boot_data_size = 0x%x;\n' % boot_data_size
686	s += '\n'
687	s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase
688	s += 'kernel_code_size = 0x%x;\n' % kernel_code_size
689	s += '\n'
690	s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase
691	s += 'kernel_data_size = 0x%x;\n' % kernel_data_size
692	s += '\n'
693	s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase
694	s += 'kernel_init_size = 0x%x;\n' % kernel_init_size
695	s += '\n'
696
697	return s
698
699	######################################################################
700	def hard_config( self ): # compute string for hard_config.h file
701	# required by
702	# - top.cpp compilation
703	# - giet_vm compilation
704	# - tsar_preloader compilation
705
706	nb_total_procs = 0
707
708	# for each peripheral type, define default values
709	# for pbase address, size, number of components, and channels
710	nb_cma = 0
711	cma_channels = 0
712	seg_cma_base = 0xFFFFFFFF
713	seg_cma_size = 0
714
715	nb_dma = 0
716	dma_channels = 0
717	seg_dma_base = 0xFFFFFFFF
718	seg_dma_size = 0
719
720	nb_fbf = 0
721	fbf_channels = 0
722	seg_fbf_base = 0xFFFFFFFF
723	seg_fbf_size = 0
724	fbf_arg0 = 0
725	fbf_arg1 = 0
726
727	nb_iob = 0
728	iob_channels = 0
729	seg_iob_base = 0xFFFFFFFF
730	seg_iob_size = 0
731
732	nb_ioc = 0
733	ioc_channels = 0
734	seg_ioc_base = 0xFFFFFFFF
735	seg_ioc_size = 0
736	use_ioc_bdv = False
737	use_ioc_sdc = False
738	use_ioc_hba = False
739	use_ioc_spi = False
740
741	nb_mmc = 0
742	mmc_channels = 0
743	seg_mmc_base = 0xFFFFFFFF
744	seg_mmc_size = 0
745
746	nb_mwr = 0
747	mwr_channels = 0
748	seg_mwr_base = 0xFFFFFFFF
749	seg_mwr_size = 0
750	mwr_arg0 = 0
751	mwr_arg1 = 0
752	mwr_arg2 = 0
753	mwr_arg3 = 0
754	use_mwr_gcd = False
755	use_mwr_dct = False
756	use_mwr_cpy = False
757
758	nb_nic = 0
759	nic_channels = 0
760	seg_nic_base = 0xFFFFFFFF
761	seg_nic_size = 0
762
763	nb_pic = 0
764	pic_channels = 0
765	seg_pic_base = 0xFFFFFFFF
766	seg_pic_size = 0
767
768	nb_rom = 0
769	rom_channels = 0
770	seg_rom_base = 0xFFFFFFFF
771	seg_rom_size = 0
772
773	nb_sim = 0
774	sim_channels = 0
775	seg_sim_base = 0xFFFFFFFF
776	seg_sim_size = 0
777
778	nb_tim = 0
779	tim_channels = 0
780	seg_tim_base = 0xFFFFFFFF
781	seg_tim_size = 0
782
783	nb_tty = 0
784	tty_channels = 0
785	seg_tty_base = 0xFFFFFFFF
786	seg_tty_size = 0
787
788	nb_xcu = 0
789	xcu_channels = 0
790	seg_xcu_base = 0xFFFFFFFF
791	seg_xcu_size = 0
792	xcu_arg0 = 0
793
794	nb_drom = 0
795	drom_channels = 0
796	seg_drom_base = 0xFFFFFFFF
797	seg_drom_size = 0
798
799	# get peripherals attributes
800	for cluster in self.clusters:
801	for periph in cluster.periphs:
802	if ( periph.ptype == 'CMA' ):
803	seg_cma_base = periph.pseg.base & 0xFFFFFFFF
804	seg_cma_size = periph.pseg.size
805	cma_channels = periph.channels
806	nb_cma +=1
807
808	elif ( periph.ptype == 'DMA' ):
809	seg_dma_base = periph.pseg.base & 0xFFFFFFFF
810	seg_dma_size = periph.pseg.size
811	dma_channels = periph.channels
812	nb_dma +=1
813
814	elif ( periph.ptype == 'FBF' ):
815	seg_fbf_base = periph.pseg.base & 0xFFFFFFFF
816	seg_fbf_size = periph.pseg.size
817	fbf_channels = periph.channels
818	fbf_arg0 = periph.arg0
819	fbf_arg1 = periph.arg1
820	nb_fbf +=1
821
822	elif ( periph.ptype == 'IOB' ):
823	seg_iob_base = periph.pseg.base & 0xFFFFFFFF
824	seg_iob_size = periph.pseg.size
825	iob_channels = periph.channels
826	nb_iob +=1
827
828	elif ( periph.ptype == 'IOC' ):
829	seg_ioc_base = periph.pseg.base & 0xFFFFFFFF
830	seg_ioc_size = periph.pseg.size
831	ioc_channels = periph.channels
832	nb_ioc += 1
833	if ( periph.subtype == 'BDV' ): use_ioc_bdv = True
834	if ( periph.subtype == 'HBA' ): use_ioc_hba = True
835	if ( periph.subtype == 'SDC' ): use_ioc_sdc = True
836	if ( periph.subtype == 'SPI' ): use_ioc_spi = True
837
838	elif ( periph.ptype == 'MMC' ):
839	seg_mmc_base = periph.pseg.base & 0xFFFFFFFF
840	seg_mmc_size = periph.pseg.size
841	mmc_channels = periph.channels
842	nb_mmc +=1
843
844	elif ( periph.ptype == 'MWR' ):
845	seg_mwr_base = periph.pseg.base & 0xFFFFFFFF
846	seg_mwr_size = periph.pseg.size
847	mwr_channels = periph.channels
848	mwr_arg0 = periph.arg0
849	mwr_arg1 = periph.arg1
850	mwr_arg2 = periph.arg2
851	mwr_arg3 = periph.arg3
852	nb_mwr +=1
853	if ( periph.subtype == 'GCD' ): use_mwr_gcd = True
854	if ( periph.subtype == 'DCT' ): use_mwr_dct = True
855	if ( periph.subtype == 'CPY' ): use_mwr_cpy = True
856
857	elif ( periph.ptype == 'ROM' ):
858	seg_rom_base = periph.pseg.base & 0xFFFFFFFF
859	seg_rom_size = periph.pseg.size
860	rom_channels = periph.channels
861	nb_rom +=1
862
863	elif ( periph.ptype == 'DROM' ):
864	seg_drom_base = periph.pseg.base & 0xFFFFFFFF
865	seg_drom_size = periph.pseg.size
866	drom_channels = periph.channels
867	nb_drom +=1
868
869	elif ( periph.ptype == 'SIM' ):
870	seg_sim_base = periph.pseg.base & 0xFFFFFFFF
871	seg_sim_size = periph.pseg.size
872	sim_channels = periph.channels
873	nb_sim +=1
874
875	elif ( periph.ptype == 'NIC' ):
876	seg_nic_base = periph.pseg.base & 0xFFFFFFFF
877	seg_nic_size = periph.pseg.size
878	nic_channels = periph.channels
879	nb_nic +=1
880
881	elif ( periph.ptype == 'PIC' ):
882	seg_pic_base = periph.pseg.base & 0xFFFFFFFF
883	seg_pic_size = periph.pseg.size
884	pic_channels = periph.channels
885	nb_pic +=1
886
887	elif ( periph.ptype == 'TIM' ):
888	seg_tim_base = periph.pseg.base & 0xFFFFFFFF
889	seg_tim_size = periph.pseg.size
890	tim_channels = periph.channels
891	nb_tim +=1
892
893	elif ( periph.ptype == 'TTY' ):
894	seg_tty_base = periph.pseg.base & 0xFFFFFFFF
895	seg_tty_size = periph.pseg.size
896	tty_channels = periph.channels
897	nb_tty +=1
898
899	elif ( periph.ptype == 'XCU' ):
900	seg_xcu_base = periph.pseg.base & 0xFFFFFFFF
901	seg_xcu_size = periph.pseg.size
902	xcu_channels = periph.channels
903	xcu_arg0 = periph.arg0
904	xcu_arg1 = periph.arg1
905	xcu_arg2 = periph.arg2
906	nb_xcu +=1
907
908	# no more than two access to external peripherals
909	assert ( nb_fbf <= 2 )
910	assert ( nb_cma <= 2 )
911	assert ( nb_ioc <= 2 )
912	assert ( nb_nic <= 2 )
913	assert ( nb_tim <= 2 )
914	assert ( nb_tty <= 2 )
915	assert ( nb_pic <= 2 )
916
917	# one and only one type of IOC controller
918	nb_ioc_types = 0
919	if use_ioc_hba: nb_ioc_types += 1
920	if use_ioc_bdv: nb_ioc_types += 1
921	if use_ioc_sdc: nb_ioc_types += 1
922	if use_ioc_spi: nb_ioc_types += 1
923	if self.use_ramdisk: nb_ioc_types += 1
924	assert ( nb_ioc_types == 1 )
925
926	# one and only one type of MWR controller
927	nb_mwr_types = 0
928	if use_mwr_gcd: nb_mwr_types += 1
929	if use_mwr_dct: nb_mwr_types += 1
930	if use_mwr_cpy: nb_mwr_types += 1
931	if ( nb_mwr > 0 ) : assert ( nb_mwr_types == 1 )
932
933	# Compute total number of processors
934	for cluster in self.clusters:
935	nb_total_procs += len( cluster.procs )
936
937	# Compute physical addresses for BOOT vsegs
938	boot_mapping_found = False
939	boot_code_found = False
940	boot_data_found = False
941	boot_stack_found = False
942
943	for vseg in self.globs:
944	if ( vseg.name == 'seg_boot_mapping' ):
945	boot_mapping_base = vseg.vbase
946	boot_mapping_size = vseg.length
947	boot_mapping_identity = vseg.identity
948	boot_mapping_found = True
949
950	if ( vseg.name == 'seg_boot_code' ):
951	boot_code_base = vseg.vbase
952	boot_code_size = vseg.length
953	boot_code_identity = vseg.identity
954	boot_code_found = True
955
956	if ( vseg.name == 'seg_boot_data' ):
957	boot_data_base = vseg.vbase
958	boot_data_size = vseg.length
959	boot_data_identity = vseg.identity
960	boot_data_found = True
961
962	if ( vseg.name == 'seg_boot_stack' ):
963	boot_stack_base = vseg.vbase
964	boot_stack_size = vseg.length
965	boot_stack_identity = vseg.identity
966	boot_stack_found = True
967
968	# check that BOOT vsegs are found and identity mapping
969	if ( (boot_mapping_found == False) or (boot_mapping_identity == False) ):
970	print '[genmap error] in hard_config()'
971	print ' seg_boot_mapping missing or not identity mapping'
972	sys.exit()
973
974	if ( (boot_code_found == False) or (boot_code_identity == False) ):
975	print '[genmap error] in hard_config()'
976	print ' seg_boot_code missing or not identity mapping'
977	sys.exit()
978
979	if ( (boot_data_found == False) or (boot_data_identity == False) ):
980	print '[genmap error] in hard_config()'
981	print ' seg_boot_data missing or not identity mapping'
982	sys.exit()
983
984	if ( (boot_stack_found == False) or (boot_stack_identity == False) ):
985	print '[genmap error] in giet_vsegs()'
986	print ' seg_boot_stask missing or not identity mapping'
987	sys.exit()
988
989	# Search RAMDISK global vseg if required
990	seg_rdk_base = 0xFFFFFFFF
991	seg_rdk_size = 0
992	seg_rdk_found = False
993
994	if self.use_ramdisk:
995	for vseg in self.globs:
996	if ( vseg.name == 'seg_ramdisk' ):
997	seg_rdk_base = vseg.vbase
998	seg_rdk_size = vseg.length
999	seg_rdk_found = True
1000
1001	if ( seg_rdk_found == False ):
1002	print 'Error in hard_config() "seg_ramdisk" not found'
1003	sys.exit(1)
1004
1005	# build string
1006	s = '/* Generated by genmap for %s */\n' % self.name
1007	s += '\n'
1008	s += '#ifndef HARD_CONFIG_H\n'
1009	s += '#define HARD_CONFIG_H\n'
1010	s += '\n'
1011
1012	s += '/* General platform parameters */\n'
1013	s += '\n'
1014	s += '#define X_SIZE %d\n' % self.x_size
1015	s += '#define Y_SIZE %d\n' % self.y_size
1016	s += '#define X_WIDTH %d\n' % self.x_width
1017	s += '#define Y_WIDTH %d\n' % self.y_width
1018	s += '#define P_WIDTH %d\n' % self.p_width
1019	s += '#define X_IO %d\n' % self.x_io
1020	s += '#define Y_IO %d\n' % self.y_io
1021	s += '#define NB_PROCS_MAX %d\n' % self.nprocs
1022	s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc
1023	s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address
1024	s += '#define NB_TOTAL_PROCS %d\n' % nb_total_procs
1025	s += '\n'
1026
1027	s += '/* Peripherals */\n'
1028	s += '\n'
1029	s += '#define NB_TTY_CHANNELS %d\n' % tty_channels
1030	s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels
1031	s += '#define NB_NIC_CHANNELS %d\n' % nic_channels
1032	s += '#define NB_CMA_CHANNELS %d\n' % cma_channels
1033	s += '#define NB_TIM_CHANNELS %d\n' % tim_channels
1034	s += '#define NB_DMA_CHANNELS %d\n' % dma_channels
1035	s += '\n'
1036	s += '#define USE_XCU %d\n' % ( nb_xcu != 0 )
1037	s += '#define USE_DMA %d\n' % ( nb_dma != 0 )
1038	s += '\n'
1039	s += '#define USE_IOB %d\n' % ( nb_iob != 0 )
1040	s += '#define USE_PIC %d\n' % ( nb_pic != 0 )
1041	s += '#define USE_FBF %d\n' % ( nb_fbf != 0 )
1042	s += '#define USE_NIC %d\n' % ( nb_nic != 0 )
1043	s += '\n'
1044	s += '#define USE_IOC_BDV %d\n' % use_ioc_bdv
1045	s += '#define USE_IOC_SDC %d\n' % use_ioc_sdc
1046	s += '#define USE_IOC_HBA %d\n' % use_ioc_hba
1047	s += '#define USE_IOC_SPI %d\n' % use_ioc_spi
1048	s += '#define USE_IOC_RDK %d\n' % self.use_ramdisk
1049	s += '\n'
1050	s += '#define USE_MWR_GCD %d\n' % use_mwr_gcd
1051	s += '#define USE_MWR_DCT %d\n' % use_mwr_dct
1052	s += '#define USE_MWR_CPY %d\n' % use_mwr_cpy
1053	s += '\n'
1054	s += '#define FBUF_X_SIZE %d\n' % fbf_arg0
1055	s += '#define FBUF_Y_SIZE %d\n' % fbf_arg1
1056	s += '\n'
1057	s += '#define XCU_NB_HWI %d\n' % xcu_arg0
1058	s += '#define XCU_NB_PTI %d\n' % xcu_arg1
1059	s += '#define XCU_NB_WTI %d\n' % xcu_arg2
1060	s += '#define XCU_NB_OUT %d\n' % xcu_channels
1061	s += '\n'
1062	s += '#define MWR_TO_COPROC %d\n' % mwr_arg0
1063	s += '#define MWR_FROM_COPROC %d\n' % mwr_arg1
1064	s += '#define MWR_CONFIG %d\n' % mwr_arg2
1065	s += '#define MWR_STATUS %d\n' % mwr_arg3
1066	s += '\n'
1067
1068	s += '/* base addresses and sizes for physical segments */\n'
1069	s += '\n'
1070	s += '#define SEG_RAM_BASE 0x%x\n' % self.ram_base
1071	s += '#define SEG_RAM_SIZE 0x%x\n' % self.ram_size
1072	s += '\n'
1073	s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base
1074	s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size
1075	s += '\n'
1076	s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base
1077	s += '#define SEG_DMA_SIZE 0x%x\n' % seg_dma_size
1078	s += '\n'
1079	s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base
1080	s += '#define SEG_FBF_SIZE 0x%x\n' % seg_fbf_size
1081	s += '\n'
1082	s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base
1083	s += '#define SEG_IOB_SIZE 0x%x\n' % seg_iob_size
1084	s += '\n'
1085	s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base
1086	s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size
1087	s += '\n'
1088	s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base
1089	s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size
1090	s += '\n'
1091	s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base
1092	s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size
1093	s += '\n'
1094	s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base
1095	s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size
1096	s += '\n'
1097	s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base
1098	s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size
1099	s += '\n'
1100	s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base
1101	s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size
1102	s += '\n'
1103	s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base
1104	s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size
1105	s += '\n'
1106	s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base
1107	s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size
1108	s += '\n'
1109	s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base
1110	s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size
1111	s += '\n'
1112	s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base
1113	s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size
1114	s += '\n'
1115	s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base
1116	s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size
1117	s += '\n'
1118	s += '#define SEG_DROM_BASE 0x%x\n' % seg_drom_base
1119	s += '#define SEG_DROM_SIZE 0x%x\n' % seg_drom_size
1120	s += '\n'
1121	s += '#define PERI_CLUSTER_INCREMENT 0x%x\n' % self.peri_increment
1122	s += '\n'
1123
1124	s += '/* physical base addresses for identity mapped vsegs */\n'
1125	s += '/* used by the GietVM OS */\n'
1126	s += '\n'
1127	s += '#define SEG_BOOT_MAPPING_BASE 0x%x\n' % boot_mapping_base
1128	s += '#define SEG_BOOT_MAPPING_SIZE 0x%x\n' % boot_mapping_size
1129	s += '\n'
1130	s += '#define SEG_BOOT_CODE_BASE 0x%x\n' % boot_code_base
1131	s += '#define SEG_BOOT_CODE_SIZE 0x%x\n' % boot_code_size
1132	s += '\n'
1133	s += '#define SEG_BOOT_DATA_BASE 0x%x\n' % boot_data_base
1134	s += '#define SEG_BOOT_DATA_SIZE 0x%x\n' % boot_data_size
1135	s += '\n'
1136	s += '#define SEG_BOOT_STACK_BASE 0x%x\n' % boot_stack_base
1137	s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size
1138	s += '#endif\n'
1139
1140	return s
1141
1142	# end of hard_config()
1143
1144	#################################################################
1145	def linux_dts( self ): # compute string for linux.dts file
1146	# used for linux configuration
1147	# header
1148	s = '/dts-v1/;\n'
1149	s += '\n'
1150	s += '/{\n'
1151	s += ' compatible = "tsar,%s";\n' % self.name
1152	s += ' #address-cells = <2>;\n' # physical address on 64 bits
1153	s += ' #size-cells = <1>;\n' # segment size on 32 bits
1154	s += ' model = "%s";\n' % self.name
1155	s += '\n'
1156
1157	# linux globals arguments
1158	s += ' chosen {\n'
1159	s += ' linux,stdout-path = &tty;\n'
1160	s += ' bootargs = "console=tty0 console=ttyVTTY0 earlyprintk";\n'
1161	s += ' };\n\n'
1162
1163	# cpus (for each cluster)
1164	s += ' cpus {\n'
1165	s += ' #address-cells = <1>;\n'
1166	s += ' #size-cells = <0>;\n'
1167
1168	for cluster in self.clusters:
1169	for proc in cluster.procs:
1170	x = cluster.x
1171	y = cluster.y
1172	l = proc.lpid
1173	proc_id = (((x << self.y_width) + y) << self.p_width) + l
1174	s += ' cpu@%d_%d_%d {\n' %(x,y,l)
1175	s += ' device_type = "cpu";\n'
1176	s += ' compatible = "soclib,mips32el";\n'
1177	s += ' reg = <0x%x>;\n' % proc_id
1178	s += ' };\n'
1179	s += '\n'
1180
1181	s += ' };\n\n'
1182
1183	# devices (ram or peripheral) are grouped per cluster
1184	# the "compatible" attribute links a peripheral device
1185	# to one or several drivers identified by ("major","minor")
1186
1187	chosen_tty = False
1188	for cluster in self.clusters:
1189	x = cluster.x
1190	y = cluster.y
1191	found_xcu = False
1192	found_pic = False
1193
1194	s += ' /* cluster[%d,%d] */\n\n' % (x,y)
1195
1196	# scan all psegs to find RAM in current cluster
1197	for pseg in cluster.psegs:
1198	if ( pseg.segtype == 'RAM' ):
1199	msb = pseg.base >> 32
1200	lsb = pseg.base & 0xFFFFFFFF
1201	size = pseg.size
1202
1203	s += ' %s@0x%x {\n' % (pseg.name, pseg.base)
1204	s += ' device_type = "memory";\n'
1205	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1206	s += ' };\n\n'
1207
1208	# scan all periphs to find XCU or PIC in current cluster
1209	for periph in cluster.periphs:
1210	msb = periph.pseg.base >> 32
1211	lsb = periph.pseg.base & 0xFFFFFFFF
1212	size = periph.pseg.size
1213
1214	# search XCU (can be replicated)
1215	if ( (periph.ptype == 'XCU') ):
1216	found_xcu = True
1217
1218	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1219	s += ' compatible = "soclib,vci_xicu","soclib,vci_xicu_timer";\n'
1220	s += ' interrupt-controller;\n'
1221	s += ' #interrupt-cells = <1>;\n'
1222	s += ' clocks = <&freq>;\n' # XCU contains a timer
1223	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1224	s += ' };\n\n'
1225
1226	# search PIC (non replicated)
1227	if ( periph.ptype == 'PIC' ):
1228	found_pic = True
1229
1230	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1231	s += ' compatible = "soclib,vci_iopic";\n'
1232	s += ' interrupt-controller;\n'
1233	s += ' #interrupt-cells = <1>;\n'
1234	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1235	s += ' };\n\n'
1236
1237	# we need one interrupt controler in any cluster containing peripherals
1238	if ( (found_xcu == False) and
1239	(found_pic == False) and
1240	(len(cluster.periphs) > 0) ):
1241	print '[genmap error] in linux_dts()'
1242	print ' No XCU/PIC in cluster(%d,%d)' % (x,y)
1243	sys.exit(1)
1244
1245	# scan all periphs to find TTY and IOC in current cluster
1246	for periph in cluster.periphs:
1247	msb = periph.pseg.base >> 32
1248	lsb = periph.pseg.base & 0xFFFFFFFF
1249	size = periph.pseg.size
1250
1251	irq_ctrl = periph.irq_ctrl
1252	if irq_ctrl != None:
1253	irq_ctrl_name = '%s@0x%x' % (irq_ctrl.pseg.name, irq_ctrl.pseg.base)
1254
1255	# search TTY (non replicated)
1256	if periph.ptype == 'TTY':
1257	assert irq_ctrl != None
1258
1259	# get HWI index to XCU or PIC (only TTY0 is used by Linux)
1260	hwi_id = 0xFFFFFFFF
1261	for irq in irq_ctrl.irqs:
1262	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == 0) ):
1263	hwi_id = irq.srcid
1264
1265	if ( hwi_id == 0xFFFFFFFF ):
1266	print '[genmap error] in linux.dts()'
1267	print ' IRQ_TTY_RX not found'
1268	sys.exit(1)
1269
1270	if chosen_tty == False:
1271	chosen_tty = True
1272	s += ' tty:\n'
1273
1274	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1275	s += ' compatible = "soclib,vci_multi_tty";\n'
1276	s += ' interrupt-parent = <&{/%s}>;\n' % (irq_ctrl_name)
1277	s += ' interrupts = <%d>;\n' % hwi_id
1278	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1279	s += ' };\n\n'
1280
1281
1282	# search IOC (non replicated)
1283	elif ( periph.ptype == 'IOC' ):
1284	assert irq_ctrl != None
1285
1286	if ( periph.subtype == 'BDV' ):
1287
1288	# get irq line index associated to bdv
1289	hwi_id = 0xFFFFFFFF
1290	for irq in irq_ctrl.irqs:
1291	if ( irq.isrtype == 'ISR_BDV' ): hwi_id = irq.srcid
1292
1293	if ( hwi_id == 0xFFFFFFFF ):
1294	print '[genmap error] in linux.dts()'
1295	print ' ISR_BDV not found'
1296	sys.exit(1)
1297
1298	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1299	s += ' compatible = "tsar,vci_block_device";\n'
1300	s += ' interrupt-parent = <&{/%s}>;\n' % (irq_ctrl_name)
1301	s += ' interrupts = <%d>;\n' % hwi_id
1302	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1303	s += ' };\n\n'
1304
1305	else:
1306	print '[genmap warning] in linux_dts() : '
1307	print ' %s' % (periph.subtype),
1308	print 'peripheral not supported by LINUX'
1309
1310	# XCU or PIC have been already parsed
1311	elif ( periph.ptype == 'XCU' ) or ( periph.ptype == 'PIC' ):
1312	pass
1313
1314	# other peripherals
1315	else:
1316	print '[genmap warning] in linux_dts() : '
1317	print ' %s peripheral not supported by LINUX' % (periph.ptype)
1318
1319	# clocks
1320	s += ' clocks {\n'
1321	s += ' freq: freq@50MHZ {\n'
1322	s += ' #clock-cells = <0>;\n'
1323	s += ' compatible = "fixed-clock";\n'
1324	s += ' clock-frequency = <50000000>;\n'
1325	s += ' };\n'
1326	s += ' };\n\n'
1327	s += ' cpuclk {\n'
1328	s += ' compatible = "soclib,mips32_clksrc";\n'
1329	s += ' clocks = <&freq>;\n'
1330	s += ' };\n'
1331	s += '};\n'
1332
1333	return s
1334	# end linux_dts()
1335
1336
1337	#################################################################
1338	def netbsd_dts( self ): # compute string for netbsd.dts file
1339	# used for netbsd configuration
1340	# header
1341	s = '/dts-v1/;\n'
1342	s += '\n'
1343	s += '/{\n'
1344	s += ' #address-cells = <2>;\n'
1345	s += ' #size-cells = <1>;\n'
1346
1347	# cpus (for each cluster)
1348	s += ' cpus {\n'
1349	s += ' #address-cells = <1>;\n'
1350	s += ' #size-cells = <0>;\n'
1351
1352	for cluster in self.clusters:
1353	for proc in cluster.procs:
1354	proc_id = (((cluster.x << self.y_width) + cluster.y)
1355	<< self.p_width) + proc.lpid
1356
1357	s += ' Mips,32@0x%x {\n' % proc_id
1358	s += ' device_type = "cpu";\n'
1359	s += ' icudev_type = "cpu:mips";\n'
1360	s += ' name = "Mips,32";\n'
1361	s += ' reg = <0x%x>;\n' % proc_id
1362	s += ' };\n'
1363	s += '\n'
1364
1365	s += ' };\n'
1366
1367	# physical memory banks (for each cluster)
1368	for cluster in self.clusters:
1369	for pseg in cluster.psegs:
1370
1371	if ( pseg.segtype == 'RAM' ):
1372	msb = pseg.base >> 32
1373	lsb = pseg.base & 0xFFFFFFFF
1374	size = pseg.size
1375
1376	s += ' %s@0x%x {\n' % (pseg.name, pseg.base)
1377	s += ' cached = <1>;\n'
1378	s += ' device_type = "memory";\n'
1379	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb,lsb,size)
1380	s += ' };\n'
1381
1382	# peripherals (for each cluster)
1383	for cluster in self.clusters:
1384	x = cluster.x
1385	y = cluster.y
1386
1387	# research XCU or PIC component
1388	found_xcu = False
1389	found_pic = False
1390	for periph in cluster.periphs:
1391	if ( (periph.ptype == 'XCU') ):
1392	found_xcu = True
1393	xcu = periph
1394	msb = periph.pseg.base >> 32
1395	lsb = periph.pseg.base & 0xFFFFFFFF
1396	size = periph.pseg.size
1397
1398	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1399	s += ' device_type = "soclib:xicu:root";\n'
1400	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb,lsb,size)
1401	s += ' input_lines = <%d>;\n' % periph.arg0
1402	s += ' ipis = <%d>;\n' % periph.arg1
1403	s += ' timers = <%d>;\n' % periph.arg2
1404
1405	output_id = 0 # output index from XCU
1406	for lpid in xrange ( len(cluster.procs) ): # destination processor index
1407	for itid in xrange ( self.irq_per_proc ): # input irq index on processor
1408	cluster_xy = (cluster.x << self.y_width) + cluster.y
1409	proc_id = (cluster_xy << self.p_width) + lpid
1410	s += ' out@%d {\n' % output_id
1411	s += ' device_type = "soclib:xicu:filter";\n'
1412	s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid)
1413	s += ' output_line = <%d>;\n' % output_id
1414	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1415	s += ' };\n'
1416
1417	output_id += 1
1418
1419	s += ' };\n'
1420
1421	if ( periph.ptype == 'PIC' ):
1422	found_pic = True
1423	pic = periph
1424	msb = periph.pseg.base >> 32
1425	lsb = periph.pseg.base & 0xFFFFFFFF
1426	size = periph.pseg.size
1427
1428	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1429	s += ' device_type = "soclib:pic:root";\n'
1430	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1431	s += ' input_lines = <%d>;\n' % periph.channels
1432	s += ' };\n'
1433
1434	# at least one interrupt controller
1435	if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ):
1436	print '[genmap error] in netbsd_dts()'
1437	print ' No XCU/PIC in cluster(%d,%d)' % (x,y)
1438	sys.exit(1)
1439
1440	# get all others peripherals in cluster
1441	for periph in cluster.periphs:
1442	msb = periph.pseg.base >> 32
1443	lsb = periph.pseg.base & 0xFFFFFFFF
1444	size = periph.pseg.size
1445
1446	irq_ctrl = periph.irq_ctrl
1447	if irq_ctrl != None:
1448	irq_ctrl_name = '%s@0x%x' % (irq_ctrl.pseg.name, irq_ctrl.pseg.base)
1449
1450	# XCU or PIC have been already parsed
1451	if ( periph.ptype == 'XCU' ) or ( periph.ptype == 'PIC' ):
1452	pass
1453
1454	# research DMA component
1455	elif ( periph.ptype == 'DMA' ):
1456
1457	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1458	s += ' device_type = "soclib:dma";\n'
1459	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1460	s += ' channel_count = <%d>;\n' % periph.channels
1461
1462	# multi-channels : get HWI index (to XCU) for each channel
1463	for channel in xrange( periph.channels ):
1464	hwi_id = 0xFFFFFFFF
1465	for irq in xcu.irqs:
1466	if ( (irq.isrtype == 'ISR_DMA') and
1467	(irq.channel == channel) ):
1468	hwi_id = irq.srcid
1469
1470	if ( hwi_id == 0xFFFFFFFF ):
1471	print '[genmap error] in netbsd.dts()'
1472	print ' ISR_DMA channel %d not found' % channel
1473	sys.exit(1)
1474
1475	name = '%s@0x%x' % (xcu.pseg.name, xcu.pseg.base)
1476	s += ' irq@%d{\n' % channel
1477	s += ' device_type = "soclib:periph:irq";\n'
1478	s += ' output_line = <%d>;\n' % channel
1479	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1480	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1481	s += ' };\n'
1482
1483	s += ' };\n'
1484
1485	# research MMC component
1486	elif ( periph.ptype == 'MMC' ):
1487
1488	# get irq line index associated to MMC in XCU
1489	irq_in = 0xFFFFFFFF
1490	for irq in xcu.irqs:
1491	if ( irq.isrtype == 'ISR_MMC' ): irq_in = irq.srcid
1492
1493	if ( irq_in == 0xFFFFFFFF ):
1494	print '[genmap error] in netbsd.dts()'
1495	print ' ISR_MMC not found'
1496	sys.exit(1)
1497
1498	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1499	s += ' device_type = "soclib:mmc";\n'
1500	s += ' irq = <&{/%s} %d>;\n' % (irq_ctrl_name, irq_in)
1501	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1502	s += ' };\n'
1503
1504	# research FBF component
1505	elif ( periph.ptype == 'FBF' ):
1506
1507	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1508	s += ' device_type = "soclib:framebuffer";\n'
1509	s += ' mode = <32>;\n' # bits par pixel
1510	s += ' width = <%d>;\n' % periph.arg0
1511	s += ' height = <%d>;\n' % periph.arg1
1512	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1513	s += ' };\n'
1514
1515	# research IOC component
1516	elif ( periph.ptype == 'IOC' ):
1517
1518	if ( periph.subtype == 'BDV' ):
1519
1520	# get irq line index associated to bdv
1521	irq_in = 0xFFFFFFFF
1522	for irq in irq_ctrl.irqs:
1523	if ( irq.isrtype == 'ISR_BDV' ): irq_in = irq.srcid
1524	if ( irq_in == 0xFFFFFFFF ):
1525	print '[genmap error] in netbsd.dts()'
1526	print ' ISR_BDV not found'
1527	sys.exit(1)
1528
1529	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1530	s += ' device_type = "soclib:blockdevice";\n'
1531	s += ' irq = <&{/%s} %d>;\n' % (irq_ctrl_name, irq_in)
1532	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1533	s += ' };\n'
1534
1535	elif ( periph.subtype == 'HBA' ):
1536
1537	print '[genmap error] in netbsd_dts()'
1538	print ' HBA peripheral not supported by NetBSD'
1539
1540	elif ( periph.subtype == 'SDC' ):
1541
1542	# get irq line index associated to sdc
1543	irq_in = 0xFFFFFFFF
1544	for irq in irq_ctrl.irqs:
1545	if ( irq.isrtype == 'ISR_SDC' ): irq_in = irq.srcid
1546	if ( irq_in == 0xFFFFFFFF ):
1547	print '[genmap error] in netbsd.dts()'
1548	print ' ISR_SDC not found'
1549	sys.exit(1)
1550
1551	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1552	s += ' device_type = "soclib:sdc";\n'
1553	s += ' irq = <&{/%s} %d>;\n' % (irq_ctrl_name, irq_in)
1554	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1555	s += ' };\n'
1556
1557	# research ROM component
1558	elif ( periph.ptype == 'ROM' ) or ( periph.ptype == 'DROM' ):
1559
1560	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1561	s += ' device_type = "rom";\n'
1562	s += ' cached = <1>;\n'
1563	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1564	s += ' };\n'
1565
1566	# research SIM component
1567	elif ( periph.ptype == 'SIM' ):
1568
1569	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1570	s += ' device_type = "soclib:simhelper";\n'
1571	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1572	s += ' };\n'
1573
1574	# research TTY component
1575	elif ( periph.ptype == 'TTY' ):
1576
1577	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1578	s += ' device_type = "soclib:tty";\n'
1579	s += ' channel_count = < %d >;\n' % periph.channels
1580	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1581
1582	# multi-channels : get HWI index (to XCU or PIC) for each channel
1583	for channel in xrange( periph.channels ):
1584	hwi_id = 0xFFFFFFFF
1585	for irq in irq_ctrl.irqs:
1586	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ):
1587	hwi_id = irq.srcid
1588	if ( hwi_id == 0xFFFFFFFF ):
1589	print '[genmap error] in netbsd.dts()'
1590	print ' ISR_TTY_RX channel %d not found' % channel
1591	sys.exit(1)
1592
1593	name = '%s' % (irq_ctrl_name)
1594	s += ' irq@%d{\n' % channel
1595	s += ' device_type = "soclib:periph:irq";\n'
1596	s += ' output_line = <%d>;\n' % channel
1597	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1598	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1599	s += ' };\n'
1600
1601	s += ' };\n'
1602
1603	# research IOB component
1604	elif ( periph.ptype == 'IOB' ):
1605
1606	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1607	s += ' device_type = "soclib:iob";\n'
1608	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1609	s += ' };\n'
1610
1611	# research NIC component
1612	elif ( periph.ptype == 'NIC' ):
1613
1614	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1615	s += ' device_type = "soclib:nic";\n'
1616	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1617	s += ' channel_count = < %d >;\n' % periph.channels
1618
1619	# multi-channels : get HWI index (to XCU or PIC) for RX & TX IRQs
1620	# RX IRQ : (2channel) / TX IRQs : (2channel + 1)
1621	for channel in xrange( periph.channels ):
1622	hwi_id = 0xFFFFFFFF
1623	for irq in irq_ctrl.irqs:
1624	if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ):
1625	hwi_id = irq.srcid
1626	if ( hwi_id == 0xFFFFFFFF ):
1627	print '[genmap error] in netbsd.dts()'
1628	print ' ISR_NIC_RX channel %d not found' % channel
1629	sys.exit(1)
1630
1631	name = '%s' % (irq_ctrl_name)
1632	s += ' irq_rx@%d{\n' % channel
1633	s += ' device_type = "soclib:periph:irq";\n'
1634	s += ' output_line = <%d>;\n' % (2*channel)
1635	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1636	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1637	s += ' };\n'
1638
1639	hwi_id = 0xFFFFFFFF
1640	for irq in irq_ctrl.irqs:
1641	if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ):
1642	hwi_id = irq.srcid
1643	if ( hwi_id == 0xFFFFFFFF ):
1644	print '[genmap error] in netbsd.dts()'
1645	print ' ISR_NIC_TX channel %d not found' % channel
1646	sys.exit(1)
1647
1648	name = '%s' % (irq_ctrl_name)
1649	s += ' irq_tx@%d{\n' % channel
1650	s += ' device_type = "soclib:periph:irq";\n'
1651	s += ' output_line = <%d>;\n' % (2*channel + 1)
1652	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1653	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1654	s += ' };\n'
1655
1656	s += ' };\n'
1657
1658	# research CMA component
1659	elif ( periph.ptype == 'CMA' ):
1660
1661	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1662	s += ' device_type = "soclib:cma";\n'
1663	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1664	s += ' channel_count = < %d >;\n' % periph.channels
1665
1666	# multi-channels : get HWI index (to XCU or PIC) for each channel
1667	for channel in xrange( periph.channels ):
1668	hwi_id = 0xFFFFFFFF
1669	for irq in irq_ctrl.irqs:
1670	if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ):
1671	hwi_id = irq.srcid
1672
1673	if ( hwi_id == 0xFFFFFFFF ):
1674	print '[genmap error] in netbsd.dts()'
1675	print ' ISR_CMA channel %d not found' % channel
1676	sys.exit(1)
1677
1678	name = '%s' % (irq_ctrl_name)
1679	s += ' irq@%d{\n' % channel
1680	s += ' device_type = "soclib:periph:irq";\n'
1681	s += ' output_line = <%d>;\n' % channel
1682	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1683	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1684	s += ' };\n'
1685
1686	s += ' };\n'
1687
1688	else:
1689
1690	print '[genmap error] in netbsd_dts()'
1691	print ' %s peripheral not supported by NetBSD' % periph.ptype
1692
1693
1694	# topology
1695	s += '\n'
1696	s += ' topology {\n'
1697	s += ' #address-cells = <2>;\n'
1698	s += ' #size-cells = <0>;\n'
1699	for cluster in self.clusters:
1700	s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y)
1701	s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y)
1702	s += ' devices = <\n'
1703
1704	offset = ((cluster.x << self.y_width) + cluster.y) << self.p_width
1705	for proc in cluster.procs:
1706	s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid)
1707	for periph in cluster.periphs:
1708	s += ' &{/%s@0x%x}\n' % (periph.pseg.name, periph.pseg.base)
1709	for pseg in cluster.psegs:
1710	if ( pseg.segtype == 'RAM' ):
1711	s += ' &{/%s@0x%x}\n' % (pseg.name, pseg.base)
1712
1713	s += ' >;\n'
1714	s += ' };\n'
1715	s += ' };\n'
1716	s += '};\n'
1717
1718	return s
1719	# end netbsd_dts()
1720
1721	######################################################################
1722	def almos_archinfo( self ): # compute string for arch.info file
1723	# used for almos configuration
1724	# header
1725	s = '# arch.info file generated by genmap for %s\n' % self.name
1726	s += '\n'
1727	s += '[HEADER]\n'
1728	s += ' REVISION=1\n'
1729	s += ' ARCH=%s\n' % self.name
1730	s += ' XMAX=%d\n' % self.x_size
1731	s += ' YMAX=%d\n' % self.y_size
1732	s += ' CPU_NR=%d\n' % self.nprocs
1733	s += '\n'
1734
1735	# clusters
1736	cluster_id = 0
1737	for cluster in self.clusters:
1738
1739	ram = None
1740	nb_cpus = len( cluster.procs )
1741	nb_devs = len( cluster.periphs )
1742
1743	# search a RAM
1744	for pseg in cluster.psegs:
1745	if ( pseg.segtype == 'RAM' ):
1746	ram = pseg
1747	nb_devs += 1
1748
1749	# search XCU to get IRQs indexes if cluster contains peripherals
1750	if ( len( cluster.periphs ) != 0 ):
1751	tty_irq_id = None
1752	bdv_irq_id = None
1753	dma_irq_id = None
1754
1755	for periph in cluster.periphs:
1756	if ( periph.ptype == 'XCU' ):
1757	# scan irqs
1758	for irq in periph.irqs:
1759	if (irq.isrtype=='ISR_TTY_RX'): tty_irq_id = irq.srcid
1760	if (irq.isrtype=='ISR_BDV' ): bdv_irq_id = irq.srcid
1761	if (irq.isrtype=='ISR_DMA' ): dma_irq_id = irq.srcid
1762
1763	# Build the cluster description
1764	s += '[CLUSTER]\n'
1765	s += ' CID=%d\n' % cluster_id
1766	s += ' ARCH_CID=0x%x\n' % ((cluster.x<<self.y_width)+cluster.y)
1767	s += ' CPU_NR=%d\n' % nb_cpus
1768	s += ' DEV_NR=%d\n' % nb_devs
1769
1770
1771	# Handling RAM when cluster contain a RAM
1772	if (ram != None ):
1773	base = ram.base
1774	size = ram.size
1775	irqid = -1
1776	s += ' DEVID=RAM'
1777	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % (base,size)
1778
1779	# Handling peripherals
1780	for periph in cluster.periphs:
1781	base = periph.pseg.base
1782	size = periph.pseg.size
1783
1784	if ( periph.ptype == 'XCU' ):
1785
1786	s += ' DEVID=XICU'
1787	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' %(base,size)
1788
1789	elif ( (periph.ptype == 'TTY')
1790	and (tty_irq_id != None) ):
1791
1792	s += ' DEVID=TTY'
1793	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' %(base,size,tty_irq_id)
1794
1795	elif ( (periph.ptype == 'DMA')
1796	and (dma_irq_id != None) ):
1797
1798	s += ' DEVID=DMA'
1799	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' %(base,size,dma_irq_id)
1800
1801	elif ( periph.ptype == 'FBF' ):
1802
1803	s += ' DEVID=FB'
1804	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' %(base,size )
1805
1806	elif ( (periph.ptype == 'IOC') and (periph.subtype == 'BDV')
1807	and (bdv_irq_id != None) ):
1808
1809	s += ' DEVID=BLKDEV'
1810	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' %(base,size,bdv_irq_id)
1811
1812	elif ( periph.ptype == 'PIC' ):
1813
1814	s += ' DEVID=IOPIC'
1815	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' %(base,size)
1816
1817	else:
1818	print '# Warning from almos_archinfo() in cluster[%d,%d]' \
1819	% (cluster.x, cluster.y)
1820	print '# peripheral type %s/%s not supported yet\n' \
1821	% ( periph.ptype, periph.subtype )
1822
1823	cluster_id += 1
1824
1825	return s
1826
1827	# end of almos_archinfo()
1828
1829
1830
1831
1832
1833
1834
1835
1836	###################################################################################
1837	class Cluster ( object ):
1838	###################################################################################
1839	def __init__( self,
1840	x,
1841	y ):
1842
1843	self.index = 0 # global index (set by Mapping constructor)
1844	self.x = x # x coordinate
1845	self.y = y # y coordinate
1846	self.psegs = [] # filled by addRam() or addPeriph()
1847	self.procs = [] # filled by addProc()
1848	self.periphs = [] # filled by addPeriph()
1849
1850	return
1851
1852	################
1853	def xml( self ): # xml for a cluster
1854
1855	s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y)
1856	for pseg in self.psegs: s += pseg.xml()
1857	for proc in self.procs: s += proc.xml()
1858	for peri in self.periphs: s += peri.xml()
1859	s += ' </cluster>\n'
1860
1861	return s
1862
1863	#############################################
1864	def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster
1865
1866	if ( verbose ):
1867	print '*** cbin for cluster [%d,%d]' % (self.x, self.y)
1868
1869	# check index
1870	if (self.index != expected):
1871	print '[genmap error] in Cluster.cbin()'
1872	print ' cluster global index = %d / expected = %d' \
1873	% (self.index,expected)
1874	sys.exit(1)
1875
1876	# compute global index for first pseg
1877	if ( len(self.psegs) > 0 ):
1878	pseg_id = self.psegs[0].index
1879	else:
1880	pseg_id = 0
1881
1882	# compute global index for first proc
1883	if ( len(self.procs) > 0 ):
1884	proc_id = self.procs[0].index
1885	else:
1886	proc_id = 0
1887
1888	# compute global index for first periph
1889	if ( len(self.periphs) > 0 ):
1890	periph_id = self.periphs[0].index
1891	else:
1892	periph_id = 0
1893
1894	byte_stream = bytearray()
1895	byte_stream += mapping.int2bytes(4,self.x) # x coordinate
1896	byte_stream += mapping.int2bytes(4,self.y) # x coordinate
1897	byte_stream += mapping.int2bytes(4,len(self.psegs)) # psegs in cluster
1898	byte_stream += mapping.int2bytes(4,pseg_id ) # global index
1899	byte_stream += mapping.int2bytes(4,len(self.procs)) # procs in cluster
1900	byte_stream += mapping.int2bytes(4,proc_id ) # global index
1901	byte_stream += mapping.int2bytes(4,len(self.periphs)) # periphs in cluster
1902	byte_stream += mapping.int2bytes(4, periph_id ) # global index
1903
1904	if ( verbose ):
1905	print 'nb_psegs = %d' % len( self.psegs )
1906	print 'pseg_id = %d' % pseg_id
1907	print 'nb_procs = %d' % len( self.procs )
1908	print 'proc_id = %d' % proc_id
1909	print 'nb_periphs = %d' % len( self.periphs )
1910	print 'periph_id = %d' % periph_id
1911
1912	return byte_stream
1913
1914	##################################################################################
1915	class Vspace( object ):
1916	##################################################################################
1917	def __init__( self,
1918	name,
1919	startname ):
1920
1921	self.index = 0 # global index ( set by addVspace() )
1922	self.name = name # vspace name
1923	self.startname = startname # name of vseg containing the start_vector
1924	self.vsegs = []
1925	self.tasks = []
1926
1927	return
1928
1929	################
1930	def xml( self ): # xml for one vspace
1931
1932	s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname )
1933	for vseg in self.vsegs: s += vseg.xml()
1934	for task in self.tasks: s += task.xml()
1935	s += ' </vspace>\n'
1936
1937	return s
1938
1939	#############################################
1940	def cbin( self, mapping, verbose, expected ): # C binary for Vspace
1941
1942	if ( verbose ):
1943	print '*** cbin for vspace %s' % (self.name)
1944
1945	# check index
1946	if (self.index != expected):
1947	print '[genmap error] in Vspace.cbin()'
1948	print ' vspace global index = %d / expected = %d' \
1949	%(self.index,expected)
1950	sys.exit(1)
1951
1952	# compute global index for vseg containing start_vector
1953	vseg_start_id = 0xFFFFFFFF
1954	for vseg in self.vsegs:
1955	if ( vseg.name == self.startname ): vseg_start_id = vseg.index
1956
1957	if ( vseg_start_id == 0xFFFFFFFF ):
1958	print '[genmap error] in Vspace.cbin()'
1959	print ' startname %s not found for vspace %s' \
1960	%(self.startname,self.name)
1961	sys.exit(1)
1962
1963	# compute first vseg and first task global index
1964	first_vseg_id = self.vsegs[0].index
1965	first_task_id = self.tasks[0].index
1966
1967	# compute number of tasks and number of vsegs
1968	nb_vsegs = len( self.vsegs )
1969	nb_tasks = len( self.tasks )
1970
1971	byte_stream = bytearray()
1972	byte_stream += mapping.str2bytes(32,self.name) # vspace name
1973	byte_stream += mapping.int2bytes(4, vseg_start_id) # vseg start_vector
1974	byte_stream += mapping.int2bytes(4, nb_vsegs) # number of vsegs
1975	byte_stream += mapping.int2bytes(4, nb_tasks) # number of tasks
1976	byte_stream += mapping.int2bytes(4, first_vseg_id) # global index
1977	byte_stream += mapping.int2bytes(4, first_task_id) # global index
1978
1979	if ( verbose ):
1980	print 'start_id = %d' % vseg_start_id
1981	print 'nb_vsegs = %d' % nb_vsegs
1982	print 'nb_tasks = %d' % nb_tasks
1983	print 'vseg_id = %d' % first_vseg_id
1984	print 'task_id = %d' % first_task_id
1985
1986	return byte_stream
1987
1988	##################################################################################
1989	class Task( object ):
1990	##################################################################################
1991	def __init__( self,
1992	name,
1993	trdid,
1994	x,
1995	y,
1996	p,
1997	stackname,
1998	heapname,
1999	startid ):
2000
2001	self.index = 0 # global index value set by addTask()
2002	self.name = name # tsk name
2003	self.trdid = trdid # task index (unique in vspace)
2004	self.x = x # cluster x coordinate
2005	self.y = y # cluster y coordinate
2006	self.p = p # processor local index
2007	self.stackname = stackname # name of vseg containing the stack
2008	self.heapname = heapname # name of vseg containing the heap
2009	self.startid = startid # index in start_vector
2010	return
2011
2012	######################################
2013	def xml( self ): # xml for one task
2014
2015	s = ' <task name="%s"' % self.name
2016	s += ' trdid="%d"' % self.trdid
2017	s += ' x="%d"' % self.x
2018	s += ' y="%d"' % self.y
2019	s += ' p="%d"' % self.p
2020	s += '\n '
2021	s += ' stackname="%s"' % self.stackname
2022	s += ' heapname="%s"' % self.heapname
2023	s += ' startid="%d"' % self.startid
2024	s += ' />\n'
2025
2026	return s
2027
2028	##########################################################################
2029	def cbin( self, mapping, verbose, expected, vspace ): # C binary for Task
2030
2031	if ( verbose ):
2032	print '*** cbin for task %s in vspace %s' \
2033	% (self.name, vspace.name)
2034
2035	# check index
2036	if (self.index != expected):
2037	print '[genmap error] in Task.cbin()'
2038	print ' task global index = %d / expected = %d' \
2039	%(self.index,expected)
2040	sys.exit(1)
2041
2042	# compute cluster global index
2043	cluster_id = (self.x * mapping.y_size) + self.y
2044
2045	# compute vseg index for stack
2046	vseg_stack_id = 0xFFFFFFFF
2047	for vseg in vspace.vsegs:
2048	if ( vseg.name == self.stackname ): vseg_stack_id = vseg.index
2049
2050	if ( vseg_stack_id == 0xFFFFFFFF ):
2051	print '[genmap error] in Task.cbin()'
2052	print ' stackname %s not found for task %s in vspace %s' \
2053	% ( self.stackname, self.name, vspace.name )
2054	sys.exit(1)
2055
2056	# compute vseg index for heap
2057	if ( self.heapname == '' ):
2058	vseg_heap_id = 0
2059	else:
2060	vseg_heap_id = 0xFFFFFFFF
2061	for vseg in vspace.vsegs:
2062	if ( vseg.name == self.heapname ): vseg_heap_id = vseg.index
2063
2064	if ( vseg_heap_id == 0xFFFFFFFF ):
2065	print '[genmap error] in Task.cbin()'
2066	print ' heapname %s not found for task %s in vspace %s' \
2067	% ( self.heapname, self.name, vspace.name )
2068	sys.exit(1)
2069
2070	byte_stream = bytearray()
2071	byte_stream += mapping.str2bytes(32,self.name) # task name in vspace
2072	byte_stream += mapping.int2bytes(4, cluster_id) # cluster global index
2073	byte_stream += mapping.int2bytes(4, self.p) # processor local index
2074	byte_stream += mapping.int2bytes(4, self.trdid) # thread index in vspace
2075	byte_stream += mapping.int2bytes(4, vseg_stack_id) # stack vseg local index
2076	byte_stream += mapping.int2bytes(4, vseg_heap_id) # heap vseg local index
2077	byte_stream += mapping.int2bytes(4, self.startid) # index in start vector
2078	byte_stream += mapping.int2bytes(4 ,0) # ltid (dynamically computed)
2079
2080	if ( verbose ):
2081	print 'clusterid = %d' % cluster_id
2082	print 'lpid = %d' % self.p
2083	print 'trdid = %d' % self.trdid
2084	print 'stackid = %d' % vseg_stack_id
2085	print 'heapid = %d' % vseg_heap_id
2086	print 'startid = %d' % self.startid
2087
2088	return byte_stream
2089
2090	##################################################################################
2091	class Vseg( object ):
2092	##################################################################################
2093	def __init__( self,
2094	name,
2095	vbase,
2096	length,
2097	mode,
2098	vtype,
2099	x,
2100	y,
2101	pseg,
2102	identity = False,
2103	local = False,
2104	big = False,
2105	binpath = '' ):
2106
2107	assert (vbase & 0xFFFFFFFF) == vbase
2108
2109	assert (length & 0xFFFFFFFF) == length
2110
2111	assert mode in VSEGMODES
2112
2113	assert vtype in VSEGTYPES
2114
2115	assert (vtype != 'ELF') or (binpath != '')
2116
2117	self.index = 0 # global index ( set by addVseg() )
2118	self.name = name # vseg name (unique in vspace)
2119	self.vbase = vbase # virtual base address in vspace
2120	self.length = length # vseg length (bytes)
2121	self.vtype = vtype # vseg type (defined in VSEGTYPES)
2122	self.mode = mode # CXWU access rights
2123	self.x = x # x coordinate of destination cluster
2124	self.y = y # y coordinate of destination cluster
2125	self.psegname = pseg # name of pseg in destination cluster
2126	self.identity = identity # identity mapping required
2127	self.local = local # only mapped in local PTAB when true
2128	self.big = big # to be mapped in a big physical page
2129	self.binpath = binpath # pathname for binary file (ELF or BLOB)
2130
2131	return
2132
2133	##################################
2134	def xml( self ): # xml for a vseg
2135
2136	s = ' <vseg name="%s"' %(self.name)
2137	s += ' vbase="0x%x"' %(self.vbase)
2138	s += ' length="0x%x"' %(self.length)
2139	s += ' type="%s"' %(self.vtype)
2140	s += ' mode="%s"' %(self.mode)
2141	s += '\n '
2142	s += ' x="%d"' %(self.x)
2143	s += ' y="%d"' %(self.y)
2144	s += ' psegname="%s"' %(self.psegname)
2145	if ( self.identity ): s += ' ident="1"'
2146	if ( self.local ): s += ' local="1"'
2147	if ( self.big ): s += ' big="1"'
2148	if ( self.binpath != '' ): s += ' binpath="%s"' %(self.binpath)
2149	s += ' />\n'
2150
2151	return s
2152
2153	#####################################################################
2154	def cbin( self, mapping, verbose, expected ): # C binary for Vseg
2155
2156	if ( verbose ):
2157	print '*** cbin for vseg[%d] %s' % (self.index, self.name)
2158
2159	# check index
2160	if (self.index != expected):
2161	print '[genmap error] in Vseg.cbin()'
2162	print ' vseg global index = %d / expected = %d' \
2163	% (self.index, expected )
2164	sys.exit(1)
2165
2166	# compute pseg_id
2167	pseg_id = 0xFFFFFFFF
2168	cluster_id = (self.x * mapping.y_size) + self.y
2169	cluster = mapping.clusters[cluster_id]
2170	for pseg in cluster.psegs:
2171	if (self.psegname == pseg.name):
2172	pseg_id = pseg.index
2173	if (pseg_id == 0xFFFFFFFF):
2174	print '[genmap error] in Vseg.cbin() : '
2175	print ' psegname %s not found for vseg %s in cluster %d' \
2176	% ( self.psegname, self.name, cluster_id )
2177	sys.exit(1)
2178
2179	# compute numerical value for mode
2180	mode_id = 0xFFFFFFFF
2181	for x in xrange( len(VSEGMODES) ):
2182	if ( self.mode == VSEGMODES[x] ):
2183	mode_id = x
2184	if ( mode_id == 0xFFFFFFFF ):
2185	print '[genmap error] in Vseg.cbin() : '
2186	print ' undefined vseg mode %s' % self.mode
2187	sys.exit(1)
2188
2189	# compute numerical value for vtype
2190	vtype_id = 0xFFFFFFFF
2191	for x in xrange( len(VSEGTYPES) ):
2192	if ( self.vtype == VSEGTYPES[x] ):
2193	vtype_id = x
2194	if ( vtype_id == 0xFFFFFFFF ):
2195	print '[genmap error] in Vseg.cbin()'
2196	print ' undefined vseg type %s' % self.vtype
2197	sys.exit(1)
2198
2199	byte_stream = bytearray()
2200	byte_stream += mapping.str2bytes(32,self.name ) # vseg name
2201	byte_stream += mapping.str2bytes(64,self.binpath ) # binpath
2202	byte_stream += mapping.int2bytes(4, self.vbase ) # virtual base address
2203	byte_stream += mapping.int2bytes(8, 0 ) # physical base address
2204	byte_stream += mapping.int2bytes(4, self.length ) # vseg size (bytes)
2205	byte_stream += mapping.int2bytes(4, pseg_id ) # pseg global index
2206	byte_stream += mapping.int2bytes(4, mode_id ) # CXWU flags
2207	byte_stream += mapping.int2bytes(4, vtype_id ) # vseg type
2208	byte_stream += mapping.int2bytes(1, 0 ) # mapped when non zero
2209	byte_stream += mapping.int2bytes(1, self.identity ) # identity mapping
2210	byte_stream += mapping.int2bytes(1, self.local ) # only in local PTAB
2211	byte_stream += mapping.int2bytes(1, self.big ) # to be mapped in BPP
2212
2213	if ( verbose ):
2214	print 'binpath = %s' % self.binpath
2215	print 'vbase = %x' % self.vbase
2216	print 'pbase = 0'
2217	print 'length = %x' % self.length
2218	print 'pseg_id = %d' % pseg_id
2219	print 'mode = %d' % mode_id
2220	print 'type = %d' % vtype_id
2221	print 'mapped = 0'
2222	print 'ident = %d' % self.identity
2223	print 'local = %d' % self.local
2224	print 'big = %d' % self.big
2225
2226	return byte_stream
2227
2228	##################################################################################
2229	class Processor ( object ):
2230	##################################################################################
2231	def __init__( self,
2232	x,
2233	y,
2234	lpid ):
2235
2236	self.index = 0 # global index ( set by addProc() )
2237	self.x = x # x cluster coordinate
2238	self.y = y # y cluster coordinate
2239	self.lpid = lpid # processor local index
2240
2241	return
2242
2243	########################################
2244	def xml( self ): # xml for a processor
2245	return ' <proc index="%d" />\n' % (self.lpid)
2246
2247	####################################################################
2248	def cbin( self, mapping, verbose, expected ): # C binary for Proc
2249
2250	if ( verbose ):
2251	print '*** cbin for proc %d in cluster (%d,%d)' \
2252	% (self.lpid, self.x, self.y)
2253
2254	# check index
2255	if (self.index != expected):
2256	print '[genmap error] in Proc.cbin()'
2257	print ' proc global index = %d / expected = %d' \
2258	% (self.index,expected)
2259	sys.exit(1)
2260
2261	byte_stream = bytearray()
2262	byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index
2263
2264	return byte_stream
2265
2266	##################################################################################
2267	class Pseg ( object ):
2268	##################################################################################
2269	def __init__( self,
2270	name,
2271	base,
2272	size,
2273	x,
2274	y,
2275	segtype ):
2276
2277	assert( segtype in PSEGTYPES )
2278
2279	self.index = 0 # global index ( set by addPseg() )
2280	self.name = name # pseg name (unique in cluster)
2281	self.base = base # physical base address
2282	self.size = size # segment size (bytes)
2283	self.x = x # cluster x coordinate
2284	self.y = y # cluster y coordinate
2285	self.segtype = segtype # RAM / PERI (defined in mapping_info.h)
2286
2287	return
2288
2289	###################################
2290	def xml( self ): # xml for a pseg
2291
2292	s = ' <pseg name="%s" type="%s" base="0x%x" length="0x%x" />\n' \
2293	% (self.name, self.segtype, self.base, self.size)
2294	return s
2295
2296	###########################################################################
2297	def cbin( self, mapping, verbose, expected, cluster ): # C binary for Pseg
2298
2299	if ( verbose ):
2300	print '*** cbin for pseg[%d] %s in cluster[%d,%d]' \
2301	% (self.index, self.name, cluster.x, cluster.y)
2302
2303	# check index
2304	if (self.index != expected):
2305	print '[genmap error] in Pseg.cbin()'
2306	print ' pseg global index = %d / expected = %d' \
2307	% (self.index,expected)
2308	sys.exit(1)
2309
2310	# compute numerical value for segtype
2311	segtype_int = 0xFFFFFFFF
2312	for x in xrange( len(PSEGTYPES) ):
2313	if ( self.segtype == PSEGTYPES[x] ): segtype_int = x
2314
2315	if ( segtype_int == 0xFFFFFFFF ):
2316	print '[genmap error] in Pseg.cbin()'
2317	print ' undefined segment type %s' % self.segtype
2318	sys.exit(1)
2319
2320	byte_stream = bytearray()
2321	byte_stream += mapping.str2bytes(32,self.name) # pseg name
2322	byte_stream += mapping.int2bytes(8 ,self.base) # physical base address
2323	byte_stream += mapping.int2bytes(8 ,self.size) # segment length
2324	byte_stream += mapping.int2bytes(4 ,segtype_int) # segment type
2325	byte_stream += mapping.int2bytes(4 ,cluster.index) # cluster global index
2326	byte_stream += mapping.int2bytes(4 ,0) # linked list of vsegs
2327
2328	if ( verbose ):
2329	print 'pbase = %x' % self.base
2330	print 'size = %x' % self.size
2331	print 'type = %s' % self.segtype
2332
2333	return byte_stream
2334
2335	##################################################################################
2336	class Periph ( object ):
2337	##################################################################################
2338	def __init__( self,
2339	pseg, # associated pseg
2340	ptype, # peripheral type
2341	subtype = 'NONE', # peripheral subtype
2342	channels = 1, # for multi-channels peripherals
2343	arg0 = 0, # optional (semantic depends on ptype)
2344	arg1 = 0, # optional (semantic depends on ptype)
2345	arg2 = 0, # optional (semantic depends on ptype)
2346	arg3 = 0 ): # optional (semantic depends on ptype)
2347
2348	self.index = 0 # global index ( set by addPeriph() )
2349	self.channels = channels
2350	self.ptype = ptype
2351	self.subtype = subtype
2352	self.arg0 = arg0
2353	self.arg1 = arg1
2354	self.arg2 = arg2
2355	self.arg3 = arg3
2356	self.pseg = pseg
2357	self.irqs = []
2358	self.irq_ctrl = None # interrupt controller peripheral
2359	return
2360
2361	######################################
2362	def xml( self ): # xml for a periph
2363
2364	s = ' <periph type="%s"' % self.ptype
2365	s += ' subtype="%s"' % self.subtype
2366	s += ' psegname="%s"' % self.pseg.name
2367	s += ' channels="%d"' % self.channels
2368	s += ' arg0="%d"' % self.arg0
2369	s += ' arg1="%d"' % self.arg1
2370	s += ' arg2="%d"' % self.arg2
2371	s += ' arg3="%d"' % self.arg3
2372	if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') ):
2373	s += ' >\n'
2374	for irq in self.irqs: s += irq.xml()
2375	s += ' </periph>\n'
2376	else:
2377	s += ' />\n'
2378	return s
2379
2380	######################################################################
2381	def cbin( self, mapping, verbose, expected ): # C binary for Periph
2382
2383	if ( verbose ):
2384	print '*** cbin for periph %s in cluster [%d,%d]' \
2385	% (self.ptype, self.pseg.x, self.pseg.y)
2386
2387	# check index
2388	if (self.index != expected):
2389	print '[genmap error] in Periph.cbin()'
2390	print ' periph global index = %d / expected = %d' \
2391	% (self.index,expected)
2392	sys.exit(1)
2393
2394	# compute pseg global index
2395	pseg_id = self.pseg.index
2396
2397	# compute first irq global index
2398	if ( len(self.irqs) > 0 ):
2399	irq_id = self.irqs[0].index
2400	else:
2401	irq_id = 0
2402
2403	# compute numerical value for ptype
2404	ptype_id = 0xFFFFFFFF
2405	for x in xrange( len(PERIPHTYPES) ):
2406	if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x
2407
2408	if ( ptype_id == 0xFFFFFFFF ):
2409	print '[genmap error] in Periph.cbin()'
2410	print ' undefined peripheral type %s' % self.ptype
2411	sys.exit(1)
2412
2413	# compute numerical value for subtype
2414	subtype_id = 0xFFFFFFFF
2415	if (self.ptype == 'IOC'):
2416	for x in xrange( len(IOCSUBTYPES) ):
2417	if ( self.subtype == IOCSUBTYPES[x] ): subtype_id = x
2418	if (self.ptype == 'MWR'):
2419	for x in xrange( len(MWRSUBTYPES) ):
2420	if ( self.subtype == MWRSUBTYPES[x] ): subtype_id = x
2421
2422	byte_stream = bytearray()
2423	byte_stream += mapping.int2bytes(4,ptype_id) # peripheral type
2424	byte_stream += mapping.int2bytes(4,subtype_id) # peripheral subtype
2425	byte_stream += mapping.int2bytes(4,pseg_id) # pseg global index
2426	byte_stream += mapping.int2bytes(4,self.channels) # number of channels
2427	byte_stream += mapping.int2bytes(4,self.arg0) # optionnal arg0
2428	byte_stream += mapping.int2bytes(4,self.arg1) # optionnal arg1
2429	byte_stream += mapping.int2bytes(4,self.arg2) # optionnal arg2
2430	byte_stream += mapping.int2bytes(4,self.arg3) # optionnal arg3
2431	byte_stream += mapping.int2bytes(4,len(self.irqs)) # number of input irqs
2432	byte_stream += mapping.int2bytes( 4 , irq_id ) # global index
2433
2434	if ( verbose ):
2435	print 'ptype = %d' % ptype_id
2436	print 'subtype = %d' % subtype_id
2437	print 'pseg_id = %d' % pseg_id
2438	print 'nb_irqs = %d' % len( self.irqs )
2439	print 'irq_id = %d' % irq_id
2440	return byte_stream
2441
2442	##################################################################################
2443	class Irq ( object ):
2444	##################################################################################
2445	def __init__( self,
2446	irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only)
2447	srcid, # input IRQ index (for XCU or PIC)
2448	isrtype, # Type of ISR to be executed
2449	channel = 0 ): # channel index for multi-channel ISR
2450
2451	assert irqtype in IRQTYPES
2452	assert isrtype in ISRTYPES
2453	assert srcid < 32
2454
2455	self.index = 0 # global index ( set by addIrq() )
2456	self.irqtype = irqtype # IRQ type
2457	self.srcid = srcid # source IRQ index
2458	self.isrtype = isrtype # ISR type
2459	self.channel = channel # channel index (for multi-channels ISR)
2460	return
2461
2462	################################
2463	def xml( self ): # xml for Irq
2464
2465	s = ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" />\n' \
2466	% ( self.irqtype, self.srcid, self.isrtype, self.channel )
2467	return s
2468
2469	####################################################################
2470	def cbin( self, mapping, verbose, expected ): # C binary for Irq
2471
2472	if ( verbose ):
2473	print '*** cbin for irq[%d]' % (self.index)
2474
2475	# check index
2476	if (self.index != expected):
2477	print '[genmap error] in Irq.cbin()'
2478	print ' irq global index = %d / expected = %d' \
2479	% (self.index,expected)
2480	sys.exit(1)
2481
2482	# compute numerical value for irqtype
2483	irqtype_id = 0xFFFFFFFF
2484	for x in xrange( len(IRQTYPES) ):
2485	if ( self.irqtype == IRQTYPES[x] ): irqtype_id = x
2486
2487	if ( irqtype_id == 0xFFFFFFFF ):
2488	print '[genmap error] in Irq.cbin()'
2489	print ' undefined irqtype %s' % self.irqtype
2490	sys.exit(1)
2491
2492	# compute numerical value for isrtype
2493	isrtype_id = 0xFFFFFFFF
2494	for x in xrange( len(ISRTYPES) ):
2495	if ( self.isrtype == ISRTYPES[x] ): isrtype_id = x
2496
2497	if ( isrtype_id == 0xFFFFFFFF ):
2498	print '[genmap error] in Irq.cbin()'
2499	print ' undefined isrtype %s' % self.isrtype
2500	sys.exit(1)
2501
2502	byte_stream = bytearray()
2503	byte_stream += mapping.int2bytes( 4, irqtype_id )
2504	byte_stream += mapping.int2bytes( 4, self.srcid )
2505	byte_stream += mapping.int2bytes( 4, isrtype_id )
2506	byte_stream += mapping.int2bytes( 4, self.channel )
2507	byte_stream += mapping.int2bytes( 4, 0 )
2508	byte_stream += mapping.int2bytes( 4, 0 )
2509
2510	if ( verbose ):
2511	print 'irqtype = %s' % self.irqtype
2512	print 'srcid = %d' % self.srcid
2513	print 'isrtype = %s' % self.isrtype
2514	print 'channel = %d' % self.channel
2515
2516	return byte_stream
2517
2518	# Local Variables:
2519	# tab-width: 4;
2520	# c-basic-offset: 4;
2521	# c-file-offsets:((innamespace . 0)(inline-open . 0));
2522	# indent-tabs-mode: nil;
2523	# End:
2524	#
2525	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
2526

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