| 1 | #!/usr/bin/env python |
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| 2 | |
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| 3 | from mapping import * |
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| 4 | |
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| 5 | #################################################################################width # |
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| 6 | # file : tsar_generic_iob.py |
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| 7 | # date : april 2014 |
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| 8 | # author : Alain Greiner |
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| 9 | ####################################################################################### |
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| 10 | # This file contains a mapping generator for the tsar_generic_iob platform. |
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| 11 | # This includes both the hardware architecture (clusters, processors, peripherals, |
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| 12 | # physical space segmentation) and the mapping of all kernel objects (global vsegs). |
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| 13 | # The parameters are: |
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| 14 | # - x_size : number of clusters in a row |
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| 15 | # - y_size : number of clusters in a column |
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| 16 | # - nb_procs : number of processors per cluster |
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| 17 | # - nb_ttys : number of TTY channels |
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| 18 | # - nb_nics : number of NIC channels |
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| 19 | # - fbf_size : frame_buffer width = frame_buffer heigth |
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| 20 | # - x_io : cluster_io x coordinate |
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| 21 | # - y_io : cluster_io y coordinate |
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| 22 | #################################################################################### |
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| 23 | |
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| 24 | ##################################### |
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| 25 | def tsar_generic_iob( x_size = 2, |
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| 26 | y_size = 2, |
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| 27 | nb_procs = 1, |
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| 28 | nb_ttys = 1, |
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| 29 | nb_nics = 2, |
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| 30 | fbf_width = 128, |
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| 31 | x_io = 0, |
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| 32 | y_io = 0 ): |
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| 33 | |
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| 34 | ### parameters checking |
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| 35 | assert ( nb_procs <= 4 ) |
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| 36 | assert ( (x_size == 1) or (x_size == 2) or (x_size == 4) |
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| 37 | or (y_size == 8) or (x_size == 16) ) |
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| 38 | assert ( (y_size == 1) or (y_size == 2) or (y_size == 4) |
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| 39 | or (y_size == 8) or (y_size == 16) ) |
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| 40 | assert ( nb_ttys <= 2 ) |
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| 41 | |
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| 42 | ### define architecture constants |
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| 43 | |
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| 44 | platform_name = 'tsar_iob_%d_%d_%d' % (x_size, y_size, nb_procs) |
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| 45 | x_width = 4 |
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| 46 | y_width = 4 |
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| 47 | paddr_width = 40 |
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| 48 | irq_per_proc = 1 |
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| 49 | use_ramdisk = False |
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| 50 | |
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| 51 | ### define physical segments |
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| 52 | |
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| 53 | ram_base = 0x0000000000 |
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| 54 | ram_size = 0x4000000 # 64 Mbytes |
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| 55 | |
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| 56 | xcu_base = 0x00B0000000 |
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| 57 | xcu_size = 0x1000 # 4 Kbytes |
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| 58 | |
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| 59 | dma_base = 0x00B1000000 |
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| 60 | dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs |
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| 61 | |
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| 62 | mmc_base = 0x00B2000000 |
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| 63 | mmc_size = 0x1000 # 4 Kbytes |
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| 64 | |
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| 65 | offset_io = ((x_io << y_width) + y_io) << (paddr_width - x_width - y_width) |
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| 66 | |
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| 67 | bdv_base = 0x00B3000000 + offset_io |
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| 68 | bdv_size = 0x1000 # 4kbytes |
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| 69 | |
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| 70 | tty_base = 0x00B4000000 + offset_io |
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| 71 | tty_size = 0x4000 # 16 Kbytes |
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| 72 | |
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| 73 | nic_base = 0x00B5000000 + offset_io |
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| 74 | nic_size = 0x80000 # 512 kbytes |
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| 75 | |
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| 76 | cma_base = 0x00B6000000 + offset_io |
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| 77 | cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics |
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| 78 | |
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| 79 | fbf_base = 0x00B7000000 + offset_io |
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| 80 | fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes |
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| 81 | |
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| 82 | pic_base = 0x00B8000000 + offset_io |
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| 83 | pic_size = 0x1000 # 4 Kbytes |
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| 84 | |
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| 85 | iob_base = 0x00BE000000 + offset_io |
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| 86 | iob_size = 0x1000 # 4kbytes |
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| 87 | |
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| 88 | rom_base = 0x00BFC00000 + offset_io |
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| 89 | rom_size = 0x4000 # 16 Kbytes |
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| 90 | |
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| 91 | ### define bootloader vsegs base addresses |
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| 92 | |
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| 93 | boot_mapping_vbase = 0x00000000 # ident |
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| 94 | boot_mapping_vsize = 0x00010000 # 64 Kbytes |
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| 95 | |
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| 96 | boot_code_vbase = 0x00010000 # ident |
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| 97 | boot_code_vsize = 0x00020000 # 128 Kbytes |
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| 98 | |
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| 99 | boot_data_vbase = 0x00030000 # ident |
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| 100 | boot_data_vsize = 0x00010000 # 64 Kbytes |
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| 101 | |
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| 102 | boot_buffer_vbase = 0x00040000 # ident |
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| 103 | boot_buffer_vsize = 0x00060000 # 384 Kbytes |
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| 104 | |
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| 105 | boot_stack_vbase = 0x000A0000 # ident |
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| 106 | boot_stack_vsize = 0x00050000 # 320 Kbytes |
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| 107 | |
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| 108 | ### define kernel vsegs base addresses |
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| 109 | |
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| 110 | kernel_code_vbase = 0x80000000 |
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| 111 | kernel_code_vsize = 0x00020000 # 128 Kbytes |
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| 112 | |
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| 113 | kernel_data_vbase = 0x80020000 |
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| 114 | kernel_data_vsize = 0x00060000 # 384 Kbytes |
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| 115 | |
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| 116 | kernel_uncdata_vbase = 0x80080000 |
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| 117 | kernel_uncdata_vsize = 0x00040000 # 256 Kbytes |
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| 118 | |
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| 119 | kernel_init_vbase = 0x800C0000 |
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| 120 | kernel_init_vsize = 0x00010000 # 64 Kbytes |
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| 121 | |
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| 122 | kernel_sched_vbase = 0xF0000000 # distributed in all clusters |
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| 123 | kernel_sched_vsize = 0x1000 * nb_procs # 4 kbytes per processor |
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| 124 | |
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| 125 | ### create mapping |
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| 126 | |
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| 127 | mapping = Mapping( name = platform_name, |
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| 128 | x_size = x_size, |
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| 129 | y_size = y_size, |
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| 130 | nb_procs = nb_procs, |
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| 131 | x_width = x_width, |
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| 132 | y_width = y_width, |
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| 133 | paddr_width = paddr_width, |
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| 134 | coherence = True, |
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| 135 | irq_per_proc = irq_per_proc, |
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| 136 | use_ramdisk = use_ramdisk, |
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| 137 | x_io = x_io, |
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| 138 | y_io = y_io ) |
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| 139 | |
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| 140 | ### add external peripherals |
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| 141 | |
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| 142 | iob = Iob( 'PSEG_IOB', base = iob_base, size = iob_size ) |
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| 143 | mapping.addPeripheral( iob ) |
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| 144 | |
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| 145 | bdv = Bdv( 'PSEG_BDV', base = bdv_base, size = bdv_size ) |
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| 146 | mapping.addPeripheral( bdv ) |
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| 147 | |
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| 148 | tty = Tty( 'PSEG_TTY', base = tty_base, size = tty_size, channels = nb_ttys ) |
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| 149 | mapping.addPeripheral( tty ) |
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| 150 | |
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| 151 | nic = Nic( 'PSEG_NIC', base = nic_base, size = nic_size, channels = nb_nics ) |
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| 152 | mapping.addPeripheral( nic ) |
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| 153 | |
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| 154 | cma = Cma( 'PSEG_CMA', base = cma_base, size = cma_size, channels = 2 * nb_nics ) |
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| 155 | mapping.addPeripheral( cma ) |
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| 156 | |
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| 157 | fbf = Fbf( 'PSEG_FBF', base = fbf_base, size = fbf_size ) |
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| 158 | mapping.addPeripheral( fbf ) |
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| 159 | |
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| 160 | rom = Rom( 'PSEG_ROM', base = rom_base, size = rom_size ) |
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| 161 | mapping.addPeripheral( rom ) |
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| 162 | |
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| 163 | pic = Pic( 'PSEG_PIC', base = pic_base, size = pic_size, channels = 32 ) |
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| 164 | pic.add( PicIrq( srcid = 0 , dstx = 0, dsty = 0, dstid = 4 ) ) |
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| 165 | pic.add( PicIrq( srcid = 1 , dstx = 0, dsty = 0, dstid = 5 ) ) |
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| 166 | pic.add( PicIrq( srcid = 2 , dstx = 0, dsty = 0, dstid = 6 ) ) |
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| 167 | pic.add( PicIrq( srcid = 3 , dstx = 0, dsty = 0, dstid = 7 ) ) |
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| 168 | pic.add( PicIrq( srcid = 4 , dstx = 0, dsty = 0, dstid = 8 ) ) |
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| 169 | pic.add( PicIrq( srcid = 5 , dstx = 0, dsty = 0, dstid = 9 ) ) |
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| 170 | pic.add( PicIrq( srcid = 6 , dstx = 0, dsty = 0, dstid = 10 ) ) |
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| 171 | pic.add( PicIrq( srcid = 7 , dstx = 0, dsty = 0, dstid = 11 ) ) |
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| 172 | pic.add( PicIrq( srcid = 8 , dstx = 0, dsty = 0, dstid = 12 ) ) |
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| 173 | pic.add( PicIrq( srcid = 16 , dstx = 0, dsty = 0, dstid = 13 ) ) |
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| 174 | pic.add( PicIrq( srcid = 17 , dstx = 0, dsty = 0, dstid = 14 ) ) |
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| 175 | pic.add( PicIrq( srcid = 18 , dstx = 0, dsty = 1, dstid = 13 ) ) |
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| 176 | pic.add( PicIrq( srcid = 19 , dstx = 0, dsty = 1, dstid = 14 ) ) |
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| 177 | pic.add( PicIrq( srcid = 20 , dstx = 1, dsty = 0, dstid = 13 ) ) |
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| 178 | pic.add( PicIrq( srcid = 21 , dstx = 1, dsty = 0, dstid = 14 ) ) |
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| 179 | pic.add( PicIrq( srcid = 22 , dstx = 1, dsty = 1, dstid = 13 ) ) |
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| 180 | pic.add( PicIrq( srcid = 23 , dstx = 1, dsty = 1, dstid = 14 ) ) |
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| 181 | mapping.addPeripheral( pic ) |
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| 182 | |
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| 183 | ### add components replicated in all clusters |
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| 184 | |
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| 185 | for x in xrange( x_size ): |
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| 186 | for y in xrange( y_size ): |
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| 187 | cluster_xy = (x << y_width) + y; |
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| 188 | offset = cluster_xy << (paddr_width - x_width - y_width) |
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| 189 | |
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| 190 | ram = Pseg( 'PSEG_RAM', base = ram_base + offset, size = ram_size, segtype = 'RAM' ) |
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| 191 | mapping.addPseg( ram ) |
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| 192 | |
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| 193 | mmc = Mmc( 'PSEG_MMC', base = mmc_base + offset, size = mmc_size ) |
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| 194 | mapping.addPeripheral( mmc ) |
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| 195 | |
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| 196 | dma = Dma( 'PSEG_DMA', base = dma_base + offset, size = dma_size, channels = nb_procs ) |
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| 197 | mapping.addPeripheral( dma ) |
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| 198 | |
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| 199 | xcu = Xcu( 'PSEG_XCU', base = xcu_base + offset, size = xcu_size, channels = nb_procs ) |
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| 200 | xcu.add ( XcuIrq ( srctype = 'HWI', srcid = 0, isrtype = 'ISR_MMC', dstid = 0 ) ) |
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| 201 | for p in xrange( nb_procs ): |
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| 202 | xcu.add ( XcuIrq ( srctype = 'WTI', srcid = p, isrtype = 'ISR_WAKUP', dstid = p ) ) |
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| 203 | xcu.add ( XcuIrq ( srctype = 'PTI', srcid = p, isrtype = 'ISR_TICK' , dstid = p ) ) |
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| 204 | if (x == 0) and (y == 0): |
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| 205 | xcu.add ( XcuIrq ( srctype = 'WTI', srcid = 4 , isrtype = 'ISR_NIC_RX', channel = 0) ) |
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| 206 | xcu.add ( XcuIrq ( srctype = 'WTI', srcid = 5 , isrtype = 'ISR_NIC_RX', channel = 1) ) |
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| 207 | xcu.add ( XcuIrq ( srctype = 'WTI', srcid = 6 , isrtype = 'ISR_NIC_TX', channel = 0) ) |
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| 208 | xcu.add ( XcuIrq ( srctype = 'WTI', srcid = 7 , isrtype = 'ISR_NIC_TX', channel = 1) ) |
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| 209 | xcu.add ( XcuIrq ( srctype = 'WTI', srcid = 8 , isrtype = 'ISR_CMA' , channel = 0) ) |
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| 210 | xcu.add ( XcuIrq ( srctype = 'WTI', srcid = 9 , isrtype = 'ISR_CMA' , channel = 1) ) |
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| 211 | xcu.add ( XcuIrq ( srctype = 'WTI', srcid = 10 , isrtype = 'ISR_CMA' , channel = 2) ) |
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| 212 | xcu.add ( XcuIrq ( srctype = 'WTI', srcid = 11 , isrtype = 'ISR_CMA' , channel = 3) ) |
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| 213 | xcu.add ( XcuIrq ( srctype = 'WTI', srcid = 12 , isrtype = 'ISR_BDV' , channel = 0) ) |
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| 214 | xcu.add ( XcuIrq ( srctype = 'WTI', srcid = 13 , isrtype = 'ISR_TTY_RX', channel = 0) ) |
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| 215 | xcu.add ( XcuIrq ( srctype = 'WTI', srcid = 14 , isrtype = 'ISR_TTY_RX', channel = 1) ) |
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| 216 | mapping.addPeripheral( xcu ) |
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| 217 | |
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| 218 | ### add processors |
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| 219 | |
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| 220 | for x in xrange (x_size): |
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| 221 | for y in xrange (y_size): |
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| 222 | for p in xrange (nb_procs): |
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| 223 | proc = Processor ( x, y, p ) |
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| 224 | mapping.addProc ( proc ) |
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| 225 | |
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| 226 | ### add global vsegs for boot_loader segments |
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| 227 | |
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| 228 | vseg = Vseg( 'seg_boot_mapping' , boot_mapping_vbase , 'C_W_' , 0, 0, 'PSEG_RAM', ident = True ) |
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| 229 | vseg.add ( Vobj( 'boot_mapping' , boot_mapping_vsize , 'BLOB' , binpath = 'map.bin' ) ) |
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| 230 | mapping.addGlobal( vseg ) |
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| 231 | |
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| 232 | vseg = Vseg( 'seg_boot_code' , boot_code_vbase , 'CXW_' , 0, 0, 'PSEG_RAM', ident = True ) |
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| 233 | vseg.add ( Vobj( 'boot_code' , boot_code_vsize , 'BUFFER' ) ) |
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| 234 | mapping.addGlobal( vseg ) |
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| 235 | |
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| 236 | vseg = Vseg( 'seg_boot_data' , boot_data_vbase , 'C_W_' , 0, 0, 'PSEG_RAM', ident = True ) |
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| 237 | vseg.add ( Vobj( 'boot_data' , boot_data_vsize , 'BUFFER' ) ) |
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| 238 | mapping.addGlobal( vseg ) |
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| 239 | |
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| 240 | vseg = Vseg( 'seg_boot_buffer' , boot_buffer_vbase , 'C_W_' , 0, 0, 'PSEG_RAM', ident = True ) |
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| 241 | vseg.add ( Vobj( 'boot_buffer' , boot_buffer_vsize , 'BUFFER' ) ) |
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| 242 | mapping.addGlobal( vseg ) |
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| 243 | |
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| 244 | vseg = Vseg( 'seg_boot_stack' , boot_stack_vbase , 'C_W_' , 0, 0, 'PSEG_RAM', ident = True ) |
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| 245 | vseg.add ( Vobj( 'boot_stack' , boot_stack_vsize , 'BUFFER' ) ) |
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| 246 | mapping.addGlobal( vseg ) |
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| 247 | |
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| 248 | ### add global vsegs for kernel segments |
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| 249 | |
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| 250 | vseg = Vseg( 'seg_kernel_code' , kernel_code_vbase , 'CXW_' , 0, 0, 'PSEG_RAM' ) |
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| 251 | vseg.add ( Vobj( 'kernel_code' , kernel_code_vsize , 'ELF' , binpath = 'build/kernel/kernel.elf' ) ) |
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| 252 | mapping.addGlobal( vseg ) |
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| 253 | |
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| 254 | vseg = Vseg( 'seg_kernel_data' , kernel_data_vbase , 'C_W_' , 0, 0, 'PSEG_RAM' ) |
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| 255 | vseg.add ( Vobj( 'kernel_data' , kernel_data_vsize , 'ELF' , binpath = 'build/kernel/kernel.elf' ) ) |
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| 256 | mapping.addGlobal( vseg ) |
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| 257 | |
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| 258 | vseg = Vseg( 'seg_kernel_uncdata' , kernel_uncdata_vbase , '__W_' , 0, 0, 'PSEG_RAM' ) |
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| 259 | vseg.add ( Vobj( 'kernel_uncdata' , kernel_uncdata_vsize , 'ELF' , binpath = 'build/kernel/kernel.elf' ) ) |
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| 260 | mapping.addGlobal( vseg ) |
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| 261 | |
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| 262 | vseg = Vseg( 'seg_kernel_init' , kernel_init_vbase , 'CXW_' , 0, 0, 'PSEG_RAM' ) |
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| 263 | vseg.add ( Vobj( 'kernel_init' , kernel_init_vsize , 'ELF' , binpath = 'build/kernel/kernel.elf' ) ) |
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| 264 | mapping.addGlobal( vseg ) |
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| 265 | |
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| 266 | ### add global vsegs for external peripherals |
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| 267 | |
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| 268 | vseg = Vseg( 'seg_iob' , iob_base , '__W_' , 0, 0, 'PSEG_IOB' ) |
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| 269 | vseg.add ( Vobj( 'iob' , iob_size , 'PERI' ) ) |
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| 270 | mapping.addGlobal( vseg ) |
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| 271 | |
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| 272 | vseg = Vseg( 'seg_bdv' , bdv_base , '__W_' , 0, 0, 'PSEG_BDV' ) |
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| 273 | vseg.add ( Vobj( 'bdv' , bdv_size , 'PERI' ) ) |
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| 274 | mapping.addGlobal( vseg ) |
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| 275 | |
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| 276 | vseg = Vseg( 'seg_tty' , tty_base , '__W_' , 0, 0, 'PSEG_TTY' ) |
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| 277 | vseg.add ( Vobj( 'tty' , tty_size , 'PERI' ) ) |
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| 278 | mapping.addGlobal( vseg ) |
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| 279 | |
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| 280 | vseg = Vseg( 'seg_nic' , nic_base , '__W_' , 0, 0, 'PSEG_NIC' ) |
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| 281 | vseg.add ( Vobj( 'nic' , nic_size , 'PERI' ) ) |
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| 282 | mapping.addGlobal( vseg ) |
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| 283 | |
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| 284 | vseg = Vseg( 'seg_cma' , cma_base , '__W_' , 0, 0, 'PSEG_CMA' ) |
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| 285 | vseg.add ( Vobj( 'cma' , cma_size , 'PERI' ) ) |
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| 286 | mapping.addGlobal( vseg ) |
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| 287 | |
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| 288 | vseg = Vseg( 'seg_fbf' , fbf_base , '__W_' , 0, 0, 'PSEG_FBF' ) |
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| 289 | vseg.add ( Vobj( 'fbf' , fbf_size , 'PERI' ) ) |
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| 290 | mapping.addGlobal( vseg ) |
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| 291 | |
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| 292 | vseg = Vseg( 'seg_pic' , pic_base , '__W_' , 0, 0, 'PSEG_PIC' ) |
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| 293 | vseg.add ( Vobj( 'pic' , pic_size , 'PERI' ) ) |
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| 294 | mapping.addGlobal( vseg ) |
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| 295 | |
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| 296 | vseg = Vseg( 'seg_rom' , rom_base , 'CXW_' , 0, 0, 'PSEG_ROM' ) |
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| 297 | vseg.add ( Vobj( 'rom' , rom_size , 'PERI' ) ) |
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| 298 | mapping.addGlobal( vseg ) |
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| 299 | |
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| 300 | ### Global vsegs for replicated XCU, DMA, MMC and Scheduler ### |
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| 301 | |
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| 302 | for x in xrange (x_size): |
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| 303 | for y in xrange (y_size): |
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| 304 | offset = ((x << y_width) + y) << 16 |
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| 305 | |
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| 306 | vseg = Vseg( 'seg_xcu_%d_%d' %(x,y) , xcu_base + offset, '__W_' , x, y, 'PSEG_XCU' ) |
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| 307 | vseg.add ( Vobj( 'xcu_%d_%d' %(x,y) , xcu_size, 'PERI' ) ) |
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| 308 | mapping.addGlobal( vseg ) |
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| 309 | |
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| 310 | vseg = Vseg( 'seg_dma_%d_%d' %(x,y) , dma_base + offset, '__W_' , x, y, 'PSEG_DMA' ) |
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| 311 | vseg.add ( Vobj( 'dma_%d_%d' %(x,y) , dma_size, 'PERI' ) ) |
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| 312 | mapping.addGlobal( vseg ) |
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| 313 | |
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| 314 | vseg = Vseg( 'seg_mmc_%d_%d' %(x,y) , mmc_base + offset, '__W_' , x, y, 'PSEG_MMC' ) |
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| 315 | vseg.add ( Vobj( 'mmc_%d_%d' %(x,y) , mmc_size, 'PERI' ) ) |
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| 316 | mapping.addGlobal( vseg ) |
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| 317 | |
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| 318 | vseg = Vseg( 'seg_sch_%d_%d' %(x,y) , kernel_sched_vbase + offset, '__W_' , x, y, 'PSEG_RAM' ) |
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| 319 | vseg.add ( Vobj( 'sch_%d_%d' %(x,y) , kernel_sched_vsize, 'SCHED' ) ) |
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| 320 | mapping.addGlobal( vseg ) |
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| 321 | |
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| 322 | ### return mapping ### |
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| 323 | |
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| 324 | return mapping |
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| 325 | |
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| 326 | ################################# transpose test ####################################################### |
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| 327 | |
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| 328 | if __name__ == '__main__': |
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| 329 | print tsar_generic_iob() |
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| 330 | |
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| 331 | |
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| 332 | # Local Variables: |
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| 333 | # tab-width: 4; |
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| 334 | # c-basic-offset: 4; |
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| 335 | # c-file-offsets:((innamespace . 0)(inline-open . 0)); |
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| 336 | # indent-tabs-mode: nil; |
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| 337 | # End: |
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| 338 | # |
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| 339 | # vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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![(please configure the [header_logo] section in trac.ini)](/trac/giet-vm/chrome/site/your_project_logo.png){kind=logo}
