1 | #!/usr/bin/env python |
---|
2 | |
---|
3 | from mapping import * |
---|
4 | |
---|
5 | ####################################################################################### |
---|
6 | # file : tsar_generic_leti.py |
---|
7 | # date : april 2014 |
---|
8 | # author : Alain Greiner |
---|
9 | ####################################################################################### |
---|
10 | # This file contains a mapping generator for the tsar_generic_leti platform. |
---|
11 | # This includes both the hardware architecture (clusters, processors, peripherals, |
---|
12 | # physical space segmentation) and the mapping of all kernel objects (global vsegs). |
---|
13 | # This platform does not include any external peripherals, but only a block-device |
---|
14 | # controler and a single channel TTY in cluster[0,0]. |
---|
15 | # The parameters are: |
---|
16 | # - x_size : number of clusters in a row |
---|
17 | # - y_size : number of clusters in a column |
---|
18 | # - nb_procs : number of processors per cluster |
---|
19 | ####################################################################################### |
---|
20 | |
---|
21 | ##################################### |
---|
22 | def tsar_generic_leti( x_size = 2, |
---|
23 | y_size = 2, |
---|
24 | nb_procs = 4 ): |
---|
25 | |
---|
26 | ### parameters checking |
---|
27 | |
---|
28 | assert ( nb_procs <= 4 ) |
---|
29 | assert ( (x_size==1) or (x_size==2) or (x_size==4) or (x_size==8) or (x_size==16) ) |
---|
30 | assert ( (y_size==1) or (y_size==2) or (y_size==4) or (y_size==8) ) |
---|
31 | |
---|
32 | ### define architecture constants |
---|
33 | |
---|
34 | platform_name = 'tsar_leti_%d_%d_%d' % (x_size, y_size, nb_procs) |
---|
35 | x_width = 4 |
---|
36 | y_width = 4 |
---|
37 | paddr_width = 40 |
---|
38 | irq_per_proc = 4 |
---|
39 | use_ram_disk = True |
---|
40 | x_io = 0 |
---|
41 | y_io = 0 |
---|
42 | |
---|
43 | ### physical segments |
---|
44 | |
---|
45 | ram_base = 0x0000000000 |
---|
46 | ram_size = 0x4000000 # 64 Mbytes |
---|
47 | |
---|
48 | xcu_base = 0x00F0000000 |
---|
49 | xcu_size = 0x1000 # 4 Kbytes |
---|
50 | |
---|
51 | mmc_base = 0x00E0000000 |
---|
52 | mmc_size = 0x1000 # 4 Kbytes |
---|
53 | |
---|
54 | bdv_base = 0x00F2000000 |
---|
55 | bdv_size = 0x1000 # 4 Kbytes |
---|
56 | |
---|
57 | tty_base = 0x00F4000000 |
---|
58 | tty_size = 0x1000 # 4 Kbytes |
---|
59 | |
---|
60 | ### Global vsegs / identity mapping |
---|
61 | |
---|
62 | reset_vbase = 0x00000000 |
---|
63 | reset_vsize = 0x00010000 # 64 Kbytes |
---|
64 | |
---|
65 | boot_code_vbase = 0x00010000 |
---|
66 | boot_code_vsize = 0x00020000 # 128 Kbytes |
---|
67 | |
---|
68 | boot_data_vbase = 0x00030000 |
---|
69 | boot_data_vsize = 0x00010000 # 64 Kbytes |
---|
70 | |
---|
71 | boot_buffer_vbase = 0x00040000 |
---|
72 | boot_buffer_vsize = 0x00060000 # 384 Kbytes |
---|
73 | |
---|
74 | boot_stack_vbase = 0x000A0000 |
---|
75 | boot_stack_vsize = 0x00050000 # 320 Kbytes |
---|
76 | |
---|
77 | boot_mapping_vbase = 0x000F0000 |
---|
78 | boot_mapping_vsize = 0x00010000 # 64 Kbytes |
---|
79 | |
---|
80 | ram_disk_vbase = 0x02000000 |
---|
81 | ram_disk_vsize = 0x02000000 # 1 Mbytes |
---|
82 | |
---|
83 | ### Global vsegs / no identity mapping |
---|
84 | |
---|
85 | kernel_code_vbase = 0x80000000 |
---|
86 | kernel_code_vsize = 0x00020000 # 128 Kbytes |
---|
87 | |
---|
88 | kernel_data_vbase = 0x80020000 |
---|
89 | kernel_data_vsize = 0x00060000 # 384 Kbytes |
---|
90 | |
---|
91 | kernel_uncdata_vbase = 0x80080000 |
---|
92 | kernel_uncdata_vsize = 0x00040000 # 256 Kbytes |
---|
93 | |
---|
94 | kernel_init_vbase = 0x800C0000 |
---|
95 | kernel_init_vsize = 0x00010000 # 64 Kbytes |
---|
96 | |
---|
97 | kernel_sched_vbase = 0x800D0000 # distributed in all clusters |
---|
98 | kernel_sched_vsize = 0x1000 * nb_procs # 4 kbytes per processor |
---|
99 | |
---|
100 | ### create mapping |
---|
101 | |
---|
102 | mapping = Mapping( name = platform_name, |
---|
103 | x_size = x_size, |
---|
104 | y_size = y_size, |
---|
105 | nb_procs = nb_procs, |
---|
106 | x_width = x_width, |
---|
107 | y_width = y_width, |
---|
108 | paddr_width = paddr_width, |
---|
109 | coherence = True, |
---|
110 | irq_per_proc = irq_per_proc, |
---|
111 | use_ram_disk = use_ram_disk, |
---|
112 | x_io = x_io, |
---|
113 | y_io = y_io ) |
---|
114 | |
---|
115 | ### add components in clusters |
---|
116 | |
---|
117 | for x in xrange( x_size ): |
---|
118 | for y in xrange( y_size ): |
---|
119 | cluster_xy = (x << y_width) + y; |
---|
120 | offset = cluster_xy << (paddr_width - x_width - y_width) |
---|
121 | |
---|
122 | if( (x==0) and (y==0) ): |
---|
123 | bdv = Bdv( 'PSEG_BDV', base = bdv_base , size = bdv_size ) |
---|
124 | mapping.addPeripheral( bdv ) |
---|
125 | |
---|
126 | tty = Tty( 'PSEG_TTY', base = tty_base , size = tty_size , channels = 1 ) |
---|
127 | mapping.addPeripheral( tty ) |
---|
128 | |
---|
129 | ram = Pseg( 'PSEG_RAM', base = ram_base + offset, size = ram_size, segtype = 'RAM' ) |
---|
130 | mapping.addPseg( ram ) |
---|
131 | |
---|
132 | mmc = Mmc( 'PSEG_MMC', base = mmc_base + offset, size = mmc_size ) |
---|
133 | mapping.addPeripheral( mmc ) |
---|
134 | |
---|
135 | xcu = Xcu( 'PSEG_XCU', base = xcu_base + offset, size = xcu_size, channels = nb_procs * irq_per_proc ) |
---|
136 | xcu.add ( XcuIrq ( srctype = 'HWI', srcid = 8 , isrtype = 'ISR_MMC' , dstid = 0 ) ) |
---|
137 | for p in xrange( nb_procs ): |
---|
138 | xcu.add ( XcuIrq ( srctype = 'WTI', srcid = p , isrtype = 'ISR_WAKUP' , dstid = p ) ) |
---|
139 | xcu.add ( XcuIrq ( srctype = 'PTI', srcid = p , isrtype = 'ISR_TICK' , dstid = p ) ) |
---|
140 | if ( (x==0) and (y==0) ): |
---|
141 | xcu.add ( XcuIrq ( srctype = 'HWI', srcid = 9 , isrtype = 'ISR_BDV' , dstid = 0 ) ) |
---|
142 | xcu.add ( XcuIrq ( srctype = 'HWI', srcid = 10 , isrtype = 'ISR_TTY_RX', dstid = 0 ) ) |
---|
143 | mapping.addPeripheral( xcu ) |
---|
144 | |
---|
145 | ### processors |
---|
146 | |
---|
147 | for x in xrange ( x_size ): |
---|
148 | for y in xrange ( y_size ): |
---|
149 | for p in xrange (nb_procs): |
---|
150 | proc = Processor ( x, y, p ) |
---|
151 | mapping.addProc ( proc ) |
---|
152 | |
---|
153 | ### glogal vsegs for Preloader and RamDisk / identity mapping |
---|
154 | |
---|
155 | vseg = Vseg( 'seg_reset_code' , reset_vbase , 'CX__' , 0, 0, 'PSEG_RAM', ident = True ) |
---|
156 | vseg.add ( Vobj( 'reset_code' , reset_vsize , 'BUFFER' ) ) |
---|
157 | mapping.addGlobal( vseg ) |
---|
158 | |
---|
159 | vseg = Vseg( 'seg_ram_disk' , ram_disk_vbase , 'CX__' , 0, 0, 'PSEG_RAM', ident = True ) |
---|
160 | vseg.add ( Vobj( 'reset_code' , ram_disk_vsize , 'BUFFER' ) ) |
---|
161 | mapping.addGlobal( vseg ) |
---|
162 | |
---|
163 | ### global vsegs for boot_loader segments / identity mapping |
---|
164 | |
---|
165 | vseg = Vseg( 'seg_boot_mapping' , boot_mapping_vbase , 'C_W_' , 0, 0, 'PSEG_RAM', ident = True ) |
---|
166 | vseg.add ( Vobj( 'boot_mapping' , boot_mapping_vsize , 'BLOB' , binpath = 'map.bin' ) ) |
---|
167 | mapping.addGlobal( vseg ) |
---|
168 | |
---|
169 | vseg = Vseg( 'seg_boot_code' , boot_code_vbase , 'CXW_' , 0, 0, 'PSEG_RAM', ident = True ) |
---|
170 | vseg.add ( Vobj( 'boot_code' , boot_code_vsize , 'BUFFER' ) ) |
---|
171 | mapping.addGlobal( vseg ) |
---|
172 | |
---|
173 | vseg = Vseg( 'seg_boot_data' , boot_data_vbase , 'C_W_' , 0, 0, 'PSEG_RAM', ident = True ) |
---|
174 | vseg.add ( Vobj( 'boot_data' , boot_data_vsize , 'BUFFER' ) ) |
---|
175 | mapping.addGlobal( vseg ) |
---|
176 | |
---|
177 | vseg = Vseg( 'seg_boot_buffer' , boot_buffer_vbase , 'C_W_' , 0, 0, 'PSEG_RAM', ident = True ) |
---|
178 | vseg.add ( Vobj( 'boot_buffer' , boot_buffer_vsize , 'BUFFER' ) ) |
---|
179 | mapping.addGlobal( vseg ) |
---|
180 | |
---|
181 | vseg = Vseg( 'seg_boot_stack' , boot_stack_vbase , 'C_W_' , 0, 0, 'PSEG_RAM', ident = True ) |
---|
182 | vseg.add ( Vobj( 'boot_stack' , boot_stack_vsize , 'BUFFER' ) ) |
---|
183 | mapping.addGlobal( vseg ) |
---|
184 | |
---|
185 | ### add global vsegs for kernel segments |
---|
186 | |
---|
187 | vseg = Vseg( 'seg_kernel_code' , kernel_code_vbase , 'CXW_' , 0, 0, 'PSEG_RAM' ) |
---|
188 | vseg.add ( Vobj( 'kernel_code' , kernel_code_vsize , 'ELF' , binpath = 'build/kernel/kernel.elf' ) ) |
---|
189 | mapping.addGlobal( vseg ) |
---|
190 | |
---|
191 | vseg = Vseg( 'seg_kernel_data' , kernel_data_vbase , 'C_W_' , 0, 0, 'PSEG_RAM' ) |
---|
192 | vseg.add ( Vobj( 'kernel_data' , kernel_data_vsize , 'ELF' , binpath = 'build/kernel/kernel.elf' ) ) |
---|
193 | mapping.addGlobal( vseg ) |
---|
194 | |
---|
195 | vseg = Vseg( 'seg_kernel_uncdata' , kernel_uncdata_vbase , '__W_' , 0, 0, 'PSEG_RAM' ) |
---|
196 | vseg.add ( Vobj( 'kernel_uncdata' , kernel_uncdata_vsize , 'ELF' , binpath = 'build/kernel/kernel.elf' ) ) |
---|
197 | mapping.addGlobal( vseg ) |
---|
198 | |
---|
199 | vseg = Vseg( 'seg_kernel_init' , kernel_init_vbase , 'CXW_' , 0, 0, 'PSEG_RAM' ) |
---|
200 | vseg.add ( Vobj( 'kernel_init' , kernel_init_vsize , 'ELF' , binpath = 'build/kernel/kernel.elf' ) ) |
---|
201 | mapping.addGlobal( vseg ) |
---|
202 | |
---|
203 | ### global vsegs for for bdv and tty peripherals |
---|
204 | |
---|
205 | vseg = Vseg( 'seg_bdv' , bdv_base , '__W_' , 0, 0, 'PSEG_BDV' ) |
---|
206 | vseg.add ( Vobj( 'bdv' , bdv_size , 'PERI' ) ) |
---|
207 | mapping.addGlobal( vseg ) |
---|
208 | |
---|
209 | vseg = Vseg( 'seg_tty' , tty_base , '__W_' , 0, 0, 'PSEG_TTY' ) |
---|
210 | vseg.add ( Vobj( 'tty' , tty_size , 'PERI' ) ) |
---|
211 | mapping.addGlobal( vseg ) |
---|
212 | |
---|
213 | ### Global vsegs for replicated XCU, MMC and Scheduler |
---|
214 | |
---|
215 | for x in xrange ( x_size ): |
---|
216 | for y in xrange ( y_size ): |
---|
217 | offset = ((x << y_width) + y) << 16 |
---|
218 | |
---|
219 | vseg = Vseg( 'seg_xcu_%d_%d' %(x,y) , xcu_base + offset, '__W_' , x, y, 'PSEG_XCU' ) |
---|
220 | vseg.add ( Vobj( 'xcu_%d_%d' %(x,y) , xcu_size, 'PERI' ) ) |
---|
221 | mapping.addGlobal( vseg ) |
---|
222 | |
---|
223 | vseg = Vseg( 'seg_mmc_%d_%d' %(x,y) , mmc_base + offset, '__W_' , x, y, 'PSEG_MMC' ) |
---|
224 | vseg.add ( Vobj( 'mmc_%d_%d' %(x,y) , mmc_size, 'PERI' ) ) |
---|
225 | mapping.addGlobal( vseg ) |
---|
226 | |
---|
227 | vseg = Vseg( 'seg_sch_%d_%d' %(x,y) , kernel_sched_vbase + offset, '__W_' , x, y, 'PSEG_RAM' ) |
---|
228 | vseg.add ( Vobj( 'sch_%d_%d' %(x,y) , kernel_sched_vsize, 'SCHED' ) ) |
---|
229 | mapping.addGlobal( vseg ) |
---|
230 | |
---|
231 | ### return mapping |
---|
232 | |
---|
233 | return mapping |
---|
234 | |
---|
235 | ################################# transpose test ####################################################### |
---|
236 | |
---|
237 | if __name__ == '__main__': |
---|
238 | print tsar_generic_leti() |
---|
239 | |
---|
240 | |
---|
241 | # Local Variables: |
---|
242 | # tab-width: 4; |
---|
243 | # c-basic-offset: 4; |
---|
244 | # c-file-offsets:((innamespace . 0)(inline-open . 0)); |
---|
245 | # indent-tabs-mode: nil; |
---|
246 | # End: |
---|
247 | # |
---|
248 | # vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
249 | |
---|