[447] | 1 | /* Generated by genmap for tsar_iob_2_2_2_1024_convol */ |
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| 2 | |
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| 3 | #ifndef HARD_CONFIG_H |
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| 4 | #define HARD_CONFIG_H |
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| 5 | |
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| 6 | /* General platform parameters */ |
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| 7 | |
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| 8 | #define X_SIZE 2 |
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| 9 | #define Y_SIZE 2 |
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| 10 | #define X_WIDTH 4 |
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| 11 | #define Y_WIDTH 4 |
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| 12 | #define P_WIDTH 4 |
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| 13 | #define X_IO 0 |
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| 14 | #define Y_IO 0 |
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| 15 | #define NB_PROCS_MAX 2 |
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| 16 | #define IRQ_PER_PROCESSOR 4 |
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| 17 | #define RESET_ADDRESS 0xbfc00000 |
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| 18 | #define NB_TOTAL_PROCS 8 |
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| 19 | |
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| 20 | /* Peripherals */ |
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| 21 | |
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| 22 | #define NB_TTY_CHANNELS 1 |
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| 23 | #define NB_IOC_CHANNELS 1 |
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| 24 | #define NB_NIC_CHANNELS 2 |
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| 25 | #define NB_CMA_CHANNELS 4 |
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| 26 | #define NB_TIM_CHANNELS 0 |
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| 27 | #define NB_DMA_CHANNELS 2 |
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| 28 | |
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| 29 | #define USE_XCU 1 |
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| 30 | #define USE_IOB 1 |
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| 31 | #define USE_PIC 1 |
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| 32 | #define USE_FBF 1 |
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| 33 | |
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| 34 | #define USE_IOC_BDV 1 |
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| 35 | #define USE_IOC_SPI 0 |
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| 36 | #define USE_IOC_HBA 0 |
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| 37 | #define USE_IOC_RDK 0 |
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| 38 | |
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| 39 | #define FBUF_X_SIZE 1024 |
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| 40 | #define FBUF_Y_SIZE 1024 |
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| 41 | |
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| 42 | #define XCU_NB_INPUTS 16 |
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| 43 | |
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| 44 | /* base addresses and sizes for physical segments */ |
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| 45 | |
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| 46 | #define SEG_RAM_BASE 0x0 |
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| 47 | #define SEG_RAM_SIZE 0x4000000 |
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| 48 | |
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| 49 | #define SEG_CMA_BASE 0xb6000000 |
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| 50 | #define SEG_CMA_SIZE 0x4000 |
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| 51 | |
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| 52 | #define SEG_DMA_BASE 0xb1000000 |
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| 53 | #define SEG_DMA_SIZE 0x1000 |
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| 54 | |
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| 55 | #define SEG_FBF_BASE 0xb7000000 |
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| 56 | #define SEG_FBF_SIZE 0x100000 |
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| 57 | |
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| 58 | #define SEG_IOB_BASE 0xbe000000 |
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| 59 | #define SEG_IOB_SIZE 0x1000 |
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| 60 | |
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| 61 | #define SEG_IOC_BASE 0xb3000000 |
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| 62 | #define SEG_IOC_SIZE 0x1000 |
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| 63 | |
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| 64 | #define SEG_MMC_BASE 0xb2000000 |
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| 65 | #define SEG_MMC_SIZE 0x1000 |
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| 66 | |
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| 67 | #define SEG_MWR_BASE 0xffffffff |
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| 68 | #define SEG_MWR_SIZE 0x0 |
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| 69 | |
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| 70 | #define SEG_ROM_BASE 0xbfc00000 |
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| 71 | #define SEG_ROM_SIZE 0x4000 |
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| 72 | |
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| 73 | #define SEG_SIM_BASE 0xffffffff |
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| 74 | #define SEG_SIM_SIZE 0x0 |
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| 75 | |
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| 76 | #define SEG_NIC_BASE 0xb5000000 |
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| 77 | #define SEG_NIC_SIZE 0x80000 |
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| 78 | |
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| 79 | #define SEG_PIC_BASE 0xb8000000 |
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| 80 | #define SEG_PIC_SIZE 0x1000 |
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| 81 | |
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| 82 | #define SEG_TIM_BASE 0xffffffff |
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| 83 | #define SEG_TIM_SIZE 0x0 |
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| 84 | |
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| 85 | #define SEG_TTY_BASE 0xb4000000 |
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| 86 | #define SEG_TTY_SIZE 0x4000 |
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| 87 | |
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| 88 | #define SEG_XCU_BASE 0xb0000000 |
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| 89 | #define SEG_XCU_SIZE 0x1000 |
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| 90 | |
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| 91 | #define SEG_RDK_BASE 0xffffffff |
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| 92 | #define SEG_RDK_SIZE 0x0 |
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| 93 | |
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| 94 | #define PERI_CLUSTER_INCREMENT 0x10000 |
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| 95 | |
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| 96 | /* physical base addresses for identity mapped vsegs */ |
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| 97 | /* used by the GietVM OS */ |
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| 98 | |
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| 99 | #define SEG_BOOT_MAPPING_BASE 0x0 |
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| 100 | #define SEG_BOOT_MAPPING_SIZE 0x80000 |
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| 101 | |
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| 102 | #define SEG_BOOT_CODE_BASE 0x80000 |
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| 103 | #define SEG_BOOT_CODE_SIZE 0x40000 |
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| 104 | |
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| 105 | #define SEG_BOOT_DATA_BASE 0xc0000 |
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| 106 | #define SEG_BOOT_DATA_SIZE 0x80000 |
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| 107 | |
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| 108 | #define SEG_BOOT_STACK_BASE 0x140000 |
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| 109 | #define SEG_BOOT_STACK_SIZE 0x50000 |
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| 110 | #endif |
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