[158] | 1 | #ifndef _HWR_MAPPING_H |
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| 2 | #define _HWR_MAPPING_H |
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| 3 | |
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| 4 | /* |
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| 5 | * Registers mapping for the different peripherals |
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| 6 | */ |
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| 7 | |
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| 8 | /* IOC (block device) */ |
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[238] | 9 | enum IOC_registers |
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| 10 | { |
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[158] | 11 | BLOCK_DEVICE_BUFFER, |
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| 12 | BLOCK_DEVICE_LBA, |
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| 13 | BLOCK_DEVICE_COUNT, |
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| 14 | BLOCK_DEVICE_OP, |
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| 15 | BLOCK_DEVICE_STATUS, |
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| 16 | BLOCK_DEVICE_IRQ_ENABLE, |
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| 17 | BLOCK_DEVICE_SIZE, |
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| 18 | BLOCK_DEVICE_BLOCK_SIZE, |
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[238] | 19 | BLOCK_DEVICE_BUFFER_EXT, |
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[158] | 20 | }; |
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[238] | 21 | enum IOC_operations |
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| 22 | { |
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[158] | 23 | BLOCK_DEVICE_NOOP, |
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| 24 | BLOCK_DEVICE_READ, |
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| 25 | BLOCK_DEVICE_WRITE, |
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| 26 | }; |
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[238] | 27 | enum IOC_status |
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| 28 | { |
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[158] | 29 | BLOCK_DEVICE_IDLE, |
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| 30 | BLOCK_DEVICE_BUSY, |
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| 31 | BLOCK_DEVICE_READ_SUCCESS, |
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| 32 | BLOCK_DEVICE_WRITE_SUCCESS, |
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| 33 | BLOCK_DEVICE_READ_ERROR, |
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| 34 | BLOCK_DEVICE_WRITE_ERROR, |
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| 35 | BLOCK_DEVICE_ERROR, |
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| 36 | }; |
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| 37 | |
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| 38 | /* DMA */ |
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[238] | 39 | enum DMA_registers |
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| 40 | { |
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[158] | 41 | DMA_SRC = 0, |
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| 42 | DMA_DST = 1, |
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| 43 | DMA_LEN = 2, |
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| 44 | DMA_RESET = 3, |
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| 45 | DMA_IRQ_DISABLE = 4, |
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[238] | 46 | DMA_SRC_EXT = 5, |
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| 47 | DMA_DST_EXT = 6, |
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[158] | 48 | /**/ |
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[238] | 49 | DMA_END = 7, |
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[158] | 50 | DMA_SPAN = 8, |
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| 51 | }; |
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| 52 | |
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[253] | 53 | /* CMA */ |
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| 54 | enum CMA_registers |
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| 55 | { |
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| 56 | CHBUF_RUN = 0, // write-only : channel activated |
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| 57 | CHBUF_STATUS = 1, // read-only : channel fsm state |
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| 58 | CHBUF_SRC_DESC = 2, // read/write : source chbuf : descriptor base address |
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| 59 | CHBUF_DST_DESC = 3, // read/write : destination chbuf : descriptor base address, |
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| 60 | CHBUF_SRC_NBUFS = 4, // read/write : source chbuf : number of buffers, |
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| 61 | CHBUF_DST_NBUFS = 5, // read/write : destination chbuf : number of buffers, |
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| 62 | CHBUF_BUF_SIZE = 6, // read/write : buffer size for both source & destination |
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| 63 | CHBUF_PERIOD = 7, // read/write : period for status polling |
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| 64 | CHBUF_SRC_EXT = 8, // read/write : source chbuf : descriptor base address |
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| 65 | CHBUF_DST_EXT = 9, // read/write : destination chbuf : descriptor base address, |
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| 66 | /****/ |
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| 67 | CHBUF_CHANNEL_SPAN = 1024, |
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| 68 | }; |
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| 69 | |
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[158] | 70 | /* GCD */ |
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[238] | 71 | enum GCD_registers |
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| 72 | { |
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[158] | 73 | GCD_OPA = 0, |
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| 74 | GCD_OPB = 1, |
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| 75 | GCD_START = 2, |
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| 76 | GCD_STATUS = 3, |
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| 77 | /**/ |
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| 78 | GCD_END = 4, |
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| 79 | }; |
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| 80 | |
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| 81 | /* ICU */ |
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[238] | 82 | enum ICU_registers |
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| 83 | { |
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[158] | 84 | ICU_INT = 0, |
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| 85 | ICU_MASK = 1, |
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| 86 | ICU_MASK_SET = 2, |
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| 87 | ICU_MASK_CLEAR = 3, |
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| 88 | ICU_IT_VECTOR = 4, |
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| 89 | /**/ |
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| 90 | ICU_END = 5, |
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| 91 | ICU_SPAN = 8, |
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| 92 | }; |
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[238] | 93 | enum Xicu_registers |
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| 94 | { |
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[203] | 95 | XICU_WTI_REG = 0, |
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| 96 | XICU_PTI_PER = 1, |
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| 97 | XICU_PTI_VAL = 2, |
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| 98 | XICU_PTI_ACK = 3, |
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[158] | 99 | |
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[203] | 100 | XICU_MSK_PTI = 4, |
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| 101 | XICU_MSK_PTI_ENABLE = 5, |
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| 102 | XICU_MSK_PTI_DISABLE = 6, |
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| 103 | XICU_PTI_ACTIVE = 6, |
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| 104 | |
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| 105 | XICU_MSK_HWI = 8, |
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| 106 | XICU_MSK_HWI_ENABLE = 9, |
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| 107 | XICU_MSK_HWI_DISABLE = 10, |
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| 108 | XICU_HWI_ACTIVE = 10, |
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| 109 | |
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| 110 | XICU_MSK_WTI = 12, |
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| 111 | XICU_MSK_WTI_ENABLE = 13, |
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| 112 | XICU_MSK_WTI_DISABLE = 14, |
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| 113 | XICU_WTI_ACTIVE = 14, |
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| 114 | |
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| 115 | XICU_PRIO = 15, |
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| 116 | }; |
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| 117 | |
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| 118 | #define XICU_REG(func, index) (((func)<<5)|(index)) |
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[228] | 119 | |
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[158] | 120 | /* TIMER */ |
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[238] | 121 | enum TIMER_registers |
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| 122 | { |
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[158] | 123 | TIMER_VALUE = 0, |
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| 124 | TIMER_MODE = 1, |
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| 125 | TIMER_PERIOD = 2, |
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| 126 | TIMER_RESETIRQ = 3, |
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| 127 | /**/ |
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| 128 | TIMER_SPAN = 4, |
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| 129 | }; |
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| 130 | |
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| 131 | /* TTY */ |
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[238] | 132 | enum TTY_registers |
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| 133 | { |
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[158] | 134 | TTY_WRITE = 0, |
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| 135 | TTY_STATUS = 1, |
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| 136 | TTY_READ = 2, |
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| 137 | TTY_CONFIG = 3, |
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| 138 | /**/ |
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| 139 | TTY_SPAN = 4, |
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| 140 | }; |
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| 141 | |
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[166] | 142 | /* IOB */ |
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[238] | 143 | enum IOB_registers |
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| 144 | { |
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[228] | 145 | IOB_IOMMU_PTPR = 0, /* R/W : Page Table Pointer Register */ |
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| 146 | IOB_IOMMU_ACTIVE = 1, /* R/W : IOMMU activated if not 0 */ |
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| 147 | IOB_IOMMU_BVAR = 2, /* R : Bad Virtual Address (unmapped) */ |
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| 148 | IOB_IOMMU_ETR = 3, /* R : Error Type */ |
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| 149 | IOB_IOMMU_BAD_ID = 4, /* R : Faulty Peripheral Index */ |
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| 150 | IOB_INVAL_PTE = 5, /* W : Invalidate a PTE (virtual address) */ |
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| 151 | IOB_IT_ADDR_IOMMU_LO = 6, /* W/R : 32 LSB bits for IOMMU IT*/ |
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| 152 | IOB_IT_ADDR_IOMMU_HI = 7, /* W/R : 32 MSB bits for IOMMU IT */ |
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| 153 | IOB_IT_ADDRESS_BEGIN = 8, /* R/W : Peripheral IT address (2 32 bits registers) */ |
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[166] | 154 | }; |
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| 155 | |
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[200] | 156 | /* MWMR */ |
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[238] | 157 | enum SoclibMwmrRegisters |
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| 158 | { |
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[200] | 159 | MWMR_IOREG_MAX = 16, |
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| 160 | MWMR_RESET = MWMR_IOREG_MAX, |
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| 161 | MWMR_CONFIG_FIFO_WAY, |
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| 162 | MWMR_CONFIG_FIFO_NO, |
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| 163 | MWMR_CONFIG_STATUS_ADDR, |
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| 164 | MWMR_CONFIG_DEPTH, |
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| 165 | MWMR_CONFIG_BUFFER_ADDR, |
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| 166 | MWMR_CONFIG_RUNNING, |
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| 167 | MWMR_CONFIG_WIDTH, |
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| 168 | MWMR_FIFO_FILL_STATUS, |
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| 169 | }; |
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| 170 | |
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[238] | 171 | enum SoclibMwmrWay |
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| 172 | { |
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[200] | 173 | MWMR_TO_COPROC, |
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| 174 | MWMR_FROM_COPROC, |
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| 175 | }; |
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| 176 | |
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[247] | 177 | /* Memory Cache (TSAR) */ |
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| 178 | enum SoclibMemCacheConfigRegs |
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| 179 | { |
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| 180 | MEMC_LOCK, |
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| 181 | MEMC_ADDR_LO, |
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| 182 | MEMC_ADDR_HI, |
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[252] | 183 | MEMC_BUF_LENGTH, |
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| 184 | MEMC_CMD_TYPE |
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[247] | 185 | }; |
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| 186 | |
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| 187 | enum SoclibMemCacheConfigCmd |
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| 188 | { |
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| 189 | MEMC_CMD_NOP, |
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| 190 | MEMC_CMD_INVAL, |
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| 191 | MEMC_CMD_SYNC |
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| 192 | }; |
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| 193 | |
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[255] | 194 | enum SoclibSimhelperRegisters |
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| 195 | { |
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| 196 | SIMHELPER_SC_STOP, |
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| 197 | SIMHELPER_END_WITH_RETVAL, |
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| 198 | SIMHELPER_EXCEPT_WITH_VAL, |
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| 199 | SIMHELPER_PAUSE_SIM, |
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| 200 | SIMHELPER_CYCLES, |
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| 201 | SIMHELPER_SIGINT, |
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| 202 | }; |
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| 203 | |
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| 204 | |
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| 205 | |
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[158] | 206 | #endif |
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| 207 | |
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[228] | 208 | // Local Variables: |
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| 209 | // tab-width: 4 |
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| 210 | // c-basic-offset: 4 |
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| 211 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 212 | // indent-tabs-mode: nil |
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| 213 | // End: |
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| 214 | // vim: filetype=c:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 215 | |
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