source: soft/giet_vm/sys/hwr_mapping.h @ 200

Last change on this file since 200 was 200, checked in by karaoui, 13 years ago

+ removing some bugs from:

  • xml_parser.c: check that strcmp == 0 for coproc direction
  • mwmr_channel.c: mwmr->ptr to ptr.
  • utils.h double definition of memcpy fonction.

+ mapping_info.h : naming the enums
+ boot_init.c: changing the order of initialisation in order

to initialise the coproc with the mwmr channel values( depth, width...).
Note that the vobjs are now physically initialised.

+ mwmr_channel.h: changing the order argument definition to suit vci_mwmr_channel Soclib componnent.
+ hwr_mapping.h: adding the register description of the vci_mwmr_controller .
File size: 2.6 KB
Line 
1#ifndef _HWR_MAPPING_H
2#define _HWR_MAPPING_H
3
4/*
5 * Registers mapping for the different peripherals
6 */
7
8/* IOC (block device) */
9enum IOC_registers {
10    BLOCK_DEVICE_BUFFER,
11    BLOCK_DEVICE_LBA,
12    BLOCK_DEVICE_COUNT,
13    BLOCK_DEVICE_OP,
14    BLOCK_DEVICE_STATUS,
15    BLOCK_DEVICE_IRQ_ENABLE,
16    BLOCK_DEVICE_SIZE,
17    BLOCK_DEVICE_BLOCK_SIZE,
18};
19enum IOC_operations {
20    BLOCK_DEVICE_NOOP,
21    BLOCK_DEVICE_READ,
22    BLOCK_DEVICE_WRITE,
23};
24enum IOC_status{
25    BLOCK_DEVICE_IDLE,
26    BLOCK_DEVICE_BUSY,
27    BLOCK_DEVICE_READ_SUCCESS,
28    BLOCK_DEVICE_WRITE_SUCCESS,
29    BLOCK_DEVICE_READ_ERROR,
30    BLOCK_DEVICE_WRITE_ERROR,
31    BLOCK_DEVICE_ERROR,
32};
33
34/* DMA */
35enum DMA_registers {
36    DMA_SRC         = 0,
37    DMA_DST         = 1,
38    DMA_LEN         = 2,
39    DMA_RESET       = 3,
40    DMA_IRQ_DISABLE = 4,
41    /**/
42    DMA_END         = 5,
43    DMA_SPAN        = 8,
44};
45
46/* GCD */
47enum GCD_registers {
48    GCD_OPA     = 0,
49    GCD_OPB     = 1,
50    GCD_START   = 2,
51    GCD_STATUS  = 3,
52    /**/
53    GCD_END     = 4,
54};
55
56/* ICU */
57enum ICU_registers {
58    ICU_INT         = 0,
59    ICU_MASK        = 1,
60    ICU_MASK_SET    = 2,
61    ICU_MASK_CLEAR  = 3,
62    ICU_IT_VECTOR   = 4,
63    /**/
64    ICU_END         = 5,
65    ICU_SPAN        = 8,
66};
67
68/* TIMER */
69enum TIMER_registers {
70    TIMER_VALUE     = 0,
71    TIMER_MODE      = 1,
72    TIMER_PERIOD    = 2,
73    TIMER_RESETIRQ  = 3,
74    /**/
75    TIMER_SPAN      = 4,
76};
77
78/* TTY */
79enum TTY_registers {
80    TTY_WRITE   = 0,
81    TTY_STATUS  = 1,
82    TTY_READ    = 2,
83    TTY_CONFIG  = 3,
84    /**/
85    TTY_SPAN    = 4,
86};
87
88/* IOB */
89enum IOB_registers {
90    IOB_IOMMU_PTPR       = 0,   /* R/W : Page Table Pointer Register */
91    IOB_IOMMU_ACTIVE     = 1,   /* R/W : IOMMU activated if not 0 */
92    IOB_IOMMU_BVAR       = 2,   /* R   : Bad Virtual Address (unmapped) */
93    IOB_IOMMU_ETR        = 3,   /* R   : Error Type */
94    IOB_IOMMU_BAD_ID     = 4,   /* R   : Faulty Peripheral Index */
95    IOB_INVAL_PTE        = 5,   /* W   : Invalidate a PTE (virtual address) */
96    IOB_IT_ADDR_IOMMU_LO = 6,   /* W/R : 32 LSB bits for IOMMU IT*/
97    IOB_IT_ADDR_IOMMU_HI = 7,   /* W/R : 32 MSB bits for IOMMU IT */
98    IOB_IT_ADDRESS_BEGIN = 8,   /* R/W : Peripheral IT address (2 32 bits registers) */
99};
100
101/* MWMR */
102enum SoclibMwmrRegisters {
103    MWMR_IOREG_MAX = 16,
104    MWMR_RESET = MWMR_IOREG_MAX,
105    MWMR_CONFIG_FIFO_WAY,
106    MWMR_CONFIG_FIFO_NO,
107    MWMR_CONFIG_STATUS_ADDR,
108    MWMR_CONFIG_DEPTH,
109    MWMR_CONFIG_BUFFER_ADDR,
110    MWMR_CONFIG_LOCK_ADDR,
111    MWMR_CONFIG_RUNNING,
112    MWMR_CONFIG_WIDTH,
113    MWMR_FIFO_FILL_STATUS,
114};
115
116enum SoclibMwmrWay {
117    MWMR_TO_COPROC,
118    MWMR_FROM_COPROC,
119};
120
121#endif
122
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