source: soft/giet_vm/sys/hwr_mapping.h @ 254

Last change on this file since 254 was 253, checked in by alain, 11 years ago

1/ introducing support to display images on the frame buffer
with the vci_chbuf_dma (in stdio.c and drivers.c)
2/ introducing support for mem_cache configuration segment
as the memory cache is considered as another addressable peripheral type
(in drivers.c)
3/ Introducing the new "increment" parameter in the mapping header.
This parameter define the virtual address increment for the vsegs
associated to the replicated peripherals (ICU, XICU, MDMA, TIMER, MMC).
This parameter is mandatory, and all map.xml files the "mappings"
directory have been updated.
File size: 4.5 KB
Line 
1#ifndef _HWR_MAPPING_H
2#define _HWR_MAPPING_H
3
4/*
5 * Registers mapping for the different peripherals
6 */
7
8/* IOC (block device) */
9enum IOC_registers
10{
11    BLOCK_DEVICE_BUFFER,
12    BLOCK_DEVICE_LBA,
13    BLOCK_DEVICE_COUNT,
14    BLOCK_DEVICE_OP,
15    BLOCK_DEVICE_STATUS,
16    BLOCK_DEVICE_IRQ_ENABLE,
17    BLOCK_DEVICE_SIZE,
18    BLOCK_DEVICE_BLOCK_SIZE,
19    BLOCK_DEVICE_BUFFER_EXT,
20};
21enum IOC_operations
22{
23    BLOCK_DEVICE_NOOP,
24    BLOCK_DEVICE_READ,
25    BLOCK_DEVICE_WRITE,
26};
27enum IOC_status
28{
29    BLOCK_DEVICE_IDLE,
30    BLOCK_DEVICE_BUSY,
31    BLOCK_DEVICE_READ_SUCCESS,
32    BLOCK_DEVICE_WRITE_SUCCESS,
33    BLOCK_DEVICE_READ_ERROR,
34    BLOCK_DEVICE_WRITE_ERROR,
35    BLOCK_DEVICE_ERROR,
36};
37
38/* DMA */
39enum DMA_registers
40{
41    DMA_SRC         = 0,
42    DMA_DST         = 1,
43    DMA_LEN         = 2,
44    DMA_RESET       = 3,
45    DMA_IRQ_DISABLE = 4,
46    DMA_SRC_EXT     = 5,
47    DMA_DST_EXT     = 6,
48    /**/
49    DMA_END         = 7,
50    DMA_SPAN        = 8,
51};
52
53/* CMA */
54enum CMA_registers
55{
56    CHBUF_RUN           = 0,    // write-only : channel activated
57    CHBUF_STATUS        = 1,    // read-only  : channel fsm state
58    CHBUF_SRC_DESC      = 2,    // read/write : source chbuf : descriptor base address
59    CHBUF_DST_DESC      = 3,    // read/write : destination chbuf : descriptor base address,
60    CHBUF_SRC_NBUFS     = 4,    // read/write : source chbuf : number of buffers,
61    CHBUF_DST_NBUFS     = 5,    // read/write : destination chbuf : number of buffers,
62    CHBUF_BUF_SIZE      = 6,    // read/write : buffer size for both source & destination 
63    CHBUF_PERIOD        = 7,    // read/write : period for status polling
64    CHBUF_SRC_EXT       = 8,    // read/write : source chbuf : descriptor base address
65    CHBUF_DST_EXT       = 9,    // read/write : destination chbuf : descriptor base address,
66    /****/
67    CHBUF_CHANNEL_SPAN  = 1024,
68};
69
70/* GCD */
71enum GCD_registers
72{
73    GCD_OPA     = 0,
74    GCD_OPB     = 1,
75    GCD_START   = 2,
76    GCD_STATUS  = 3,
77    /**/
78    GCD_END     = 4,
79};
80
81/* ICU */
82enum ICU_registers
83{
84    ICU_INT         = 0,
85    ICU_MASK        = 1,
86    ICU_MASK_SET    = 2,
87    ICU_MASK_CLEAR  = 3,
88    ICU_IT_VECTOR   = 4,
89    /**/
90    ICU_END         = 5,
91    ICU_SPAN        = 8,
92};
93enum Xicu_registers
94{
95    XICU_WTI_REG = 0,
96    XICU_PTI_PER = 1,
97    XICU_PTI_VAL = 2,
98    XICU_PTI_ACK = 3,
99
100    XICU_MSK_PTI = 4,
101    XICU_MSK_PTI_ENABLE = 5,
102    XICU_MSK_PTI_DISABLE = 6,
103    XICU_PTI_ACTIVE = 6,
104
105    XICU_MSK_HWI = 8,
106    XICU_MSK_HWI_ENABLE = 9,
107    XICU_MSK_HWI_DISABLE = 10,
108    XICU_HWI_ACTIVE = 10,
109
110    XICU_MSK_WTI = 12,
111    XICU_MSK_WTI_ENABLE = 13,
112    XICU_MSK_WTI_DISABLE = 14,
113    XICU_WTI_ACTIVE = 14,
114
115    XICU_PRIO = 15,
116};
117
118#define XICU_REG(func, index) (((func)<<5)|(index))
119
120/* TIMER */
121enum TIMER_registers
122{
123    TIMER_VALUE     = 0,
124    TIMER_MODE      = 1,
125    TIMER_PERIOD    = 2,
126    TIMER_RESETIRQ  = 3,
127    /**/
128    TIMER_SPAN      = 4,
129};
130
131/* TTY */
132enum TTY_registers
133{
134    TTY_WRITE   = 0,
135    TTY_STATUS  = 1,
136    TTY_READ    = 2,
137    TTY_CONFIG  = 3,
138    /**/
139    TTY_SPAN    = 4,
140};
141
142/* IOB */
143enum IOB_registers
144{
145    IOB_IOMMU_PTPR       = 0, /* R/W : Page Table Pointer Register */
146    IOB_IOMMU_ACTIVE     = 1, /* R/W : IOMMU activated if not 0 */
147    IOB_IOMMU_BVAR       = 2, /* R   : Bad Virtual Address (unmapped) */
148    IOB_IOMMU_ETR        = 3, /* R   : Error Type */
149    IOB_IOMMU_BAD_ID     = 4, /* R   : Faulty Peripheral Index */
150    IOB_INVAL_PTE        = 5, /* W   : Invalidate a PTE (virtual address) */
151    IOB_IT_ADDR_IOMMU_LO = 6, /* W/R : 32 LSB bits for IOMMU IT*/
152    IOB_IT_ADDR_IOMMU_HI = 7, /* W/R : 32 MSB bits for IOMMU IT */
153    IOB_IT_ADDRESS_BEGIN = 8, /* R/W : Peripheral IT address (2 32 bits registers) */
154};
155
156/* MWMR */
157enum SoclibMwmrRegisters
158{
159    MWMR_IOREG_MAX = 16,
160    MWMR_RESET = MWMR_IOREG_MAX,
161    MWMR_CONFIG_FIFO_WAY,
162    MWMR_CONFIG_FIFO_NO,
163    MWMR_CONFIG_STATUS_ADDR,
164    MWMR_CONFIG_DEPTH,
165    MWMR_CONFIG_BUFFER_ADDR,
166    MWMR_CONFIG_RUNNING,
167    MWMR_CONFIG_WIDTH,
168    MWMR_FIFO_FILL_STATUS,
169};
170
171enum SoclibMwmrWay
172{
173    MWMR_TO_COPROC,
174    MWMR_FROM_COPROC,
175};
176
177/* Memory Cache (TSAR) */
178enum SoclibMemCacheConfigRegs
179{
180    MEMC_LOCK,
181    MEMC_ADDR_LO,
182    MEMC_ADDR_HI,
183    MEMC_BUF_LENGTH,
184    MEMC_CMD_TYPE
185};
186
187enum SoclibMemCacheConfigCmd
188{
189    MEMC_CMD_NOP,
190    MEMC_CMD_INVAL,
191    MEMC_CMD_SYNC
192};
193
194#endif
195
196// Local Variables:
197// tab-width: 4
198// c-basic-offset: 4
199// c-file-offsets:((innamespace . 0)(inline-open . 0))
200// indent-tabs-mode: nil
201// End:
202// vim: filetype=c:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
203
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