source: soft/giet_vm/sys/irq_handler.c @ 158

Last change on this file since 158 was 158, checked in by alain, 12 years ago

Introducing the giet_vm and some example applications

File size: 7.6 KB
Line 
1///////////////////////////////////////////////////////////////////////////////////
2// File     : irq_handler.c
3// Date     : 01/04/2012
4// Author   : alain greiner and joel porquet
5// Copyright (c) UPMC-LIP6
6///////////////////////////////////////////////////////////////////////////////////
7// The irq_handler.c and irq_handler.h files are part of the GIET nano-kernel.
8// They contain the code of the _int_demux function that handle
9// the ICU (Interupt Controler Unit), and the various ISRs associated
10// to the CoCLib peripherals.
11///////////////////////////////////////////////////////////////////////////////////
12
13#include <giet_config.h>
14#include <irq_handler.h>
15#include <sys_handler.h>
16#include <drivers.h>
17#include <common.h>
18#include <ctx_handler.h>
19#include <hwr_mapping.h>
20
21///////////////////////////////////////////////////////////////////////////////////
22// Initialize the whole interrupt vector with the default ISR
23///////////////////////////////////////////////////////////////////////////////////
24
25_isr_func_t _interrupt_vector[32] = { [0 ... 31] = &_isr_default };
26
27///////////////////////////////////////////////////////////////////////////////////
28//      _int_demux()
29// This functions uses an external ICU component (Interrupt Controler Unit)
30// that concentrates up to 32 input interrupts lines. This component
31// can support up to NB_PROCS_MAX output IRQ.
32//
33// This component returns the highest priority active interrupt index (smaller
34// indexes have the highest priority) by reading the ICU_IT_VECTOR register.
35// Any value larger than 31 means "no active interrupt", and the default ISR
36// (that does nothing) is executed.
37//
38// The interrupt vector (32 ISR addresses array stored at _interrupt_vector
39// address) is initialised with the default ISR address. The actual ISR
40// addresses are supposed to be written in the interrupt vector array by the
41// boot code.
42///////////////////////////////////////////////////////////////////////////////////
43void _int_demux(void)
44{
45    int interrupt_index;
46    _isr_func_t isr;
47
48    /* retrieves the highest priority active interrupt index */
49    if (!_icu_read(ICU_IT_VECTOR, (unsigned int*)&interrupt_index))
50    {
51        /* no interrupt is active */
52        if (interrupt_index == -1)
53            return;
54
55        /* call the ISR corresponding to this index */
56        isr = _interrupt_vector[interrupt_index];
57        isr();
58    }
59}
60///////////////////////////////////////////////////////////////////////////////////
61//      _isr_default()
62// The default ISR is called when no specific ISR has been installed in the
63// interrupt vector. It simply displays a message on TTY0.
64///////////////////////////////////////////////////////////////////////////////////
65void _isr_default()
66{
67    _puts("\n\n!!! Default ISR !!!\n");
68}
69///////////////////////////////////////////////////////////////////////////////////
70//      _isr_dma()
71// This ISR acknowledges the interrupt from the dma controller, depending on
72// the proc_id. It reset the global variable _dma_busy[i] for software
73// signaling, after copying the DMA status into the _dma_status[i] variable.
74///////////////////////////////////////////////////////////////////////////////////
75void _isr_dma()
76{
77    volatile unsigned int* dma_address;
78    unsigned int proc_id;
79
80    proc_id = _procid();
81    dma_address = (unsigned int*)&seg_dma_base + (proc_id * DMA_SPAN);
82
83    _dma_status[proc_id] = dma_address[DMA_LEN]; /* save status */
84    _dma_busy[proc_id] = 0;                      /* release DMA */
85    dma_address[DMA_RESET] = 0;                  /* reset IRQ */
86}
87///////////////////////////////////////////////////////////////////////////////////
88//      _isr_ioc()
89// There is only one IOC controler shared by all tasks. It acknowledge the IRQ
90// using the ioc base address, save the status, and set the _ioc_done variable
91// to signal completion.
92///////////////////////////////////////////////////////////////////////////////////
93void _isr_ioc()
94{
95    volatile unsigned int* ioc_address;
96
97    ioc_address = (unsigned int*)&seg_ioc_base;
98
99    _ioc_status = ioc_address[BLOCK_DEVICE_STATUS]; /* save status & reset IRQ */
100    _ioc_done   = 1;                                /* signals completion */
101}
102///////////////////////////////////////////////////////////////////////////////////
103//      _isr_timer_* (* = 0,1,2,3,4,5,6,7)
104// This ISR handles up to 8 IRQs generated by 8 independant timers.
105// It acknowledges the IRQ on TIMER[*] and displays a message on TTY0
106///////////////////////////////////////////////////////////////////////////////////
107void _isr_timer_indexed(unsigned int timer_id)
108{
109    volatile unsigned int *timer_address;
110
111    timer_address = (unsigned int*)&seg_timer_base + (timer_id * TIMER_SPAN);
112
113    timer_address[TIMER_RESETIRQ] = 0; /* reset IRQ */
114
115    _puts("\n\n!!! Interrupt timer received from timer ");
116    _putw( timer_id );
117    _puts(" at cycle ");
118    _putw( _proctime() );
119    _puts("\n\n");
120}
121
122void _isr_timer_0()  { _isr_timer_indexed(0);  }
123void _isr_timer_1()  { _isr_timer_indexed(1);  }
124void _isr_timer_2()  { _isr_timer_indexed(2);  }
125void _isr_timer_3()  { _isr_timer_indexed(3);  }
126void _isr_timer_4()  { _isr_timer_indexed(4);  }
127void _isr_timer_5()  { _isr_timer_indexed(5);  }
128void _isr_timer_6()  { _isr_timer_indexed(6);  }
129void _isr_timer_7()  { _isr_timer_indexed(7);  }
130
131///////////////////////////////////////////////////////////////////////////////////
132// _isr_tty_get_* (* = 0,1,2,3,4,5,6,7,9,10,11,12,13,14,15)
133// The Giet supports up to 16 TTY terminals.
134// These 16 ISRs handle the up to 16 IRQs associated to 16 independant
135// terminals, signaling that a character is available.
136// There is one communication buffer _tty_get_buf[tty_id] per terminal.
137// The sychronisation variable _tty_get_full[tty_id], is set by the ISR,
138// and reset by the OS.
139// A character is lost if the buffer is full when the ISR is executed.
140///////////////////////////////////////////////////////////////////////////////////
141void _isr_tty_get_indexed(unsigned int tty_id)
142{
143    volatile unsigned int *tty_address;
144
145    /* compute terminal base address */
146    tty_address = (unsigned int*)&seg_tty_base + (tty_id * TTY_SPAN);
147
148    /* save character and reset IRQ */
149    _tty_get_buf[tty_id] = (unsigned char)tty_address[TTY_READ];
150
151    /* signals character available */
152    _tty_get_full[tty_id] = 1;
153}
154
155void _isr_tty_get_0()  { _isr_tty_get_indexed(0);  }
156void _isr_tty_get_1()  { _isr_tty_get_indexed(1);  }
157void _isr_tty_get_2()  { _isr_tty_get_indexed(2);  }
158void _isr_tty_get_3()  { _isr_tty_get_indexed(3);  }
159void _isr_tty_get_4()  { _isr_tty_get_indexed(4);  }
160void _isr_tty_get_5()  { _isr_tty_get_indexed(5);  }
161void _isr_tty_get_6()  { _isr_tty_get_indexed(6);  }
162void _isr_tty_get_7()  { _isr_tty_get_indexed(7);  }
163void _isr_tty_get_8()  { _isr_tty_get_indexed(8);  }
164void _isr_tty_get_9()  { _isr_tty_get_indexed(9);  }
165void _isr_tty_get_10() { _isr_tty_get_indexed(10); }
166void _isr_tty_get_11() { _isr_tty_get_indexed(11); }
167void _isr_tty_get_12() { _isr_tty_get_indexed(12); }
168void _isr_tty_get_13() { _isr_tty_get_indexed(13); }
169void _isr_tty_get_14() { _isr_tty_get_indexed(14); }
170void _isr_tty_get_15() { _isr_tty_get_indexed(15); }
171
172/////////////////////////////////////////////////////////////////////////////////////
173// _isr_switch
174// This ISR is in charge of context switch.
175// It acknowledges the IRQ on TIMER[proc_id] and calls the _ctx_switch() function.
176/////////////////////////////////////////////////////////////////////////////////////
177void _isr_switch()
178{
179    volatile unsigned int *timer_address;
180    unsigned int proc_id;
181
182    proc_id = _procid();
183    timer_address = (unsigned int*)&seg_timer_base + (proc_id * TIMER_SPAN);
184
185    timer_address[TIMER_RESETIRQ] = 0; /* reset IRQ */
186    _ctx_switch();
187}
188
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