Index: /soft/giet_vm/Makefile
===================================================================
--- /soft/giet_vm/Makefile	(revision 255)
+++ /soft/giet_vm/Makefile	(revision 256)
@@ -50,4 +50,7 @@
                  build/libs/malloc.o
 
+SORT_OBJS      = build/sort/main.o \
+                 build/libs/stdio.o \
+                 build/libs/barrier.o
 
 CFLAGS = -Wall -ffreestanding -mno-gpopt -mips32 
@@ -66,4 +69,5 @@
           build/gameoflife/gameoflife.elf \
           build/dhrystone/dhrystone.elf \
+          build/sort/sort.elf \
           
 	$(MAKE) -C memo
@@ -150,4 +154,12 @@
 	$(CC) $(INCLUDE) $(CFLAGS)  -c -o $@ $<
 
+### sort compilation
+build/sort/sort.elf: $(SORT_OBJS) sort/sort.ld
+	$(LD) -o $@ -T sort/sort.ld $(SORT_OBJS)
+	$(DU) -D $@ > $@.txt
+
+build/sort/main.o: sort/main.c
+	$(CC) $(INCLUDE) $(CFLAGS) -O3 -c -o $@ $<
+
 ### libs compilation
 build/libs/utils.o: libs/utils.c giet_config.h
Index: /soft/giet_vm/mappings/4c_2p_40_sort.xml
===================================================================
--- /soft/giet_vm/mappings/4c_2p_40_sort.xml	(revision 256)
+++ /soft/giet_vm/mappings/4c_2p_40_sort.xml	(revision 256)
@@ -0,0 +1,264 @@
+<?xml version="1.0"?>
+
+<mapping_info signature    = "0xdeadbeef" 
+              name         = "4c_1p_40_sort" 
+              cluster_x    = "2" 
+              cluster_y    = "2" 
+              vspaces      = "1"
+              increment    = "0x0010000" >
+
+*** This first section describes an instance of the "tsar_generic_xbar" architecture
+*** with 4 clusters, 2 processor per cluster and 40 bits physical address.
+
+    <clusterset>
+
+        <cluster index = "0" >
+            <pseg name = "PSEG_RAM"  type = "RAM"  base = "0x0000000000" length = "0x0010000000" />
+            <pseg name = "PSEG_XCU"  type = "PERI" base = "0x00B0000000" length = "0x0000002000" />
+            <pseg name = "PSEG_DMA"  type = "PERI" base = "0x00B1000000" length = "0x0000008000" />
+
+*** Boot ROM and non replicated peripherals
+
+            <pseg name = "PSEG_FBF"  type = "PERI" base = "0x00B2000000" length = "0x0000004000" /> 
+            <pseg name = "PSEG_IOC"  type = "PERI" base = "0x00B3000000" length = "0x0000001000" /> 
+            <pseg name = "PSEG_TTY"  type = "PERI" base = "0x00B4000000" length = "0x0000001000" /> 
+            <pseg name = "PSEG_NIC"  type = "PERI" base = "0x00B5000000" length = "0x0000021000" />
+            <pseg name = "PSEG_CMA"  type = "PERI" base = "0x00B6000000" length = "0x0000004000" />
+            <pseg name = "PSEG_IOB"  type = "PERI" base = "0x00BE000000" length = "0x0000100000" />
+            <pseg name = "PSEG_ROM"  type = "ROM"  base = "0x00BFC00000" length = "0x0000100000" />
+
+            <proc index  = "0" >
+                <irq type = "HARD" icuid = "0"  isr = "ISR_SWITCH" /> 
+                <irq type = "HARD" icuid = "8"  isr = "ISR_DMA" channel = "0" /> 
+                <irq type = "HARD" icuid = "16" isr = "ISR_TTY" channel = "0" /> 
+                <irq type = "HARD" icuid = "17" isr = "ISR_TTY" channel = "1" /> 
+                <irq type = "HARD" icuid = "18" isr = "ISR_TTY" channel = "2" /> 
+                <irq type = "HARD" icuid = "19" isr = "ISR_TTY" channel = "3" /> 
+                <irq type = "HARD" icuid = "20" isr = "ISR_TTY" channel = "4" /> 
+                <irq type = "HARD" icuid = "21" isr = "ISR_TTY" channel = "5" /> 
+                <irq type = "HARD" icuid = "22" isr = "ISR_TTY" channel = "6" /> 
+                <irq type = "HARD" icuid = "23" isr = "ISR_TTY" channel = "7" /> 
+                <irq type = "HARD" icuid = "24" isr = "ISR_TTY" channel = "8" /> 
+                <irq type = "HARD" icuid = "25" isr = "ISR_TTY" channel = "9" />
+                <irq type = "HARD" icuid = "26" isr = "ISR_TTY" channel = "10" /> 
+                <irq type = "HARD" icuid = "27" isr = "ISR_TTY" channel = "11" /> 
+                <irq type = "HARD" icuid = "28" isr = "ISR_TTY" channel = "12" /> 
+                <irq type = "HARD" icuid = "29" isr = "ISR_TTY" channel = "13" /> 
+                <irq type = "HARD" icuid = "30" isr = "ISR_TTY" channel = "14" /> 
+                <irq type = "HARD" icuid = "31" isr = "ISR_IOC" channel = "0" /> 
+            </proc> 
+            <proc index = "1" >
+                <irq type = "HARD" icuid = "1"  isr = "ISR_SWITCH" />
+            </proc>
+
+            <periph type = "DMA"  psegname = "PSEG_DMA"  channels = "4" /> 
+            <periph type = "CMA"  psegname = "PSEG_CMA"  channels = "4" /> 
+            <periph type = "XCU"  psegname = "PSEG_XCU"  channels = "1" />
+            <periph type = "IOC"  psegname = "PSEG_IOC"  channels = "1" /> 
+            <periph type = "TTY"  psegname = "PSEG_TTY"  channels = "8" /> 
+            <periph type = "NIC"  psegname = "PSEG_NIC"  channels = "2" />
+            <periph type = "FBF"  psegname = "PSEG_FBF" />
+        </cluster>
+
+        <cluster index = "1" >
+            <pseg name = "PSEG_RAM"  type = "RAM"  base = "0x4000000000" length = "0x0010000000" />
+            <pseg name = "PSEG_XCU"  type = "PERI" base = "0x40B0000000" length = "0x0000002000" />
+            <pseg name = "PSEG_DMA"  type = "PERI" base = "0x40B1000000" length = "0x0000008000" />
+
+            <proc index = "0" >
+                <irq type = "HARD" icuid = "0"  isr = "ISR_SWITCH" />
+                <irq type = "HARD" icuid = "8"  isr = "ISR_DMA" channel = "0" />
+            </proc>
+            <proc index = "1" >
+                <irq type = "HARD" icuid = "1"  isr = "ISR_SWITCH" />
+            </proc>
+
+            <periph type = "DMA"  psegname = "PSEG_DMA"  channels = "4" />
+            <periph type = "XCU"  psegname = "PSEG_XCU"  channels = "2" />
+        </cluster>
+
+        <cluster index = "2" >
+            <pseg name = "PSEG_RAM"  type = "RAM"  base = "0x8000000000" length = "0x0010000000" />
+            <pseg name = "PSEG_XCU"  type = "PERI" base = "0x80B0000000" length = "0x0000002000" />
+            <pseg name = "PSEG_DMA"  type = "PERI" base = "0x80B1000000" length = "0x0000008000" />
+
+            <proc index = "0" >
+                <irq type = "HARD" icuid = "0" isr = "ISR_SWITCH" />
+                <irq type = "HARD" icuid = "8" isr = "ISR_DMA" channel = "0" />
+            </proc>
+            <proc index = "1" >
+                <irq type = "HARD" icuid = "1"  isr = "ISR_SWITCH" />
+            </proc>
+
+            <periph type = "DMA"  psegname = "PSEG_DMA"  channels = "4" />
+            <periph type = "XCU"  psegname = "PSEG_XCU"  channels = "2" />
+        </cluster>
+
+        <cluster index = "3" >
+            <pseg name = "PSEG_RAM"  type = "RAM"  base = "0xC000000000" length = "0x0010000000" />
+            <pseg name = "PSEG_XCU"  type = "PERI" base = "0xC0B0000000" length = "0x0000002000" />
+            <pseg name = "PSEG_DMA"  type = "PERI" base = "0xC0B1000000" length = "0x0000008000" />
+
+            <proc index = "0" >
+                <irq type = "HARD" icuid = "0" isr = "ISR_SWITCH" />
+                <irq type = "HARD" icuid = "8" isr = "ISR_DMA" channel = "0" />
+            </proc>
+            <proc index = "1" >
+                <irq type = "HARD" icuid = "1"  isr = "ISR_SWITCH" />
+            </proc>
+
+            <periph  type = "DMA" psegname = "PSEG_DMA"  channels = "4" />
+            <periph  type = "XCU" psegname = "PSEG_XCU"  channels = "2" />
+        </cluster>
+    </clusterset>
+
+    <globalset> 
+
+*** segments used by the boot code / A[31:28] = 0xB / Identity mapping
+
+        <vseg name = "seg_boot_code"      vbase = "0xBFC00000" mode = "CXW_" clusterid = "0" psegname = "PSEG_ROM" ident = "1" >
+            <vobj name = "boot_code"      type = "ELF" length = "0x00008000" binpath	= "build/boot/boot.elf" />
+        </vseg>
+        <vseg name = "seg_boot_data"      vbase = "0x00000000" mode = "C_W_" clusterid = "0" psegname = "PSEG_RAM" ident = "1" >
+            <vobj name = "boot_data"      type = "ELF" length = "0x00001000" binpath	= "build/boot/boot.elf" />
+        </vseg>
+        <vseg name = "seg_boot_stack"     vbase = "0x00001000" mode = "C_W_" clusterid = "0" psegname = "PSEG_RAM" ident = "1" >
+            <vobj name = "boot_stack"     type = "BUFFER" length = "0x00003000" />
+        </vseg>
+        <vseg name = "seg_boot_mapping"   vbase = "0x00004000" mode = "C_W_" clusterid = "0" psegname = "PSEG_RAM" ident = "1" >
+            <vobj name = "boot_mapping"   type = "BLOB" length  = "0x00004000" binpath	= "map.bin" />
+        </vseg>
+
+*** Non replicated peripherals / A[31:28] = 0xB / Identity mapping
+
+        <vseg name = "seg_fbf"            vbase = "0xB2000000" mode = "C_W_" clusterid = "0" psegname = "PSEG_FBF" ident = "1" >
+            <vobj name = "fbf"            type = "PERI" length  = "0x00004000" /> 
+        </vseg>
+        <vseg name = "seg_ioc"            vbase = "0xB3000000" mode = "__W_" clusterid = "0" psegname = "PSEG_IOC" ident = "1" >
+            <vobj name = "ioc"            type = "PERI" length  = "0x00001000" /> 
+        </vseg>
+        <vseg name = "seg_tty"            vbase = "0xB4000000" mode = "__W_" clusterid = "0" psegname = "PSEG_TTY" ident = "1" >
+   			<vobj name = "tty"            type = "PERI" length  = "0x00001000" />
+        </vseg>
+        <vseg name = "seg_nic"            vbase = "0xB5000000" mode = "__W_" clusterid = "0" psegname = "PSEG_NIC" ident = "1" >
+            <vobj name = "nic"            type = "PERI" length  = "0x00021000" /> 
+        </vseg>
+
+*** segments used by the kernel / A[31:28] = 0x8 
+  
+        <vseg name = "seg_kernel_code"    vbase = "0x80000000" mode = "CX__" clusterid = "0" psegname = "PSEG_RAM" > 
+            <vobj name = "kernel_code"    type = "ELF" length = "0x00010000" binpath = "build/sys/sys.elf" />
+        </vseg>
+        <vseg name = "seg_kernel_data"    vbase = "0x80020000" mode = "C_W_" clusterid = "0" psegname = "PSEG_RAM" > 
+            <vobj name = "kernel_data"    type = "ELF" length = "0x00040000" binpath = "build/sys/sys.elf" />
+		</vseg>
+        <vseg name = "seg_kernel_uncdata" vbase = "0x80080000" mode = "__W_" clusterid = "0" psegname = "PSEG_RAM" > 
+            <vobj name = "kernel_uncdata" type = "ELF" length = "0x00010000" binpath = "build/sys/sys.elf" />
+        </vseg>
+        <vseg name = "seg_kernel_init"    vbase = "0x80090000" mode = "CX__" clusterid = "0" psegname = "PSEG_RAM" > 
+            <vobj name	= "kernel_init"   type = "ELF" length = "0x00010000" binpath	= "build/sys/sys.elf" />
+        </vseg>
+
+*** Replicated ICUS / A[31:28] = 0xE / Increment = 0x10000             
+
+        <vseg name = "seg_icu_0"          vbase = "0xE0000000" mode = "__W_" clusterid = "0" psegname = "PSEG_XCU"  > 
+            <vobj name = "icu_0"          type = "PERI" length  = "0x00001000" /> 
+        </vseg>
+        <vseg name = "seg_icu_1"          vbase = "0xE0010000" mode = "__W_" clusterid = "1" psegname = "PSEG_XCU"  > 
+            <vobj name = "icu_1"          type = "PERI" length  = "0x00001000" /> 
+        </vseg>
+        <vseg name = "seg_icu_2"          vbase = "0xE0020000" mode = "__W_" clusterid = "2" psegname = "PSEG_XCU"  > 
+            <vobj name = "icu_2"          type = "PERI" length  = "0x00001000" /> 
+        </vseg>
+        <vseg name = "seg_icu_3"          vbase = "0xE0030000" mode = "__W_" clusterid = "3" psegname = "PSEG_XCU"  > 
+            <vobj name = "icu_3"          type = "PERI" length  = "0x00001000" /> 
+        </vseg>
+
+*** Replicated DMAs / A[31:28] = 0xD / Increment = 0x10000
+
+        <vseg name = "seg_dma_0"          vbase = "0xD0000000" mode = "__W_" clusterid = "0" psegname = "PSEG_DMA" >
+            <vobj name = "dma_0"          type = "PERI" length  = "0x00008000" />
+        </vseg>
+        <vseg name = "seg_dma_1"          vbase = "0xD0010000" mode = "__W_" clusterid = "1" psegname = "PSEG_DMA" >
+            <vobj name = "dma_1"          type = "PERI" length  = "0x00008000" />
+        </vseg>
+        <vseg name = "seg_dma_2"          vbase = "0xD0020000" mode = "__W_" clusterid = "2" psegname = "PSEG_DMA" >
+            <vobj name = "dma_2"          type = "PERI" length  = "0x00008000" />
+        </vseg>
+        <vseg name = "seg_dma_3"          vbase = "0xD0030000" mode = "__W_" clusterid = "3" psegname = "PSEG_DMA" >
+            <vobj name = "dma_3"          type = "PERI" length  = "0x00008000" />
+        </vseg>
+
+*** Replicated schedulers / A[31:28] = 0xF / Increment = 0x10000
+
+        <vseg name = "seg_sched_0"        vbase = "0xF0000000" mode = "C_W_" clusterid = "0" psegname = "PSEG_RAM" >
+            <vobj name = "sched_0"        type = "SCHED" length  = "0x00008000" />
+        </vseg>
+        <vseg name = "seg_sched_1"        vbase = "0xF0010000" mode = "C_W_" clusterid = "1" psegname = "PSEG_RAM" >
+            <vobj name = "sched_1"        type = "SCHED" length  = "0x00008000" />
+        </vseg>
+        <vseg name = "seg_sched_2"        vbase = "0xF0020000" mode = "C_W_" clusterid = "2" psegname = "PSEG_RAM" >
+            <vobj name = "sched_2"        type = "SCHED" length  = "0x00008000" />
+        </vseg>
+        <vseg name = "seg_sched_3"        vbase = "0xF0030000" mode = "C_W_" clusterid = "3" psegname = "PSEG_RAM" >
+            <vobj name = "sched_3"        type = "SCHED" length  = "0x00008000" />
+        </vseg>
+***
+    </globalset> 
+
+    <vspaceset>
+        <vspace name = "sort" startname = "sort_data" > 
+            <vseg name = "seg_data"        vbase = "0x00800000" mode = "__WU" clusterid = "0" psegname = "PSEG_RAM" >
+                <vobj name = "sort_data"   type	= "ELF" length = "0x00010000" binpath = "build/sort/sort.elf" />
+            </vseg>
+            <vseg name = "seg_code"        vbase = "0x00400000" mode = "CX_U" clusterid = "0" psegname = "PSEG_RAM" > 
+                <vobj name = "sort_code"   type	= "ELF" length = "0x00010000" binpath = "build/sort/sort.elf" /> 
+            </vseg>
+            <vseg name = "seg_ptab"        vbase = "0x00300000" mode = "C___" clusterid = "0" psegname = "PSEG_RAM" > 
+                <vobj name = "ptab"        type	= "PTAB" length  = "0x00012000" align   = "13" />
+            </vseg>
+            <vseg name = "seg_stack_0"  vbase = "0x00010000" mode = "C_WU" clusterid = "0" psegname = "PSEG_RAM" >
+                <vobj name = "stack_0"  type	= "BUFFER" length = "0x00008000" /> 
+                <vobj name = "heap_0"   type	= "BUFFER" length = "0x00008000" /> 
+            </vseg>
+            <vseg name = "seg_stack_1"  vbase = "0x00020000" mode = "C_WU" clusterid = "0" psegname = "PSEG_RAM" >
+                <vobj name = "stack_1"  type	= "BUFFER" length = "0x00008000" /> 
+                <vobj name = "heap_1"   type	= "BUFFER" length = "0x00008000" /> 
+            </vseg>
+            <vseg name = "seg_stack_2"  vbase = "0x00030000" mode = "C_WU" clusterid = "1" psegname = "PSEG_RAM" >
+                <vobj name = "stack_2"  type	= "BUFFER" length = "0x00008000" /> 
+                <vobj name = "heap_2"   type	= "BUFFER" length = "0x00008000" /> 
+            </vseg>
+            <vseg name = "seg_stack_3"  vbase = "0x00040000" mode = "C_WU" clusterid = "1" psegname = "PSEG_RAM" >
+                <vobj name = "stack_3"  type	= "BUFFER" length = "0x00008000" /> 
+                <vobj name = "heap_3"   type	= "BUFFER" length = "0x00008000" /> 
+            </vseg>
+            <vseg name = "seg_stack_4"  vbase = "0x00050000" mode = "C_WU" clusterid = "2" psegname = "PSEG_RAM" >
+                <vobj name = "stack_4"  type	= "BUFFER" length = "0x00008000" /> 
+                <vobj name = "heap_4"   type	= "BUFFER" length = "0x00008000" /> 
+            </vseg>
+            <vseg name = "seg_stack_5"  vbase = "0x00060000" mode = "C_WU" clusterid = "2" psegname = "PSEG_RAM" >
+                <vobj name = "stack_5"  type	= "BUFFER" length = "0x00008000" /> 
+                <vobj name = "heap_5"   type	= "BUFFER" length = "0x00008000" /> 
+            </vseg>
+            <vseg name = "seg_stack_6"  vbase = "0x00070000" mode = "C_WU" clusterid = "3" psegname = "PSEG_RAM" >
+                <vobj name = "stack_6"  type	= "BUFFER" length = "0x00008000" /> 
+                <vobj name = "heap_6"   type	= "BUFFER" length = "0x00008000" /> 
+            </vseg>
+            <vseg name = "seg_stack_7"  vbase = "0x00080000" mode = "C_WU" clusterid = "3" psegname = "PSEG_RAM" >
+                <vobj name = "stack_7"  type	= "BUFFER" length = "0x00008000" /> 
+                <vobj name = "heap_7"   type	= "BUFFER" length = "0x00008000" /> 
+            </vseg>
+
+            <task name = "task0" clusterid = "0" proclocid = "0" stackname = "stack_0" heapname = "heap_0" startid = "0" usetty = "1" />
+            <task name = "task1" clusterid = "0" proclocid = "1" stackname = "stack_1" heapname = "heap_1" startid = "0" />
+            <task name = "task2" clusterid = "1" proclocid = "0" stackname = "stack_2" heapname = "heap_2" startid = "0" />
+            <task name = "task3" clusterid = "1" proclocid = "1" stackname = "stack_3" heapname = "heap_3" startid = "0" />
+            <task name = "task4" clusterid = "2" proclocid = "0" stackname = "stack_4" heapname = "heap_4" startid = "0" />
+            <task name = "task5" clusterid = "2" proclocid = "1" stackname = "stack_5" heapname = "heap_5" startid = "0" />
+            <task name = "task6" clusterid = "3" proclocid = "0" stackname = "stack_6" heapname = "heap_6" startid = "0" />
+            <task name = "task7" clusterid = "3" proclocid = "1" stackname = "stack_7" heapname = "heap_7" startid = "0" />
+        </vspace>
+
+    </vspaceset>
+</mapping_info>
Index: /soft/giet_vm/sort/main.c
===================================================================
--- /soft/giet_vm/sort/main.c	(revision 256)
+++ /soft/giet_vm/sort/main.c	(revision 256)
@@ -0,0 +1,242 @@
+//=================================================================================================
+// File       : main.c
+//
+// Date       : 11/2013
+//
+// Author     : Cesar Fuguet Tortolero
+//            :<cesar.fuguet-tortolero@lip6.fr>
+//
+// Description: Sort application using the GIET-VM OS.
+//              This application uses the barrier routines to apply a sort algorithm
+//              in several stages.
+//=================================================================================================
+
+#include "stdio.h"
+#include "hard_config.h"
+#include "barrier.h"
+
+#define NPROCS          8
+#define ARRAY_LENGTH    (NPROCS * 50)
+#define IPP             (ARRAY_LENGTH / NPROCS) // ITEMS PER PROCESSOR
+
+// Other processors than 0 display algorithm state 
+#define VERBOSE         1
+
+#if (VERBOSE == 1)
+#define printf(...)     giet_tty_printf(__VA_ARGS__)
+#define puts(...)       giet_tty_puts(__VA_ARGS__)
+#else
+#define printf(...)
+#define puts(...)
+#endif
+
+#define exit    giet_exit
+#define procid  giet_procid
+#define rand    giet_rand
+
+#define task0_printf(...) if(procid() == 0) giet_tty_printf(__VA_ARGS__)
+
+int array0[ARRAY_LENGTH];
+int array1[ARRAY_LENGTH];
+
+volatile int init_ok = 0;
+
+void bubbleSort(
+        int * array,
+        unsigned int length,
+        unsigned int init_pos);
+
+void merge(
+        int * array,
+        int * result,
+        int length,
+        int init_pos_a,
+        int init_pos_b,
+        int init_pos_result);
+
+// this application support at most 256 processors
+// number of barriers = log2(NPROCS)
+giet_barrier_t barrier[8];
+
+__attribute__ ((constructor)) void sort()
+{
+    int proc_id = procid();
+    int * src_array;
+    int * dst_array;
+    int i;
+
+    /**************************************************************************/
+    /* Hello World */
+
+    task0_printf("Starting SORT application\n");
+
+    /**************************************************************************/
+    /* Array Inititialitatin */
+
+    for (i = IPP * proc_id; i < IPP * (proc_id + 1); i++)
+    {
+        array0[i] = rand();
+    }
+
+    /**************************************************************************/
+    /* Barriers Inititialitatin */
+
+    while((proc_id != 0) && (init_ok == 0));
+
+    if (proc_id == 0)
+    {
+        for (i = 0; i < __builtin_ctz(NPROCS); i++)
+        {
+            printf("Initializing barrier %d with %d\n", i, NPROCS >> i);
+            barrier_init(&barrier[i], NPROCS >> i);
+        }
+
+        asm volatile ("sync");
+        init_ok = 1;
+    }
+
+    asm volatile ("sync");
+    barrier_wait(&barrier[0]);
+
+    /**************************************************************************/
+    /* Parallel sorting of array pieces */
+
+    task0_printf("Stage 0: Processor Sorting...\n\r");
+    bubbleSort(array0, IPP, IPP * proc_id);
+    task0_printf("Finishing Stage 0...\n\r");
+
+    for (i = 0; i < __builtin_ctz(NPROCS); i++)
+    {
+        asm volatile ("sync");
+        barrier_wait(&barrier[i]);
+        task0_printf("Stage %d: Starting...\n\r", i+1);
+
+        if((proc_id % (2 << i)) != 0) exit();
+
+        if((i % 2) == 0)
+        {
+            src_array = &array0[0];
+            dst_array = &array1[0];
+        }
+        else
+        {
+            src_array = &array1[0];
+            dst_array = &array0[0];
+        }
+
+        merge(src_array, dst_array
+                , IPP << i
+                , IPP * proc_id
+                , IPP * (proc_id + (1 << i))
+                , IPP * proc_id
+                );
+
+        task0_printf("Finishing Stage %d...\n\r", i + 1);
+    }
+
+    int success;
+    int failure_index;
+
+    if(proc_id == 0)
+    {
+        success = 1;
+
+        for(i=0; i<(ARRAY_LENGTH-1); i++)
+        {
+            if(dst_array[i] > dst_array[i+1])
+            {
+
+                success = 0;
+                failure_index = i;
+                break;
+            }
+        }
+
+        if (success)
+        {
+            printf("Success!!\n\r");
+        }
+        else
+        {
+            printf("Failure!! Incorrect element: %d\n\r", failure_index);
+
+
+            for(i=0; i<ARRAY_LENGTH; i++)
+            {
+                printf("array[%d] = %d\n", i, dst_array[i]);
+            }
+        }
+    }
+
+    exit();
+}
+
+void bubbleSort(
+        int * array,
+        unsigned int length,
+        unsigned int init_pos)
+{
+    int i;
+    int j;
+    int aux;
+
+    for(i = 0; i < length; i++)
+    {
+        for(j = init_pos; j < (init_pos + length - i - 1); j++)
+        {
+            if(array[j] > array[j + 1])
+            {
+                aux          = array[j + 1];
+                array[j + 1] = array[j];
+                array[j]     = aux;
+            }
+        }
+    }
+}
+
+void merge(
+        int * array,
+        int * result,
+        int length,
+        int init_pos_a,
+        int init_pos_b,
+        int init_pos_result)
+{
+    int i;
+    int j;
+    int k;
+
+    i = 0;
+    j = 0;
+    k = init_pos_result;
+
+    while((i < length) || (j < length))
+    {
+        if((i < length) && (j < length))
+        {
+            if(array[init_pos_a + i] < array[init_pos_b + j])
+            {
+                result[k++] = array[init_pos_a + i];
+                i++;
+            }
+            else
+            {
+                result[k++] = array[init_pos_b + j];
+                j++;
+            }
+        }
+        else if(i < length)
+        {
+            result[k++] = array[init_pos_a + i];
+            i++;
+        }
+        else
+        {
+            result[k++] = array[init_pos_b + j];
+            j++;
+        }
+    }
+}
+
+/* vim: tabstop=4 : shiftwidth=4 : expandtab
+*/
Index: /soft/giet_vm/sort/sort.ld
===================================================================
--- /soft/giet_vm/sort/sort.ld	(revision 256)
+++ /soft/giet_vm/sort/sort.ld	(revision 256)
@@ -0,0 +1,40 @@
+/****************************************************************************
+* Definition of the base address for all virtual segments
+*****************************************************************************/
+
+seg_data_base      = 0x00800000;
+seg_code_base      = 0x00400000;
+
+/***************************************************************************
+* Grouping sections into segments for code and data
+***************************************************************************/
+
+SECTIONS
+{
+    . = seg_code_base;
+    seg_code : 
+    {
+        *(.text)
+        *(.text.*)
+    }
+    . = seg_data_base;
+    seg_data : 
+    {
+        *(.ctors)
+        *(.rodata)
+        /* . = ALIGN(4); */
+        *(.rodata.*)
+        /* . = ALIGN(4); */
+        *(.data)
+        /* . = ALIGN(4); */
+        *(.lit8)
+        *(.lit4)
+        *(.sdata)
+        /* . = ALIGN(4); */
+        *(.bss)
+        *(COMMON)
+        *(.sbss)
+        *(.scommon)
+    }
+}
+
