Changeset 319 for soft/giet_vm/giet_python
- Timestamp:
- Jun 10, 2014, 12:30:13 PM (11 years ago)
- Location:
- soft/giet_vm/giet_python
- Files:
-
- 1 added
- 2 deleted
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
soft/giet_vm/giet_python/mapping.py
r305 r319 1 1 #!/usr/bin/env python 2 2 3 ####################################################################################### 3 import sys 4 5 ########################################################################################## 4 6 # file : giet_mapping.py 5 7 # date : april 2014 6 8 # author : Alain Greiner 7 ####################################################################################### 8 # This file contains the classes required to define a generic mapping in python 9 # for the GIET_VM. 10 # - A 'Mapping' contains + various structural constants, 11 # + a 'Cluster' set, (hardware architecture) 12 # + a 'Vseg' set, (kernel virtual segments mapping) 13 # + a 'Vspace' set (several user applications). 14 # - A 'Cluster' contains + coordinates (x,y), 15 # + a 'Pseg' set, (all physical segments in cluster) 16 # + a 'Proc' set, (processors in cluster) 17 # + a 'Peripheral' set (peripherals in cluster) 18 # - A 'Vspace' contains + a 'Vseg' set, (user virtual segments mapping) 19 # + a 'Task' set (user tasks mapping) 20 #################################################################################### 21 22 ######################### 9 ########################################################################################## 10 # This file contains the classes required to define a mapping for the GIET_VM. 11 # - A 'Mapping' contains a set of 'Cluster' (hardware architecture) 12 # a set of 'Vseg' (kernel virtual segments mapping) 13 # a set of 'Vspace' (several user applications). 14 # - A 'Cluster' contains a set of 'Pseg' (all physical segments in cluster) 15 # a set of 'Proc' (processors in cluster) 16 # a set of 'Periph' (peripherals in cluster) 17 # a set of 'Coproc' (coprocessors in cluster) 18 # - A 'Vspace' contains a set of 'Vseg' (user virtual segments mapping) 19 # a set of 'Task' (user tasks mapping) 20 # - A 'Vseg' contains a set of 'Vobj' 21 # - A 'Periph' contains a set of 'Irq' (only for XCU, ICU and PIC types ) 22 # - A 'Coproc' contains a set of 'Cpports' (one port per MWMR channel) 23 ########################################################################################## 24 # Implementation Note 25 # As described above, the various objects are distributed in the PYTHON structure: 26 # For example the psegs set is split in several subsets (one subset per cluster), 27 # or the tasks set is split in several subsets (one subset per vspace), etc... 28 # In the C binary data structure used by the giet_vm, all objects of same type 29 # are stored in a linear array (one single array for all psegs for example). 30 # For all objects, we compute and store in the PYTHON object itsel a "global index" 31 # corresponding to the index in this global array, and this index can be used as 32 # a pseudo-pointer to identify a specific object of a given type. 33 ########################################################################################## 34 35 ###################################################################################### 36 # These global lists must be consistent with enums in mapping_info.h or irq_handler.h 37 ###################################################################################### 38 PERIPHTYPES = [ 39 'CMA', 40 'DMA', 41 'FBF', 42 'ICU', 43 'IOB', 44 'IOC', 45 'MMC', 46 'MWR', 47 'NIC', 48 'ROM', 49 'SIM', 50 'TIM', 51 'TTY', 52 'XCU', 53 'PIC', 54 ] 55 56 PERIPHSUBTYPES = [ 57 'BDV', 58 'HBA', 59 'SPI', 60 'NONE', 61 ] 62 63 IRQTYPES = [ 64 'HWI', 65 'WTI', 66 'PTI', 67 ] 68 69 ISRTYPES = [ 70 'ISR_DEFAULT', 71 'ISR_TICK', 72 'ISR_TTY_RX', 73 'ISR_TTY_TX', 74 'ISR_BDV', 75 'ISR_TIMER', 76 'ISR_WAKUP', 77 'ISR_NIC_RX', 78 'ISR_NIC_TX', 79 'ISR_CMA', 80 'ISR_MMC', 81 'ISR_DMA', 82 'ISR_SPI', 83 ] 84 85 VOBJTYPES = [ 86 'ELF', 87 'BLOB', 88 'PTAB', 89 'PERI', 90 'MWMR', 91 'LOCK', 92 'BUFFER', 93 'BARRIER', 94 'CONST', 95 'MEMSPACE', 96 'SCHED', 97 ] 98 99 VSEGMODES = [ 100 '____', 101 '___U', 102 '__W_', 103 '__WU', 104 '_X__', 105 '_X_U', 106 '_XW_', 107 '_XWU', 108 'C___', 109 'C__U', 110 'C_W_', 111 'C_WU', 112 'CX__', 113 'CX_U', 114 'CXW_', 115 'CXWU', 116 ] 117 118 PSEGTYPES = [ 119 'RAM', 120 'ROM', # deprecated => use PERI 121 'PERI', 122 ] 123 124 CP_PORT_DIRS = [ 125 'TO_COPROC', 126 'FROM_COPROC', 127 ] 128 129 ########################################################################################## 23 130 class Mapping( object ): 24 ######################### 131 ########################################################################################## 25 132 def __init__( self, 26 name, # mapping name 27 x_size, # number of clusters in a row 28 y_size, # number of clusters in a column 29 nb_procs, # max number of processors per cluster 30 x_width = 4, # number of bits encoding x coordinate 31 y_width = 4, # number of bits encoding y coordinate 32 paddr_width = 32, # number of bits for physical address 33 coherence = False, # hardware cache coherence 34 irq_per_proc = 1, # number or IRQ lines from XCU to processor 35 use_ram_disk = False, # architecture contains ram_disk when true 36 x_io = 0, # cluster_io x coordinate 37 y_io = 0 ): # cluster_io y coordinate 38 39 self.name = name 40 self.paddr_width = paddr_width 41 self.coherence = coherence 42 self.x_size = x_size 43 self.y_size = y_size 44 self.x_width = x_width 45 self.y_width = y_width 46 self.irq_per_proc = irq_per_proc 47 self.nb_procs = nb_procs 48 self.use_ram_disk = use_ram_disk 49 self.x_io = x_io 50 self.y_io = y_io 51 52 self.total_procs = 0 53 self.total_globs = 0 54 55 # clusters array 56 self.clusters = [] 57 for x in xrange (1<<x_width): 58 for y in xrange (1<<y_width): 59 self.clusters.append( Cluster(x,y) ) 60 61 # globals array 62 self.globs = [] 63 64 # vspace array 65 self.vspaces = [] 133 name, # mapping name 134 x_size, # number of clusters in a row 135 y_size, # number of clusters in a column 136 procs_max, # max number of processors per cluster 137 x_width = 4, # number of bits encoding x coordinate 138 y_width = 4, # number of bits encoding y coordinate 139 paddr_width = 40, # number of bits for physical address 140 coherence = 1, # hardware cache coherence when non-zero 141 irq_per_proc = 1, # number or IRQs from XCU to processor 142 use_ramdisk = False, # use ramdisk when true 143 x_io = 0, # cluster_io x coordinate 144 y_io = 0, # cluster_io y coordinate 145 reset_address = 0xBFC00000 ): # Processor wired boot_address 146 147 self.signature = 0xDACE2014 148 self.name = name 149 self.paddr_width = paddr_width 150 self.coherence = coherence 151 self.x_size = x_size 152 self.y_size = y_size 153 self.x_width = x_width 154 self.y_width = y_width 155 self.irq_per_proc = irq_per_proc 156 self.procs_max = procs_max 157 self.use_ramdisk = use_ramdisk 158 self.x_io = x_io 159 self.y_io = y_io 160 self.reset_address = reset_address 161 162 self.vseg_increment = 0x10000 163 164 self.total_vspaces = 0 165 self.total_globals = 0 166 self.total_psegs = 0 167 self.total_vsegs = 0 168 self.total_vobjs = 0 169 self.total_tasks = 0 170 self.total_procs = 0 171 self.total_irqs = 0 172 self.total_coprocs = 0 173 self.total_cpports = 0 174 self.total_periphs = 0 175 176 self.clusters = [] 177 self.globs = [] 178 self.vspaces = [] 179 180 for x in xrange( self.x_size ): 181 for y in xrange( self.y_size ): 182 cluster = Cluster( x , y ) 183 cluster.index = (x * self.y_size) + y 184 self.clusters.append( cluster ) 66 185 67 186 return 68 187 69 ########################## 70 def addPseg( self, pseg ): 71 cluster_xy = pseg.base >> (self.paddr_width - self.x_width - self.y_width) 188 ########################## add a ram pseg in a cluster 189 def addRam( self, 190 name, # pseg name 191 base, # pseg base address 192 size ): # pseg length (bytes) 193 194 # check coordinates (obtained from the base address) 195 cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width) 72 196 x = cluster_xy >> (self.y_width); 73 197 y = cluster_xy & ((1 << self.y_width) - 1) 74 if (x >= self.x_size) or (y >= self.y_size): 75 print '(x,y) coordinates too large for pdeg %s' % str(pseg) 76 self.clusters[cluster_xy].psegs.append( pseg ) 77 return 78 79 ###################################### 80 def addPeripheral( self, peripheral ): 81 cluster_xy = peripheral.pseg.base >> (self.paddr_width - self.x_width - self.y_width) 198 199 assert (base & 0xFFF) == 0 200 201 assert (x < self.x_size) and (y < self.y_size) 202 203 cluster_id = (x * self.y_size) + y 204 205 # add one pseg in the mapping 206 pseg = Pseg( name, base, size, x, y, 'RAM' ) 207 self.clusters[cluster_id].psegs.append( pseg ) 208 pseg.index = self.total_psegs 209 self.total_psegs += 1 210 211 return pseg 212 213 ############################## add a peripheral and the associated pseg in a cluster 214 def addPeriph( self, 215 name, # associated pseg name 216 base, # associated pseg base address 217 size, # associated pseg length (bytes) 218 ptype, # peripheral type 219 subtype = 'NONE', # peripheral subtype 220 channels = 1, # number of channels 221 arg = 0 ): # optional argument (semantic depends on ptype) 222 223 # check cluster coordinates (obtained from the base address) 224 cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width) 82 225 x = cluster_xy >> (self.y_width); 83 226 y = cluster_xy & ((1 << self.y_width) - 1) 84 if (x >= self.x_size) or (y >= self.y_size): 85 print '(x,y) coordinates too large for pdeg %s' % str(pseg) 86 self.clusters[cluster_xy].peripherals.append( peripheral ) 227 228 assert (x < self.x_size) and (y < self.y_size) 229 230 assert (base & 0xFFF) == 0 231 232 assert ptype in PERIPHTYPES 233 234 assert subtype in PERIPHSUBTYPES 235 236 cluster_id = (x * self.y_size) + y 237 238 # add one pseg into mapping 239 pseg = Pseg( name, base, size, x, y, 'PERI' ) 240 self.clusters[cluster_id].psegs.append( pseg ) 241 pseg.index = self.total_psegs 242 self.total_psegs += 1 243 244 # add one periph into mapping 245 periph = Periph( pseg, ptype, subtype, channels, arg ) 246 self.clusters[cluster_id].periphs.append( periph ) 247 periph.index = self.total_periphs 248 self.total_periphs += 1 249 250 return periph 251 252 ################################ add an IRQ in a peripheral 253 def addIrq( self, 254 periph, # peripheral containing IRQ (PIC or XCU) 255 index, # peripheral input port index 256 isrtype, # ISR type 257 channel = 0 ): # channel for multi-channels ISR 258 259 assert isrtype in ISRTYPES 260 261 assert index < 32 262 263 # add one irq into mapping 264 irq = Irq( 'HWI', index , isrtype, channel ) 265 periph.irqs.append( irq ) 266 irq.index = self.total_irqs 267 self.total_irqs += 1 268 269 return irq 270 271 ########################## add a processor in a cluster 272 def addProc( self, 273 x, # cluster x coordinate 274 y, # cluster y coordinate 275 p ): # processor local index 276 277 assert (x < self.x_size) and (y < self.y_size) 278 279 cluster_id = (x * self.y_size) + y 280 281 # add one proc into mapping 282 proc = Processor( x, y, p ) 283 self.clusters[cluster_id].procs.append( proc ) 284 proc.index = self.total_procs 285 self.total_procs += 1 286 287 return proc 288 289 ############################## add a coprocessor in a cluster 290 def addCoproc( self, 291 name, # associated pseg name 292 base, # associated pseg base address 293 size ): # associated pseg length 294 295 # check cluster coordinates (obtained from the base address) 296 cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width) 297 x = cluster_xy >> (self.y_width); 298 y = cluster_xy & ((1 << self.y_width) - 1) 299 300 assert (x < self.x_size) and (y < self.y_size) 301 302 cluster_id = (x * self.y_size) + y 303 304 # add one pseg into mapping 305 pseg = Pseg( name, base, size, x, y, 'PERI' ) 306 self.clusters[cluster_id].psegs.append( pseg ) 307 pseg.index = self.total_psegs 308 self.total_psegs += 1 309 310 # add one coproc into mapping 311 periph = Coproc( pseg ) 312 self.clusters[cluster_id].coprocs.append( coproc ) 313 periph.index = self.total_coprocs 314 self.total_coprocs += 1 315 316 return coproc 317 318 ################################## add a port in a coprocessor 319 def addPort( self, 320 coproc, # coprocessor containing the port 321 direction, # direction (TO_COPROC / FROM_COPROC) 322 vspacename, # name of vspace using the coproc 323 mwmrname ): # name of the vobj defining the MWMR channel 324 325 assert direction in CP_PORT_DIRS 326 327 # add one cpport into mapping 328 port = Cpport( direction, vspacename, mwmrname ) 329 coproc.ports.append( port ) 330 port.index = self.total_cpports 331 self.total_cpports += 1 332 333 return port 334 335 ############################ add one (or several) global vseg into mapping 336 def addGlobal( self, 337 name, # vseg name 338 vbase, # virtual base address 339 size, # vobj length (bytes) 340 mode, # CXWU flags 341 vtype, # vobj type 342 x, # destination x coordinate 343 y, # destination y coordinate 344 pseg, # destination pseg name 345 identity = False, # identity mapping required if true 346 replicated = False, # replicated in all clusters if true 347 binpath = '' ): # pathname for binary code 348 349 assert (identity and replicated) == False 350 351 assert mode in VSEGMODES 352 353 assert vtype in VOBJTYPES 354 355 assert (vbase & 0xFFF) == 0 356 357 assert (x < self.x_size) and (y < self.y_size) 358 359 if ( replicated ): # replicated 360 for x_rep in xrange( self.x_size ): 361 for y_rep in xrange( self.y_size ): 362 vbase_rep = vbase + (((x_rep << self.y_width) + y_rep) << 16) 363 name_rep = name + '_%d_%d' % ( x_rep , y_rep ) 364 365 # add one vseg [x,y] into mapping 366 vseg = Vseg( name_rep, vbase_rep, mode, x_rep, y_rep, pseg, identity ) 367 self.globs.append( vseg ) 368 self.total_globals += 1 369 vseg.index = self.total_vsegs 370 self.total_vsegs += 1 371 372 # add one vobj [x,y] in the mapping 373 vobj = Vobj( name_rep, size, vtype, binpath, 0, 0 ) 374 vseg.vobjs.append( vobj ) 375 vobj.index = self.total_vobjs 376 self.total_vobjs += 1 377 378 else: # single vseg 379 # add one vseg into mapping 380 vseg = Vseg( name, vbase, mode, x, y, pseg, identity ) 381 self.globs.append( vseg ) 382 self.total_globals += 1 383 vseg.index = self.total_vsegs 384 self.total_vsegs += 1 385 386 # add one vobj into mapping 387 vobj = Vobj( name, size, vtype, binpath, 0, 0 ) 388 vseg.vobjs.append( vobj ) 389 vobj.index = self.total_vobjs 390 self.total_vobjs += 1 391 87 392 return 88 393 89 ########################### 90 def addProc ( self, proc ): 91 cluster_xy = (proc.x << self.y_width) + proc.y 92 self.clusters[cluster_xy].procs.append( proc ) 93 self.total_procs += 1 94 if (proc.x >= self.x_size) or (proc.y >= self.y_size): 95 print '(x,y) coordinates too large for node %s' % str(proc) 96 return 97 98 ############################ 99 def addGlobal( self, vseg ): 100 self.globs.append( vseg ) 101 return 102 103 ############################## 104 def addVspace( self, vspace ): 394 ################################ add a vspace into mapping 395 def addVspace( self, 396 name, # vspace name 397 startname ): # name of vobj containing start_vector 398 399 # add one vspace into mapping 400 vspace = Vspace( name, startname ) 105 401 self.vspaces.append( vspace ) 106 return 402 vspace.index = self.total_vspaces 403 self.total_vspaces += 1 404 405 return vspace 107 406 108 #################### 109 def __str__( self ): # xml generation for mapping 407 ################################# add a private vseg and a vobj in a vspace 408 def addVseg( self, 409 vspace, # vspace containing the vseg 410 name, # vseg name 411 vbase, # virtual base address 412 size, # vobj length (bytes) 413 mode, # CXWU flags 414 vtype, # vobj type 415 x, # destination x coordinate 416 y, # destination y coordinate 417 pseg, # destination pseg name 418 binpath = '', # pathname for binary code 419 align = 0, # alignment required 420 init = 0 ): # initial value 421 422 assert mode in VSEGMODES 423 424 assert vtype in VOBJTYPES 425 426 assert (x < self.x_size) and (y < self.y_size) 427 428 # add one vseg into mapping 429 vseg = Vseg( name, vbase, mode, x, y, pseg ) 430 vspace.vsegs.append( vseg ) 431 vseg.index = self.total_vsegs 432 self.total_vsegs += 1 433 434 # add one vobj into mapping 435 vobj = Vobj( name, size, vtype, binpath, align, init ) 436 vseg.vobjs.append( vobj ) 437 vobj.index = self.total_vobjs 438 self.total_vobjs += 1 439 440 return vseg 441 442 ################################ add a vobj in a private vseg 443 def addVobj( self, 444 vseg, # vseg containing vobj 445 name, # vobj name 446 size, # vobj length (bytes) 447 vtype, # vobj type 448 binpath = '', # pathname to binary 449 align = 0, # alignment constraint 450 init = 0 ): # initial value 451 452 assert vtype in VOBJTYPES 453 454 # add one vobj into mapping 455 vobj = Vobj( name, size, vtype, binpath, align, init ) 456 vseg.vobjs.append( vobj ) 457 vobj.index = self.total_vobjs 458 self.total_vobjs += 1 459 460 return vobj 461 462 ################################ add a task in a vspace 463 def addTask( self, 464 vspace, # vspace containing task 465 name, # task name 466 trdid, # task index in vspace 467 x, # destination x coordinate 468 y, # destination y coordinate 469 lpid, # destination processor local index 470 stackname, # name of vobj containing stack 471 heapname, # name of vobj containing heap 472 startid, # index in start_vector 473 usetty = False, # request a private TTY channel 474 usenic = False, # request a private NIC channel 475 usecma = False, # request a private CMA channel 476 usehba = False, # request a private HBA channel 477 usetim = False ): # request a private TIM channel 478 479 assert (x < self.x_size) and (y < self.y_size) 480 481 assert lpid < self.procs_max 482 483 # add one task into mapping 484 task = Task( name, trdid, x, y, lpid, stackname, heapname, startid, 485 usetty, usenic, usecma, usehba, usetim ) 486 vspace.tasks.append( task ) 487 task.index = self.total_tasks 488 self.total_tasks += 1 489 490 return task 491 492 ################################# 493 def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array 494 495 byte_stream = bytearray() 496 length = len( s ) 497 if length < (nbytes - 1): 498 for b in s: 499 byte_stream.append( b ) 500 for x in xrange(nbytes-length): 501 byte_stream.append( '\0' ) 502 else: 503 print 'error in str2bytes() string %s too long' % s 504 sys.exit(1) 505 506 return byte_stream 507 508 ################################### 509 def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array 510 511 byte_stream = bytearray() 512 for n in xrange( nbytes ): 513 byte_stream.append( (val >> (n<<3)) & 0xFF ) 514 515 return byte_stream 516 517 ################ 518 def xml( self ): # xml file generation for mapping 519 110 520 s = '<?xml version="1.0"?>\n\n' 111 s += '<mapping_info signature = "0x DACE2014"\n'521 s += '<mapping_info signature = "0x%x"\n' % (self.signature) 112 522 s += ' name = "%s"\n' % (self.name) 113 523 s += ' x_size = "%d"\n' % (self.x_size) … … 116 526 s += ' y_width = "%d"\n' % (self.y_width) 117 527 s += ' irq_per_proc = "%d"\n' % (self.irq_per_proc) 118 s += ' use_ram _disk = "%d"\n' % (self.use_ram_disk)528 s += ' use_ramdisk = "%d"\n' % (self.use_ramdisk) 119 529 s += ' x_io = "%d"\n' % (self.x_io) 120 530 s += ' y_io = "%d" >\n' % (self.y_io) 531 s += '\n' 532 121 533 s += ' <clusterset>\n' 122 534 for x in xrange ( self.x_size ): 123 535 for y in xrange ( self.y_size ): 124 cluster_ xy = (x << self.y_width) + y125 s += s tr( self.clusters[cluster_xy])536 cluster_id = (x * self.y_size) + y 537 s += self.clusters[cluster_id].xml() 126 538 s += ' </clusterset>\n' 539 s += '\n' 540 127 541 s += ' <globalset>\n' 128 for vseg in self.globs: 129 s += str ( vseg ) 542 for vseg in self.globs: s += vseg.xml() 130 543 s += ' </globalset>\n' 544 s += '\n' 545 131 546 s += ' <vspaceset>\n' 132 for vspace in self.vspaces: 133 s += str( vspace ) 547 for vspace in self.vspaces: s += vspace.xml() 134 548 s += ' </vspaceset>\n' 549 135 550 s += '</mapping_info>\n' 136 551 return s 137 138 ####################### 552 553 ######################### 554 def cbin( self, verbose ): # C binary structure generation for mapping 555 556 byte_stream = bytearray() 557 558 # header 559 byte_stream += self.int2bytes(4, self.signature) 560 byte_stream += self.int2bytes(4, self.x_size) 561 byte_stream += self.int2bytes(4, self.y_size) 562 byte_stream += self.int2bytes(4, self.x_width) 563 byte_stream += self.int2bytes(4, self.y_width) 564 byte_stream += self.int2bytes(4, self.x_io) 565 byte_stream += self.int2bytes(4, self.y_io) 566 byte_stream += self.int2bytes(4, self.irq_per_proc) 567 byte_stream += self.int2bytes(4, self.use_ramdisk) 568 byte_stream += self.int2bytes(4, self.total_globals) 569 byte_stream += self.int2bytes(4, self.total_vspaces) 570 byte_stream += self.int2bytes(4, self.total_psegs) 571 byte_stream += self.int2bytes(4, self.total_vsegs) 572 byte_stream += self.int2bytes(4, self.total_vobjs) 573 byte_stream += self.int2bytes(4, self.total_tasks) 574 byte_stream += self.int2bytes(4, self.total_procs) 575 byte_stream += self.int2bytes(4, self.total_irqs) 576 byte_stream += self.int2bytes(4, self.total_coprocs) 577 byte_stream += self.int2bytes(4, self.total_cpports) 578 byte_stream += self.int2bytes(4, self.total_periphs) 579 byte_stream += self.str2bytes(32, self.name) 580 581 if ( verbose ): 582 print '\n' 583 print 'name = %s' % self.name 584 print 'signature = %x' % self.signature 585 print 'x_size = %d' % self.x_size 586 print 'y_size = %d' % self.y_size 587 print 'x_width = %d' % self.x_width 588 print 'y_width = %d' % self.y_width 589 print 'x_io = %d' % self.x_io 590 print 'y_io = %d' % self.y_io 591 print 'irq_per_proc = %d' % self.irq_per_proc 592 print 'use_ramdisk = %d' % self.use_ramdisk 593 print 'total_globals = %d' % self.total_globals 594 print 'total_psegs = %d' % self.total_psegs 595 print 'total_vsegs = %d' % self.total_vsegs 596 print 'total_vobjs = %d' % self.total_vobjs 597 print 'total_tasks = %d' % self.total_tasks 598 print 'total_procs = %d' % self.total_procs 599 print 'total_irqs = %d' % self.total_irqs 600 print 'total_coprocs = %d' % self.total_coprocs 601 print 'total_cpports = %d' % self.total_cpports 602 print 'total_periphs = %d' % self.total_periphs 603 print '\n' 604 605 # clusters array 606 index = 0 607 for cluster in self.clusters: 608 byte_stream += cluster.cbin( self, verbose, index ) 609 index += 1 610 611 if ( verbose ): print '\n' 612 613 # psegs array 614 index = 0 615 for cluster in self.clusters: 616 for pseg in cluster.psegs: 617 byte_stream += pseg.cbin( self, verbose, index, cluster ) 618 index += 1 619 620 if ( verbose ): print '\n' 621 622 # vspaces array 623 index = 0 624 for vspace in self.vspaces: 625 byte_stream += vspace.cbin( self, verbose, index ) 626 index += 1 627 628 if ( verbose ): print '\n' 629 630 # vsegs array 631 index = 0 632 for vseg in self.globs: 633 byte_stream += vseg.cbin( self, verbose, index ) 634 index += 1 635 for vspace in self.vspaces: 636 for vseg in vspace.vsegs: 637 byte_stream += vseg.cbin( self, verbose, index ) 638 index += 1 639 640 if ( verbose ): print '\n' 641 642 # vobjs array 643 index = 0 644 for vseg in self.globs: 645 for vobj in vseg.vobjs: 646 byte_stream += vobj.cbin( self, verbose, index ) 647 index += 1 648 for vspace in self.vspaces: 649 for vseg in vspace.vsegs: 650 for vobj in vseg.vobjs: 651 byte_stream += vobj.cbin( self, verbose, index ) 652 index += 1 653 654 if ( verbose ): print '\n' 655 656 # tasks array 657 index = 0 658 for vspace in self.vspaces: 659 for task in vspace.tasks: 660 byte_stream += task.cbin( self, verbose, index, vspace ) 661 index += 1 662 663 if ( verbose ): print '\n' 664 665 # procs array 666 index = 0 667 for cluster in self.clusters: 668 for proc in cluster.procs: 669 byte_stream += proc.cbin( self, verbose, index ) 670 index += 1 671 672 if ( verbose ): print '\n' 673 674 # irqs array 675 index = 0 676 for cluster in self.clusters: 677 for periph in cluster.periphs: 678 for irq in periph.irqs: 679 byte_stream += irq.cbin( self, verbose, index ) 680 index += 1 681 682 if ( verbose ): print '\n' 683 684 # coprocs array 685 index = 0 686 for cluster in self.clusters: 687 for coproc in cluster.coprocs: 688 byte_stream += coproc.cbin( self, verbose, index ) 689 index += 1 690 691 if ( verbose ): print '\n' 692 693 # cpports array 694 index = 0 695 for cluster in self.clusters: 696 for coproc in cluster.coprocs: 697 for port in coproc.ports: 698 byte_stream += port.cbin( self, verbose, index ) 699 index += 1 700 701 if ( verbose ): print '\n' 702 703 # periphs array 704 index = 0 705 for cluster in self.clusters: 706 for periph in cluster.periphs: 707 byte_stream += periph.cbin( self, verbose, index ) 708 index += 1 709 710 return byte_stream 711 # end of cbin() 712 713 ####################### 714 def giet_vsegs( self ): # compute string for giet_vsegs.ld file 715 # required by giet_vm compilation 716 717 # search the vsegs required for the giet_vsegs.ld 718 boot_code_found = False 719 boot_data_found = False 720 kernel_uncdata_found = False 721 kernel_data_found = False 722 kernel_code_found = False 723 kernel_init_found = False 724 for vseg in self.globs: 725 if ( vseg.name == 'seg_boot_code' ): 726 boot_code_vbase = vseg.vbase 727 boot_code_size = vseg.vobjs[0].length 728 boot_code_found = True 729 730 if ( vseg.name == 'seg_boot_data' ): 731 boot_data_vbase = vseg.vbase 732 boot_data_size = vseg.vobjs[0].length 733 boot_data_found = True 734 735 if ( vseg.name == 'seg_kernel_uncdata' ): 736 kernel_uncdata_vbase = vseg.vbase 737 kernel_uncdata_size = vseg.vobjs[0].length 738 kernel_uncdata_found = True 739 740 if ( vseg.name == 'seg_kernel_data' ): 741 kernel_data_vbase = vseg.vbase 742 kernel_data_size = vseg.vobjs[0].length 743 kernel_data_found = True 744 745 if ( vseg.name == 'seg_kernel_code' ): 746 kernel_code_vbase = vseg.vbase 747 kernel_code_size = vseg.vobjs[0].length 748 kernel_code_found = True 749 750 if ( vseg.name == 'seg_kernel_init' ): 751 kernel_init_vbase = vseg.vbase 752 kernel_init_size = vseg.vobjs[0].length 753 kernel_init_found = True 754 755 # check if all required vsegs have been found 756 if ( boot_code_found == False ): 757 print 'error in giet_vsegs() : seg_boot_code vseg missing' 758 sys.exit() 759 760 if ( boot_data_found == False ): 761 print 'error in giet_vsegs() : seg_boot_data vseg missing' 762 sys.exit() 763 764 if ( kernel_data_found == False ): 765 print 'error in giet_vsegs() : seg_kernel_data vseg missing' 766 sys.exit() 767 768 if ( kernel_uncdata_found == False ): 769 print 'error in giet_vsegs() : seg_kernel_uncdata vseg missing' 770 sys.exit() 771 772 if ( kernel_code_found == False ): 773 print 'error in giet_vsegs() : seg_kernel_data vseg missing' 774 sys.exit() 775 776 if ( kernel_init_found == False ): 777 print 'error in giet_vsegs() : seg_kernel_init vseg missing' 778 sys.exit() 779 780 # build string 781 s = '/* Generated by tsarmap for %s */\n' % self.name 782 s += '\n' 783 784 s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase 785 s += 'boot_code_size = 0x%x;\n' % boot_code_size 786 s += '\n' 787 s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase 788 s += 'boot_data_size = 0x%x;\n' % boot_data_size 789 s += '\n' 790 s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase 791 s += 'kernel_code_size = 0x%x;\n' % kernel_code_size 792 s += '\n' 793 s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase 794 s += 'kernel_data_size = 0x%x;\n' % kernel_data_size 795 s += '\n' 796 s += 'kernel_uncdata_vbase = 0x%x;\n' % kernel_uncdata_vbase 797 s += 'kernel_uncdata_size = 0x%x;\n' % kernel_uncdata_size 798 s += '\n' 799 s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase 800 s += 'kernel_init_size = 0x%x;\n' % kernel_init_size 801 s += '\n' 802 803 return s 804 805 ######################## 806 def hard_config( self ): # compute string for hard_config.h file required by 807 # - top.cpp compilation 808 # - giet_vm compilation 809 # - tsar_preloader compilation 810 811 nb_total_procs = 0 812 813 # for each peripheral type, define default values 814 # for pbase address, size, number of components, and channels 815 nb_cma = 0 816 cma_channels = 0 817 seg_cma_base = 0xFFFFFFFF 818 seg_cma_size = 0 819 820 nb_dma = 0 821 dma_channels = 0 822 seg_dma_base = 0xFFFFFFFF 823 seg_dma_size = 0 824 825 nb_fbf = 0 826 fbf_channels = 0 827 seg_fbf_base = 0xFFFFFFFF 828 seg_fbf_size = 0 829 830 nb_icu = 0 831 icu_channels = 0 832 seg_icu_base = 0xFFFFFFFF 833 seg_icu_size = 0 834 835 nb_iob = 0 836 iob_channels = 0 837 seg_iob_base = 0xFFFFFFFF 838 seg_iob_size = 0 839 840 nb_ioc = 0 841 ioc_channels = 0 842 seg_ioc_base = 0xFFFFFFFF 843 seg_ioc_size = 0 844 845 nb_mmc = 0 846 mmc_channels = 0 847 seg_mmc_base = 0xFFFFFFFF 848 seg_mmc_size = 0 849 850 nb_mwr = 0 851 mwr_channels = 0 852 seg_mwr_base = 0xFFFFFFFF 853 seg_mwr_size = 0 854 855 nb_nic = 0 856 nic_channels = 0 857 seg_nic_base = 0xFFFFFFFF 858 seg_nic_size = 0 859 860 nb_pic = 0 861 pic_channels = 0 862 seg_pic_base = 0xFFFFFFFF 863 seg_pic_size = 0 864 865 nb_rom = 0 866 rom_channels = 0 867 seg_rom_base = 0xFFFFFFFF 868 seg_rom_size = 0 869 870 nb_sim = 0 871 sim_channels = 0 872 seg_sim_base = 0xFFFFFFFF 873 seg_sim_size = 0 874 875 nb_tim = 0 876 tim_channels = 0 877 seg_tim_base = 0xFFFFFFFF 878 seg_tim_size = 0 879 880 nb_tty = 0 881 tty_channels = 0 882 seg_tty_base = 0xFFFFFFFF 883 seg_tty_size = 0 884 885 nb_xcu = 0 886 xcu_channels = 0 887 seg_xcu_base = 0xFFFFFFFF 888 seg_xcu_size = 0 889 890 use_bdv = False 891 use_spi = False 892 use_hba = False 893 894 # get peripherals attributes 895 for cluster in self.clusters: 896 for periph in cluster.periphs: 897 if ( periph.ptype == 'CMA' ): 898 seg_cma_base = periph.pseg.base & 0xFFFFFFFF 899 seg_cma_size = periph.pseg.size 900 cma_channels = periph.channels 901 nb_cma +=1 902 903 elif ( periph.ptype == 'DMA' ): 904 seg_dma_base = periph.pseg.base & 0xFFFFFFFF 905 seg_dma_size = periph.pseg.size 906 dma_channels = periph.channels 907 nb_dma +=1 908 909 elif ( periph.ptype == 'FBF' ): 910 seg_fbf_base = periph.pseg.base & 0xFFFFFFFF 911 seg_fbf_size = periph.pseg.size 912 fbf_channels = periph.channels 913 nb_fbf +=1 914 915 elif ( periph.ptype == 'ICU' ): 916 seg_icu_base = periph.pseg.base & 0xFFFFFFFF 917 seg_icu_size = periph.pseg.size 918 icu_channels = periph.channels 919 nb_icu +=1 920 921 elif ( periph.ptype == 'IOB' ): 922 seg_iob_base = periph.pseg.base & 0xFFFFFFFF 923 seg_iob_size = periph.pseg.size 924 iob_channels = periph.channels 925 nb_iob +=1 926 927 elif ( periph.ptype == 'IOC' ): 928 seg_ioc_base = periph.pseg.base & 0xFFFFFFFF 929 seg_ioc_size = periph.pseg.size 930 ioc_channels = periph.channels 931 nb_ioc += 1 932 if ( periph.subtype == 'BDV' ): use_bdv = True 933 elif ( periph.subtype == 'HBA' ): use_hba = True 934 elif ( periph.subtype == 'SPI' ): use_spi = True 935 936 elif ( periph.ptype == 'MMC' ): 937 seg_mmc_base = periph.pseg.base & 0xFFFFFFFF 938 seg_mmc_size = periph.pseg.size 939 mmc_channels = periph.channels 940 nb_mmc +=1 941 942 elif ( periph.ptype == 'MWR' ): 943 seg_mwr_base = periph.pseg.base & 0xFFFFFFFF 944 seg_wmr_size = periph.pseg.size 945 mwr_channels = periph.channels 946 nb_mwr +=1 947 948 elif ( periph.ptype == 'ROM' ): 949 seg_rom_base = periph.pseg.base & 0xFFFFFFFF 950 seg_rom_size = periph.pseg.size 951 rom_channels = periph.channels 952 nb_rom +=1 953 954 elif ( periph.ptype == 'SIM' ): 955 seg_sim_base = periph.pseg.base & 0xFFFFFFFF 956 seg_sim_size = periph.pseg.size 957 sim_channels = periph.channels 958 nb_sim +=1 959 960 elif ( periph.ptype == 'NIC' ): 961 seg_nic_base = periph.pseg.base & 0xFFFFFFFF 962 seg_nic_size = periph.pseg.size 963 nic_channels = periph.channels 964 nb_nic +=1 965 966 elif ( periph.ptype == 'PIC' ): 967 seg_pic_base = periph.pseg.base & 0xFFFFFFFF 968 seg_pic_size = periph.pseg.size 969 pic_channels = periph.channels 970 nb_pic +=1 971 972 elif ( periph.ptype == 'TIM' ): 973 seg_tim_base = periph.pseg.base & 0xFFFFFFFF 974 seg_tim_size = periph.pseg.size 975 tim_channels = periph.channels 976 nb_tim +=1 977 978 elif ( periph.ptype == 'TTY' ): 979 seg_tty_base = periph.pseg.base & 0xFFFFFFFF 980 seg_tty_size = periph.pseg.size 981 tty_channels = periph.channels 982 nb_tty +=1 983 984 elif ( periph.ptype == 'XCU' ): 985 seg_xcu_base = periph.pseg.base & 0xFFFFFFFF 986 seg_xcu_size = periph.pseg.size 987 xcu_channels = periph.channels 988 nb_xcu +=1 989 990 # don't mix ICU and XCU 991 assert ( nb_icu*nb_xcu == 0 ) 992 993 # no more than two access to external peripherals 994 assert ( nb_fbf <= 2 ) 995 assert ( nb_cma <= 2 ) 996 assert ( nb_ioc <= 2 ) 997 assert ( nb_nic <= 2 ) 998 assert ( nb_tim <= 2 ) 999 assert ( nb_tty <= 2 ) 1000 assert ( nb_pic <= 2 ) 1001 1002 # one and only one type of IOC controller 1003 assert ( use_hba or use_bdv or use_spi ) 1004 assert ( (use_hba and use_bdv) == False ) 1005 assert ( (use_hba and use_spi) == False ) 1006 assert ( (use_bdv and use_spi) == False ) 1007 1008 # Compute total number of processors 1009 for cluster in self.clusters: 1010 nb_total_procs += len( cluster.procs ) 1011 1012 # Compute physical addresses for BOOT vsegs 1013 boot_mapping_found = False 1014 boot_code_found = False 1015 boot_data_found = False 1016 boot_buffer_found = False 1017 boot_stack_found = False 1018 1019 for vseg in self.globs: 1020 if ( vseg.name == 'seg_boot_mapping' ): 1021 boot_mapping_base = vseg.vbase 1022 boot_mapping_size = vseg.vobjs[0].length 1023 boot_mapping_ident = vseg.ident 1024 boot_mapping_found = True 1025 1026 if ( vseg.name == 'seg_boot_code' ): 1027 boot_code_base = vseg.vbase 1028 boot_code_size = vseg.vobjs[0].length 1029 boot_code_ident = vseg.ident 1030 boot_code_found = True 1031 1032 if ( vseg.name == 'seg_boot_data' ): 1033 boot_data_base = vseg.vbase 1034 boot_data_size = vseg.vobjs[0].length 1035 boot_data_ident = vseg.ident 1036 boot_data_found = True 1037 1038 if ( vseg.name == 'seg_boot_buffer' ): 1039 boot_buffer_base = vseg.vbase 1040 boot_buffer_size = vseg.vobjs[0].length 1041 boot_buffer_ident = vseg.ident 1042 boot_buffer_found = True 1043 1044 if ( vseg.name == 'seg_boot_stack' ): 1045 boot_stack_base = vseg.vbase 1046 boot_stack_size = vseg.vobjs[0].length 1047 boot_stack_ident = vseg.ident 1048 boot_stack_found = True 1049 1050 # check all BOOT vsegs are found and identity mapping 1051 if ( (boot_mapping_found == False) or (boot_mapping_ident == False) ): 1052 print 'error in hard_config() : seg_boot_mapping missing or not ident' 1053 sys.exit() 1054 1055 if ( (boot_code_found == False) or (boot_code_ident == False) ): 1056 print 'error in hard_config() : seg_boot_code missing or not ident' 1057 sys.exit() 1058 1059 if ( (boot_data_found == False) or (boot_data_ident == False) ): 1060 print 'error in hard_config() : seg_boot_data missing or not ident' 1061 sys.exit() 1062 1063 if ( (boot_buffer_found == False) or (boot_buffer_ident == False) ): 1064 print 'error in hard_config() : seg_boot_buffer missing or not ident' 1065 sys.exit() 1066 1067 if ( (boot_stack_found == False) or (boot_stack_ident == False) ): 1068 print 'error in giet_vsegs() : seg_boot_stack missing or not ident' 1069 sys.exit() 1070 1071 # Search RAMDISK global vseg if required 1072 seg_rdk_base = 0xFFFFFFFF 1073 seg_rdk_size = 0 1074 seg_rdk_found = False 1075 1076 if self.use_ramdisk: 1077 for vseg in self.globs: 1078 if ( vseg.name == 'seg_ramdisk' ): 1079 seg_rdk_base = vseg.vbase 1080 seg_rdk_size = vseg.vobjs[0].length 1081 seg_rdk_found = True 1082 1083 if ( seg_rdk_found == False ): 1084 print 'Error in hard_config() "seg_ramdisk" not found' 1085 sys.exit(1) 1086 1087 # build string 1088 s = '/* Generated by tsarmap for %s */\n' % self.name 1089 s += '\n' 1090 s += '#ifndef HARD_CONFIG_H\n' 1091 s += '#define HARD_CONFIG_H\n' 1092 s += '\n' 1093 1094 s += '/* General platform parameters */\n' 1095 s += '\n' 1096 s += '#define X_SIZE %d\n' % self.x_size 1097 s += '#define Y_SIZE %d\n' % self.y_size 1098 s += '#define X_WIDTH %d\n' % self.x_width 1099 s += '#define Y_WIDTH %d\n' % self.y_width 1100 s += '#define X_IO %d\n' % self.x_io 1101 s += '#define Y_IO %d\n' % self.y_io 1102 s += '#define NB_PROCS_MAX %d\n' % self.procs_max 1103 s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc 1104 s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address 1105 s += '#define NB_TOTAL_PROCS %d\n' % nb_total_procs 1106 s += '\n' 1107 1108 s += '/* Peripherals */\n' 1109 s += '\n' 1110 s += '#define NB_TTY_CHANNELS %d\n' % tty_channels 1111 s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels 1112 s += '#define NB_NIC_CHANNELS %d\n' % nic_channels 1113 s += '#define NB_CMA_CHANNELS %d\n' % cma_channels 1114 s += '#define NB_TIM_CHANNELS %d\n' % tim_channels 1115 s += '#define NB_DMA_CHANNELS %d\n' % dma_channels 1116 s += '\n' 1117 s += '#define USE_XCU %d\n' % ( nb_xcu != 0 ) 1118 s += '#define USE_IOB %d\n' % ( nb_iob != 0 ) 1119 s += '#define USE_PIC %d\n' % ( nb_pic != 0 ) 1120 s += '#define USE_FBF %d\n' % ( nb_fbf != 0 ) 1121 s += '\n' 1122 s += '#define USE_IOC_BDV %d\n' % use_bdv 1123 s += '#define USE_IOC_SPI %d\n' % use_spi 1124 s += '#define USE_IOC_HBA %d\n' % use_hba 1125 s += '\n' 1126 s += '#define USE_RAMDISK %d\n' % self.use_ramdisk 1127 s += '\n' 1128 1129 s += '/* physical base addresses for peripherals */\n' 1130 s += '\n' 1131 s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base 1132 s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size 1133 s += '\n' 1134 s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base 1135 s += '#define SEG_DMA_SIZE 0x%x\n' % seg_cma_size 1136 s += '\n' 1137 s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base 1138 s += '#define SEG_FBF_SIZE 0x%x\n' % seg_cma_size 1139 s += '\n' 1140 s += '#define SEG_ICU_BASE 0x%x\n' % seg_icu_base 1141 s += '#define SEG_ICU_SIZE 0x%x\n' % seg_cma_size 1142 s += '\n' 1143 s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base 1144 s += '#define SEG_IOB_SIZE 0x%x\n' % seg_cma_size 1145 s += '\n' 1146 s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base 1147 s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size 1148 s += '\n' 1149 s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base 1150 s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size 1151 s += '\n' 1152 s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base 1153 s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size 1154 s += '\n' 1155 s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base 1156 s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size 1157 s += '\n' 1158 s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base 1159 s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size 1160 s += '\n' 1161 s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base 1162 s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size 1163 s += '\n' 1164 s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base 1165 s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size 1166 s += '\n' 1167 s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base 1168 s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size 1169 s += '\n' 1170 s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base 1171 s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size 1172 s += '\n' 1173 s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base 1174 s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size 1175 s += '\n' 1176 s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base 1177 s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size 1178 s += '\n' 1179 s += '#define VSEG_CLUSTER_INCREMENT 0x%x\n' % self.vseg_increment 1180 s += '\n' 1181 1182 s += '/* physical base addresses for identity mapped boot vsegs */\n' 1183 s += '\n' 1184 s += '#define SEG_BOOT_MAPPING_BASE 0x%x\n' % boot_mapping_base 1185 s += '#define SEG_BOOT_MAPPING_SIZE 0x%x\n' % boot_mapping_size 1186 s += '\n' 1187 s += '#define SEG_BOOT_CODE_BASE 0x%x\n' % boot_code_base 1188 s += '#define SEG_BOOT_CODE_SIZE 0x%x\n' % boot_code_size 1189 s += '\n' 1190 s += '#define SEG_BOOT_DATA_BASE 0x%x\n' % boot_data_base 1191 s += '#define SEG_BOOT_DATA_SIZE 0x%x\n' % boot_data_size 1192 s += '\n' 1193 s += '#define SEG_BOOT_BUFFER_BASE 0x%x\n' % boot_buffer_base 1194 s += '#define SEG_BOOT_BUFFER_SIZE 0x%x\n' % boot_buffer_size 1195 s += '\n' 1196 s += '#define SEG_BOOT_STACK_BASE 0x%x\n' % boot_stack_base 1197 s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size 1198 s += '#endif\n' 1199 1200 return s 1201 1202 # end of hard_config() 1203 1204 ####################### 1205 def netbsd_dts( self ): # compute string for netbsd.dts file generation, 1206 # used for netbsd configuration 1207 # header 1208 s = '/dts-v1/;\n' 1209 s += '\n' 1210 s += '/{\n' 1211 s += ' #address-cells = <2>;\n' 1212 s += ' #size-cells = <1>;\n' 1213 1214 # cpus (for each cluster) 1215 s += ' cpus {\n' 1216 s += ' #address-cells = <1>;\n' 1217 s += ' #size-cells = <0>;\n' 1218 1219 for cluster in self.clusters: 1220 for proc in cluster.procs: 1221 proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + proc.lpid 1222 1223 s += ' Mips,32@0x%x {\n' % proc_id 1224 s += ' device_type = "cpu";\n' 1225 s += ' icudev_type = "cpu:mips";\n' 1226 s += ' name = "Mips,32";\n' 1227 s += ' reg = <0x%x>;\n' % proc_id 1228 s += ' };\n' 1229 s += '\n' 1230 1231 s += ' };\n' 1232 1233 # rams (for each cluster) 1234 for cluster in self.clusters: 1235 for pseg in cluster.psegs: 1236 1237 if ( pseg.segtype == 'RAM' ): 1238 msb = pseg.base >> 32 1239 lsb = pseg.base & 0xFFFFFFFF 1240 size = pseg.size 1241 1242 s += ' %s@0x%x {\n' % (pseg.name, pseg.base) 1243 s += ' cached = <1>;\n' 1244 s += ' device_type = "memory";\n' 1245 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1246 s += ' };\n' 1247 1248 # peripherals (for each cluster) 1249 for cluster in self.clusters: 1250 1251 # research XCU component 1252 found_xcu = False 1253 for periph in cluster.periphs: 1254 if ( (periph.ptype == 'XCU') ): 1255 found_xcu = True 1256 xcu = periph 1257 msb = periph.pseg.base >> 32 1258 lsb = periph.pseg.base & 0xFFFFFFFF 1259 size = periph.pseg.size 1260 1261 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) 1262 s += ' device_type = "soclib:xicu:root";\n' 1263 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1264 s += ' input_lines = <%d>;\n' % periph.arg1 1265 s += ' ipis = <%d>;\n' % periph.arg2 1266 s += ' timers = <%d>;\n' % periph.arg3 1267 1268 output_id = 0 # output index from XCU 1269 for lpid in xrange ( len(cluster.procs) ): # destination processor index 1270 for itid in xrange ( self.irq_per_proc ): # input irq index on processor 1271 proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + lpid 1272 s += ' out@%d {\n' % output_id 1273 s += ' device_type = "soclib:xicu:filter";\n' 1274 s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid) 1275 s += ' output_line = <%d>;\n' % output_id 1276 s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base) 1277 s += ' };\n' 1278 1279 output_id += 1 1280 1281 s += ' };\n' 1282 1283 # research PIC component 1284 found_pic = False 1285 for periph in cluster.periphs: 1286 if ( periph.ptype == 'PIC' ): 1287 found_pic = True 1288 pic = periph 1289 msb = periph.pseg.base >> 32 1290 lsb = periph.pseg.base & 0xFFFFFFFF 1291 size = periph.pseg.size 1292 1293 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) 1294 s += ' device_type = "soclib:pic:root";\n' 1295 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1296 s += ' input_lines = <%d>;\n' % periph.channels 1297 s += ' };\n' 1298 1299 if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ): 1300 print 'error in netbsd_dts() : No XCU/PIC in cluster(%d,%d)' % (cluster.x, cluster.y) 1301 sys.exit(1) 1302 1303 if ( found_pic == True ): irq_tgt = pic 1304 else: irq_tgt = xcu 1305 1306 # get all others peripherals in cluster 1307 for periph in cluster.periphs: 1308 msb = periph.pseg.base >> 32 1309 lsb = periph.pseg.base & 0xFFFFFFFF 1310 size = periph.pseg.size 1311 1312 # research DMA component 1313 if ( periph.ptype == 'DMA' ): 1314 1315 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) 1316 s += ' device_type = "soclib:dma";\n' 1317 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1318 s += ' channel_count = <%d>;\n' % periph.channels 1319 1320 # multi-channels : get HWI index (to XCU) for each channel 1321 for channel in xrange( periph.channels ): 1322 hwi_id = 0xFFFFFFFF 1323 for irq in xcu.irqs: 1324 if ( (irq.isrtype == 'ISR_DMA') and (irq.channel == channel) ): 1325 hwi_id = irq.srcid 1326 if ( hwi_id == 0xFFFFFFFF ): 1327 print 'error in netbsd.dts() ISR_DMA channel %d not found' % channel 1328 sys.exit(1) 1329 1330 name = '%s@0x%x' % (xcu.pseg.name, xcu.pseg.base) 1331 s += ' irq@%d{\n' % channel 1332 s += ' device_type = "soclib:periph:irq";\n' 1333 s += ' output_line = <%d>;\n' % channel 1334 s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id) 1335 s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base) 1336 s += ' };\n' 1337 1338 s += ' };\n' 1339 1340 # research MMC component 1341 elif ( periph.ptype == 'MMC' ): 1342 1343 # get irq line index associated to MMC in XCU 1344 irq_in = 0xFFFFFFFF 1345 for irq in xcu.irqs: 1346 if ( irq.isrtype == 'ISR_MMC' ): irq_in = irq.srcid 1347 if ( irq_in == 0xFFFFFFFF ): 1348 print 'error in netbsd.dts() ISR_MMC not found' 1349 sys.exit(1) 1350 1351 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) 1352 s += ' device_type = "soclib:mmc";\n' 1353 s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in) 1354 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1355 s += ' };\n' 1356 1357 # research FBF component 1358 elif ( periph.ptype == 'FBF' ): 1359 1360 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) 1361 s += ' device_type = "soclib:framebuffer";\n' 1362 s += ' mode = <32>;\n' # bits par pixel 1363 s += ' width = <%d>;\n' % periph.arg1 1364 s += ' height = <%d>;\n' % periph.arg2 1365 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1366 s += ' };\n' 1367 1368 # research IOC component 1369 elif ( periph.ptype == 'IOC' ): 1370 1371 if ( periph.subtype == 'BDV' ): 1372 1373 # get irq line index associated to bdv 1374 irq_in = 0xFFFFFFFF 1375 for irq in irq_tgt.irqs: 1376 if ( irq.isrtype == 'ISR_BDV' ): irq_in = irq.srcid 1377 if ( irq_in == 0xFFFFFFFF ): 1378 print 'error in netbsd.dts() ISR_BDV not found' 1379 sys.exit(1) 1380 1381 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) 1382 s += ' device_type = "soclib:blockdevice";\n' 1383 s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in) 1384 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1385 s += ' };\n' 1386 1387 elif ( periph.subtype == 'HBA' ): 1388 print 'error in netbsd_dts() : HBA peripheral not supported by NetBSD' 1389 sys.exit(1) 1390 1391 elif ( periph.subtype == 'SPI' ): 1392 1393 # get irq line index associated to spi 1394 irq_in = 0xFFFFFFFF 1395 for irq in irq_tgt.irqs: 1396 if ( irq.isrtype == 'ISR_SPI' ): irq_in = irq.srcid 1397 if ( irq_in == 0xFFFFFFFF ): 1398 print 'error in netbsd.dts() ISR_SPI not found' 1399 sys.exit(1) 1400 1401 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) 1402 s += ' device_type = "soclib:spi";\n' 1403 s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in) 1404 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1405 s += ' };\n' 1406 1407 # research ROM component 1408 elif ( periph.ptype == 'ROM' ): 1409 1410 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) 1411 s += ' device_type = "rom";\n' 1412 s += ' cached = <1>;\n' 1413 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1414 s += ' };\n' 1415 1416 # research SIM component 1417 elif ( periph.ptype == 'SIM' ): 1418 1419 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) 1420 s += ' device_type = "soclib:simhelper";\n' 1421 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1422 s += ' };\n' 1423 1424 # research TTY component 1425 elif ( periph.ptype == 'TTY' ): 1426 1427 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) 1428 s += ' device_type = "soclib:tty";\n' 1429 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1430 s += ' channel_count = < %d >;\n' % periph.channels 1431 1432 # multi-channels : get HWI index (to XCU or PIC) for each channel 1433 for channel in xrange( periph.channels ): 1434 hwi_id = 0xFFFFFFFF 1435 for irq in irq_tgt.irqs: 1436 if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ): 1437 hwi_id = irq.srcid 1438 if ( hwi_id == 0xFFFFFFFF ): 1439 print 'error in netbsd.dts() ISR_TTY_RX channel %d not found' % channel 1440 sys.exit(1) 1441 1442 name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base) 1443 s += ' irq@%d{\n' % channel 1444 s += ' device_type = "soclib:periph:irq";\n' 1445 s += ' output_line = <%d>;\n' % channel 1446 s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id) 1447 s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base) 1448 s += ' };\n' 1449 1450 s += ' };\n' 1451 1452 # research IOB component 1453 elif ( periph.ptype == 'IOB' ): 1454 1455 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) 1456 s += ' device_type = "soclib:iob";\n' 1457 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1458 s += ' };\n' 1459 1460 # research NIC component 1461 elif ( periph.ptype == 'NIC' ): 1462 1463 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) 1464 s += ' device_type = "soclib:nic";\n' 1465 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1466 s += ' channel_count = < %d >;\n' % periph.channels 1467 1468 # multi-channels : get HWI index (to XCU or PIC) for RX & TX IRQs 1469 # RX IRQ : (2*channel) / TX IRQs : (2*channel + 1) 1470 for channel in xrange( periph.channels ): 1471 hwi_id = 0xFFFFFFFF 1472 for irq in irq_tgt.irqs: 1473 if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ): 1474 hwi_id = irq.srcid 1475 if ( hwi_id == 0xFFFFFFFF ): 1476 print 'error in netbsd.dts() ISR_NIC_RX channel %d not found' % channel 1477 sys.exit(1) 1478 1479 name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base) 1480 s += ' irq_rx@%d{\n' % channel 1481 s += ' device_type = "soclib:periph:irq";\n' 1482 s += ' output_line = <%d>;\n' % (2*channel) 1483 s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id) 1484 s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base) 1485 s += ' };\n' 1486 1487 hwi_id = 0xFFFFFFFF 1488 for irq in irq_tgt.irqs: 1489 if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ): 1490 hwi_id = irq.srcid 1491 if ( hwi_id == 0xFFFFFFFF ): 1492 print 'error in netbsd.dts() ISR_NIC_TX channel %d not found' % channel 1493 sys.exit(1) 1494 1495 name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base) 1496 s += ' irq_tx@%d{\n' % channel 1497 s += ' device_type = "soclib:periph:irq";\n' 1498 s += ' output_line = <%d>;\n' % (2*channel + 1) 1499 s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id) 1500 s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base) 1501 s += ' };\n' 1502 1503 s += ' };\n' 1504 1505 # research CMA component 1506 elif ( periph.ptype == 'CMA' ): 1507 1508 s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base) 1509 s += ' device_type = "soclib:cma";\n' 1510 s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size) 1511 s += ' channel_count = < %d >;\n' % periph.channels 1512 1513 # multi-channels : get HWI index (to XCU or PIC) for each channel 1514 for channel in xrange( periph.channels ): 1515 hwi_id = 0xFFFFFFFF 1516 for irq in irq_tgt.irqs: 1517 if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ): 1518 hwi_id = irq.srcid 1519 if ( hwi_id == 0xFFFFFFFF ): 1520 print 'error in netbsd.dts() ISR_CMA channel %d not found' % channel 1521 sys.exit(1) 1522 1523 name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base) 1524 s += ' irq@%d{\n' % channel 1525 s += ' device_type = "soclib:periph:irq";\n' 1526 s += ' output_line = <%d>;\n' % channel 1527 s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id) 1528 s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base) 1529 s += ' };\n' 1530 1531 s += ' };\n' 1532 1533 # research TIM component 1534 elif ( periph.ptype == 'TIM' ): 1535 1536 print 'error in netbsd_dts() : TIM peripheral not supported by NetBSD' 1537 sys.exit(1) 1538 1539 # research MWR component 1540 elif ( periph.ptype == 'MWR' ): 1541 1542 print 'error in netbsd_dts() : MWR peripheral not supported by NetBSD' 1543 sys.exit(1) 1544 1545 # research ICU component 1546 elif ( periph.ptype == 'ICU' ): 1547 print 'error in netbsd_dts() : ICU peripheral not supported by NetBSD' 1548 sys.exit(1) 1549 1550 # topology 1551 s += '\n' 1552 s += ' topology {\n' 1553 s += ' #address-cells = <2>;\n' 1554 s += ' #size-cells = <0>;\n' 1555 for cluster in self.clusters: 1556 s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y) 1557 s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y) 1558 s += ' devices = <\n' 1559 1560 offset = ((cluster.x << self.y_width) + cluster.y) * self.procs_max 1561 for proc in cluster.procs: 1562 s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid) 1563 for periph in cluster.periphs: 1564 s += ' &{/%s@0x%x}\n' % (periph.pseg.name, periph.pseg.base) 1565 1566 s += ' >;\n' 1567 s += ' };\n' 1568 s += ' };\n' 1569 s += '};\n' 1570 1571 return s 1572 # end netbsd_dts( ) 1573 1574 ########################### 1575 def almos_archinfo( self ): # compute string for arch.info file generation, 1576 # used for almos configuration 1577 # header 1578 s = '# arch.info file generated by tsarmap for %s\n' % self.name 1579 s += '\n' 1580 s += '[HEADER]\n' 1581 s += ' REVISION=1\n' 1582 s += ' ARCH=%s\n' % self.name 1583 s += ' XMAX=%d\n' % self.x_size 1584 s += ' YMAX=%d\n' % self.y_size 1585 s += ' CPU_NR=%d\n' % self.procs_max 1586 s += '\n' 1587 1588 # clusters 1589 cluster_id = 0 1590 for cluster in self.clusters: 1591 1592 ram = None 1593 nb_cpus = len( cluster.procs ) 1594 nb_devs = len( cluster.periphs ) 1595 if ( len( cluster.coprocs ) != 0 ): 1596 print 'Error in almos_archinfo() coprocessors not supported yet' 1597 sys.exit(1) 1598 1599 # search a RAM 1600 for pseg in cluster.psegs: 1601 if ( pseg.segtype == 'RAM' ): 1602 ram = pseg 1603 nb_devs += 1 1604 1605 # search XCU to get IRQs indexes if cluster contains peripherals 1606 if ( len( cluster.periphs ) != 0 ): 1607 tty_irq_id = None 1608 bdv_irq_id = None 1609 dma_irq_id = None 1610 1611 for periph in cluster.periphs: 1612 if ( periph.ptype == 'XCU' ): 1613 # scan irqs 1614 for irq in periph.irqs: 1615 if ( irq.isrtype == 'ISR_TTY_RX' ) : tty_irq_id = irq.srcid 1616 if ( irq.isrtype == 'ISR_BDV' ) : bdv_irq_id = irq.srcid 1617 if ( irq.isrtype == 'ISR_DMA' ) : dma_irq_id = irq.srcid 1618 1619 # Build the cluster description 1620 s += '[CLUSTER]\n' 1621 s += ' CID=%d\n' % cluster_id 1622 s += ' ARCH_CID=0x%x\n' % ((cluster.x << self.y_width) + cluster.y) 1623 s += ' CPU_NR=%d\n' % nb_cpus 1624 s += ' DEV_NR=%d\n' % nb_devs 1625 1626 1627 # Handling RAM when cluster contain a RAM 1628 if (ram != None ): 1629 base = ram.base 1630 size = ram.size 1631 irqid = -1 1632 s += ' DEVID=RAM' 1633 s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size ) 1634 1635 # Handling peripherals 1636 for periph in cluster.periphs: 1637 base = periph.pseg.base 1638 size = periph.pseg.size 1639 1640 if ( periph.ptype == 'XCU' ): 1641 1642 s += ' DEVID=XICU' 1643 s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size ) 1644 1645 elif ( (periph.ptype == 'TTY') 1646 and (tty_irq_id != None) ): 1647 1648 s += ' DEVID=TTY' 1649 s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, tty_irq_id ) 1650 1651 elif ( (periph.ptype == 'DMA') 1652 and (dma_irq_id != None) ): 1653 1654 s += ' DEVID=DMA' 1655 s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, dma_irq_id ) 1656 1657 elif ( periph.ptype == 'FBF' ): 1658 1659 s += ' DEVID=FB' 1660 s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size ) 1661 1662 elif ( (periph.ptype == 'IOC') and (periph.subtype == 'BDV') 1663 and (bdv_irq_id != None) ): 1664 1665 s += ' DEVID=BLKDEV' 1666 s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, bdv_irq_id ) 1667 1668 elif ( periph.ptype == 'PIC' ): 1669 1670 s += ' DEVID=IOPIC' 1671 s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size ) 1672 1673 else: 1674 print '# Warning from almos_archinfo() in cluster[%d,%d]' \ 1675 % (cluster.x, cluster.y) 1676 print '# peripheral type %s/%s not supported yet\n' \ 1677 % ( periph.ptype, periph.subtype ) 1678 1679 cluster_id += 1 1680 1681 return s 1682 1683 # end of almos_archinfo() 1684 1685 1686 1687 1688 1689 1690 1691 1692 ########################################################################################### 1693 class Cluster ( object ): 1694 ########################################################################################### 1695 def __init__( self, 1696 x, 1697 y ): 1698 1699 self.index = 0 # global index (set by Mapping constructor) 1700 self.x = x # x coordinate 1701 self.y = y # y coordinate 1702 self.psegs = [] # filled by addRam() or addPeriph() 1703 self.procs = [] # filled by addProc() 1704 self.coprocs = [] # filled by addCoproc() 1705 self.periphs = [] # filled by addPeriph() 1706 1707 return 1708 1709 ################ 1710 def xml( self ): # xml for a cluster 1711 1712 s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y) 1713 for pseg in self.psegs: s += pseg.xml() 1714 for proc in self.procs: s += proc.xml() 1715 for copr in self.coprocs: s += copr.xml() 1716 for peri in self.periphs: s += peri.xml() 1717 s += ' </cluster>\n' 1718 1719 return s 1720 1721 ############################################# 1722 def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster 1723 1724 if ( verbose ): 1725 print '*** cbin for cluster [%d,%d]' % (self.x, self.y) 1726 1727 # check index 1728 if (self.index != expected): 1729 print 'error in Cluster.cbin() : cluster global index = %d / expected = %d' \ 1730 % (self.index, expected ) 1731 sys.exit(1) 1732 1733 # compute global index for first pseg 1734 if ( len(self.psegs) > 0 ): 1735 pseg_id = self.psegs[0].index 1736 else: 1737 pseg_id = 0 1738 1739 # compute global index for first proc 1740 if ( len(self.procs) > 0 ): 1741 proc_id = self.procs[0].index 1742 else: 1743 proc_id = 0 1744 1745 # compute global index for first coproc 1746 if ( len(self.coprocs) > 0 ): 1747 coproc_id = self.coprocs[0].index 1748 else: 1749 coproc_id = 0 1750 1751 # compute global index for first periph 1752 if ( len(self.periphs) > 0 ): 1753 periph_id = self.periphs[0].index 1754 else: 1755 periph_id = 0 1756 1757 byte_stream = bytearray() 1758 byte_stream += mapping.int2bytes( 4 , self.x ) # x coordinate 1759 byte_stream += mapping.int2bytes( 4 , self.y ) # x coordinate 1760 byte_stream += mapping.int2bytes( 4 , len( self.psegs ) ) # number of psegs in cluster 1761 byte_stream += mapping.int2bytes( 4 , pseg_id ) # first pseg global index 1762 byte_stream += mapping.int2bytes( 4 , len( self.procs ) ) # number of procs in cluster 1763 byte_stream += mapping.int2bytes( 4 , proc_id ) # first proc global index 1764 byte_stream += mapping.int2bytes( 4 , len( self.coprocs ) ) # number of coprocs in cluster 1765 byte_stream += mapping.int2bytes( 4 , coproc_id ) # first coproc global index 1766 byte_stream += mapping.int2bytes( 4 , len( self.periphs ) ) # number of periphs in cluster 1767 byte_stream += mapping.int2bytes( 4 , periph_id ) # first periph global index 1768 1769 if ( verbose ): 1770 print 'nb_psegs = %d' % len( self.psegs ) 1771 print 'pseg_id = %d' % pseg_id 1772 print 'nb_procs = %d' % len( self.procs ) 1773 print 'proc_id = %d' % proc_id 1774 print 'nb_coprocs = %d' % len( self.coprocs ) 1775 print 'coproc_id = %d' % coproc_id 1776 print 'nb_periphs = %d' % len( self.periphs ) 1777 print 'periph_id = %d' % periph_id 1778 1779 return byte_stream 1780 1781 ########################################################################################### 139 1782 class Vspace( object ): 140 ####################### 141 def __init__( self, name, startname ): 142 self.name = name # application name 1783 ########################################################################################### 1784 def __init__( self, 1785 name, 1786 startname ): 1787 1788 self.index = 0 # global index ( set by addVspace() ) 1789 self.name = name # vspace name 143 1790 self.startname = startname # name of vobj containing the start_vector 144 self.vsegs = [] 1791 self.vsegs = [] 145 1792 self.tasks = [] 1793 146 1794 return 147 ########################## 148 def addTask( self, task ): 149 self.tasks.append( task ) 1795 1796 ################ 1797 def xml( self ): # xml for one vspace 1798 1799 s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname ) 1800 for vseg in self.vsegs: s += vseg.xml() 1801 for task in self.tasks: s += task.xml() 1802 s += ' </vspace>\n' 1803 1804 return s 1805 1806 ############################################# 1807 def cbin( self, mapping, verbose, expected ): # C binary structure for Vspace 1808 1809 if ( verbose ): 1810 print '*** cbin for vspace %s' % (self.name) 1811 1812 # check index 1813 if (self.index != expected): 1814 print 'error in Vspace.cbin() : vspace global index = %d / expected = %d' \ 1815 % (self.index, expected ) 1816 sys.exit(1) 1817 1818 # compute global index for vobj containing start_vector 1819 vobj_start_id = 0xFFFFFFFF 1820 for vseg in self.vsegs: 1821 if ( vseg.vobjs[0].name == self.startname ): 1822 vobj_start_id = vseg.vobjs[0].index 1823 if ( vobj_start_id == 0xFFFFFFFF ): 1824 print 'error in Vspace.cbin() : startname %s not found for vspace %s' \ 1825 % ( self.startname, self.name ) 1826 sys.exit(1) 1827 1828 # compute first vseg, vobj, task global index 1829 first_vseg_id = self.vsegs[0].index 1830 first_vobj_id = self.vsegs[0].vobjs[0].index 1831 first_task_id = self.tasks[0].index 1832 1833 # compute number of vobjs, tasks, vsegs 1834 nb_vsegs = len( self.vsegs ) 1835 nb_tasks = len( self.tasks ) 1836 nb_vobjs = 0 1837 for vseg in self.vsegs: 1838 nb_vobjs += len( vseg.vobjs ) 1839 1840 byte_stream = bytearray() 1841 byte_stream += mapping.str2bytes( 32, self.name ) # vspace name 1842 byte_stream += mapping.int2bytes( 4, vobj_start_id ) # vobj start_vector 1843 byte_stream += mapping.int2bytes( 4, nb_vsegs ) # number of vsegs 1844 byte_stream += mapping.int2bytes( 4, nb_vobjs ) # number of vobjs 1845 byte_stream += mapping.int2bytes( 4, nb_tasks ) # number of tasks 1846 byte_stream += mapping.int2bytes( 4, first_vseg_id ) # first vseg global index 1847 byte_stream += mapping.int2bytes( 4, first_vobj_id ) # first vobj global index 1848 byte_stream += mapping.int2bytes( 4, first_task_id ) # first task global index 1849 1850 if ( verbose ): 1851 print 'start_id = %d' % vobj_start_id 1852 print 'nb_vsegs = %d' % nb_vsegs 1853 print 'nb_vobjs = %d' % nb_vobjs 1854 print 'nb_tasks = %d' % nb_tasks 1855 print 'vseg_id = %d' % first_vseg_id 1856 print 'vobj_id = %d' % first_vobj_id 1857 print 'task_id = %d' % first_task_id 1858 1859 return byte_stream 1860 1861 ########################################################################################### 1862 class Task( object ): 1863 ########################################################################################### 1864 def __init__( self, 1865 name, 1866 trdid, 1867 x, 1868 y, 1869 p, 1870 stackname, 1871 heapname, 1872 startid, 1873 usetty = False, 1874 usenic = False, 1875 usecma = False, 1876 usehba = False, 1877 usetim = False ): 1878 1879 self.index = 0 # global index value set by addTask() 1880 self.name = name # tsk name 1881 self.trdid = trdid # task index (unique in vspace) 1882 self.x = x # cluster x coordinate 1883 self.y = y # cluster y coordinate 1884 self.p = p # processor local index 1885 self.stackname = stackname # name of vobj containing the stack 1886 self.heapname = heapname # name of vobj containing the heap 1887 self.startid = startid # index in start_vector 1888 self.usetty = usetty # request a private TTY channel 1889 self.usenic = usenic # request a private NIC channel 1890 self.usecma = usecma # request a private CMA channel 1891 self.usehba = usehba # request a private HBA channel 1892 self.usetim = usetim # request a private TIM channel 150 1893 return 151 1894 152 ########################## 153 def addVseg( self, vseg ): 154 self.vsegs.append( vseg ) 1895 ################ 1896 def xml( self ): # xml for one task 1897 1898 s = ' <task name="%s"' % self.name 1899 s += ' trdid="%d"' % self.trdid 1900 s += ' x="%d"' % self.x 1901 s += ' y="%d"' % self.y 1902 s += ' p="%d"' % self.p 1903 s += ' stackname="%s"' % self.stackname 1904 s += ' heapname="%s"' % self.heapname 1905 s += ' startid="%d"' % self.startid 1906 if self.usetty != 0: s += ' usetty="1"' 1907 if self.usenic != 0: s += ' usenic="1"' 1908 if self.usecma != 0: s += ' usehba="1"' 1909 if self.usehba != 0: s += ' usehba="1"' 1910 if self.usetim != 0: s += ' usehba="1"' 1911 s += ' />\n' 1912 1913 return s 1914 1915 ##################################################### 1916 def cbin( self, mapping, verbose, expected, vspace ): # C binary data structure for Task 1917 1918 if ( verbose ): 1919 print '*** cbin for task %s in vspace %s' % (self.name, vspace.name) 1920 1921 # check index 1922 if (self.index != expected): 1923 print 'error in Task.cbin() : task global index = %d / expected = %d' \ 1924 % (self.index, expected ) 1925 sys.exit(1) 1926 1927 # compute cluster global index 1928 cluster_id = (self.x * mapping.y_size) + self.y 1929 1930 # compute vobj local index for stack 1931 vobj_stack_id = 0xFFFFFFFF 1932 for vseg in vspace.vsegs: 1933 if ( vseg.vobjs[0].name == self.stackname ): 1934 vobj_stack_id = vseg.vobjs[0].index 1935 if ( vobj_stack_id == 0xFFFFFFFF ): 1936 print 'error in Task.cbin() : stackname %s not found for task %s in vspace %s' \ 1937 % ( self.stackname, self.name, vspace.name ) 1938 sys.exit(1) 1939 1940 # compute vobj local index for heap 1941 vobj_heap_id = 0xFFFFFFFF 1942 for vseg in vspace.vsegs: 1943 if ( vseg.vobjs[0].name == self.heapname ): 1944 vobj_heap_id = vseg.vobjs[0].index 1945 if ( vobj_heap_id == 0xFFFFFFFF ): 1946 print 'error in Task.cbin() : heapname %s not found for task %s in vspace %s' \ 1947 % ( self.heapname, self.name, vspace.name ) 1948 sys.exit(1) 1949 1950 byte_stream = bytearray() 1951 byte_stream += mapping.str2bytes( 32, self.name ) # task name in vspace 1952 byte_stream += mapping.int2bytes( 4, cluster_id ) # cluster global index 1953 byte_stream += mapping.int2bytes( 4, self.p ) # processor local index in cluster 1954 byte_stream += mapping.int2bytes( 4, self.trdid ) # thread local index in vspace 1955 byte_stream += mapping.int2bytes( 4, vobj_stack_id ) # stack vobj local index 1956 byte_stream += mapping.int2bytes( 4, vobj_heap_id ) # heap vobj local index 1957 byte_stream += mapping.int2bytes( 4, self.startid ) # index in start vector 1958 byte_stream += mapping.int2bytes( 4, self.usetty ) # TTY channel required 1959 byte_stream += mapping.int2bytes( 4, self.usenic ) # NIC channel required 1960 byte_stream += mapping.int2bytes( 4, self.usecma ) # CMA channel required 1961 byte_stream += mapping.int2bytes( 4, self.usehba ) # IOC channel required 1962 byte_stream += mapping.int2bytes( 4, self.usetim ) # TIM channel required 1963 1964 if ( verbose ): 1965 print 'clusterid = %d' % cluster_id 1966 print 'lpid = %d' % self.p 1967 print 'trdid = %d' % self.trdid 1968 print 'stackid = %d' % vobj_stack_id 1969 print 'heapid = %d' % vobj_heap_id 1970 print 'startid = %d' % self.startid 1971 1972 return byte_stream 1973 1974 ########################################################################################### 1975 class Vseg( object ): 1976 ########################################################################################### 1977 def __init__( self, 1978 name, 1979 vbase, 1980 mode, 1981 x, 1982 y, 1983 psegname, 1984 ident = False ): 1985 1986 assert mode in VSEGMODES 1987 1988 self.index = 0 # global index ( set by addVseg() ) 1989 self.name = name # vseg name 1990 self.vbase = vbase & 0xFFFFFFFF # virtual base address in vspace 1991 self.mode = mode # CXWU access rights 1992 self.x = x # x coordinate of destination cluster 1993 self.y = y # y coordinate of destination cluster 1994 self.psegname = psegname # name of pseg in destination cluster 1995 self.ident = ident # identity mapping required 1996 self.vobjs = [] 155 1997 return 156 1998 157 #################### 158 def __str__( self ): # xml for one vspace 159 s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname ) 160 for vseg in self.vsegs: 161 s += str( vseg ) 162 for task in self.tasks: 163 s += str( task ) 164 s += ' </vspace>\n' 1999 ################ 2000 def xml( self ): # xml for one vseg 2001 2002 s = ' <vseg name="%s" vbase="0x%x" mode="%s" x="%d" y="%d" psegname="%s"' \ 2003 % ( self.name, self.vbase, self.mode, self.x, self.y, self.psegname ) 2004 if ( self.ident ): s += ' ident="1" >\n' 2005 else: s += ' >\n' 2006 for vobj in self.vobjs: s += vobj.xml() 2007 s += ' </vseg>\n' 2008 165 2009 return s 166 2010 167 ##################### 168 class Task( object ): 169 ##################### 170 def __init__( self, name, trdid, x, y, p, stackname, heapname, startid, \ 171 usetty = False, usenic = False, usehba = False ): 172 self.name = name # thread name 173 self.trdid = trdid # thread index (unique in vspace) 174 self.x = x # processor x coordinate 175 self.y = y # processor y coordinate 176 self.p = p # processor local index 177 self.stackname = stackname # name of vobj containing the stack 178 self.heapname = heapname # name of vobj containing the heap 179 self.startid = startid # index in start_vector 180 self.usetty = usetty # request a private TTY channel 181 self.usenic = usenic # request a private NIC channel 182 self.usehba = usehba # request a private HBA channel 183 return 184 185 #################### 186 def __str__( self ): # xml for one task 187 s = ' <task name="%s" trdid="%d" x="%d" y="%d" p="%d" stackname="%s" heapname="%s" startid="%d"' \ 188 % (self.name, self.trdid, self.x, self.y, self.p, self.stackname, self.heapname, self.startid) 189 if self.usetty != 0: 190 s += ' usetty="1"' 191 if self.usenic != 0: 192 s += ' usenic="1"' 193 if self.usehba != 0: 194 s += ' usehba="1"' 195 s += ' />\n' 196 return s 197 198 ###################### 199 class Vseg( object ): 200 ###################### 201 def __init__( self, name, vbase, mode, x, y, psegname, ident = False ): 202 assert mode in ['CXWU','CXW_','CX_U','CX__', 203 'C_WU','C_W_','C__U','C___', 204 '_XWU','_XW_','_X_U','_X__', 205 '__WU','__W_','___U','____'] 206 self.name = name 207 self.vbase = vbase 208 self.mode = mode 209 self.x = x 210 self.y = y 211 self.psegname = psegname 212 self. ident = ident 213 self.vobjs = [] 214 return 215 216 ##################### 217 def add ( self, vo ): 218 self.vobjs.append( vo ) 219 return 220 221 #################### 222 def __str__( self ): # xml for one vseg 223 s = ' <vseg name="%s" vbase="0x%x" mode="%s" x="%d" y="%d" psegname="%s"' \ 224 % ( self.name, self.vbase, self.mode, self.x, self.y, self.psegname ) 225 if self.ident != 0: 226 s += ' ident="1"' 227 s += ' >\n' 228 for vobj in self.vobjs: 229 s += str( vobj ) 230 s += ' </vseg>\n' 231 return s 232 233 ###################### 2011 ############################################# 2012 def cbin( self, mapping, verbose, expected ): # C binary structure for Vseg 2013 2014 if ( verbose ): 2015 print '*** cbin for vseg[%d] %s' % (self.index, self.name) 2016 2017 # check index 2018 if (self.index != expected): 2019 print 'error in Vseg.cbin() : vseg global index = %d / expected = %d' \ 2020 % (self.index, expected ) 2021 sys.exit(1) 2022 2023 # compute pseg_id 2024 pseg_id = 0xFFFFFFFF 2025 cluster_id = (self.x * mapping.y_size) + self.y 2026 cluster = mapping.clusters[cluster_id] 2027 for pseg in cluster.psegs: 2028 if (self.psegname == pseg.name): 2029 pseg_id = pseg.index 2030 if (pseg_id == 0xFFFFFFFF): 2031 print 'error in Vseg.cbin() : psegname %s not found for vseg %s in cluster %d' \ 2032 % ( self.psegname, self.name, cluster_id ) 2033 sys.exit(1) 2034 2035 # compute numerical value for mode 2036 mode_id = 0xFFFFFFFF 2037 for x in xrange( len(VSEGMODES) ): 2038 if ( self.mode == VSEGMODES[x] ): 2039 mode_id = x 2040 if ( mode_id == 0xFFFFFFFF ): 2041 print 'error in Vseg.cbin() : undefined vseg mode %s' % self.mode 2042 sys.exit(1) 2043 2044 # compute vobj_id 2045 vobj_id = self.vobjs[0].index 2046 2047 byte_stream = bytearray() 2048 byte_stream += mapping.str2bytes( 32, self.name ) # vseg name 2049 byte_stream += mapping.int2bytes( 4, self.vbase ) # virtual base address 2050 byte_stream += mapping.int2bytes( 8, 0 ) # physical base address 2051 byte_stream += mapping.int2bytes( 4, 0 ) # vseg size (bytes) 2052 byte_stream += mapping.int2bytes( 4, pseg_id ) # physical segment global index 2053 byte_stream += mapping.int2bytes( 4, mode_id ) # CXWU flags 2054 byte_stream += mapping.int2bytes( 4, len(self.vobjs) ) # number of vobjs in vseg 2055 byte_stream += mapping.int2bytes( 4, vobj_id ) # first vobj global index 2056 byte_stream += mapping.int2bytes( 4, 0 ) # linked list of vsegs on same pseg 2057 byte_stream += mapping.int2bytes( 1, 0 ) # mapped when non zero 2058 byte_stream += mapping.int2bytes( 1, self.ident ) # identity mapping when non zero 2059 byte_stream += mapping.int2bytes( 2, 0 ) # reserved (padding) 2060 2061 if ( verbose ): 2062 print 'vbase = %x' % self.vbase 2063 print 'pseg_id = %d' % pseg_id 2064 print 'mode = %s' % self.mode 2065 print 'nb_vobjs = %d' % len(self.vobjs) 2066 print 'vobj_id = %d' % vobj_id 2067 2068 return byte_stream 2069 2070 ########################################################################################### 234 2071 class Vobj( object ): 235 ###################### 236 def __init__( self, name, length, vtype, binpath = None, align = 0, init = 0 ): 2072 ########################################################################################### 2073 def __init__( self, 2074 name, 2075 length, 2076 vtype, 2077 binpath = '', 2078 align = 0, 2079 init = 0 ): 2080 237 2081 assert vtype in ['ELF','BLOB','PTAB','PERI','MWMR','LOCK', \ 238 2082 'BUFFER','BARRIER','CONST','MEMSPACE','SCHED'] 239 self.name = name 240 self.vtype = vtype 241 self.length = length 242 self.binpath = binpath 243 self.align = align 244 self.init = init 2083 2084 assert (vtype != 'ELF') or (binpath != '') 2085 2086 self.index = 0 # global index ( set by addVobj() ) 2087 self.name = name # vobj name (unique in vspace) 2088 self.vtype = vtype # vobj type (defined in mapping_info.h) 2089 self.length = length # vobj size (bytes) 2090 self.binpath = binpath # pathname for (ELF type) 2091 self.align = align # required alignment (logarithm of 2) 2092 self.init = init # initialisation value (for BARRIER or MWMR types) 2093 245 2094 return 246 2095 247 #################### 248 def __str__( self ): # xml for a vobj 2096 ################ 2097 def xml( self ): # xml for a vobj 2098 249 2099 s = ' <vobj name="%s" type="%s" length="0x%x"' \ 250 2100 % ( self.name, self.vtype, self.length ) 251 if (self.binpath != None): 252 s += ' binpath="%s"' % (self.binpath) 253 if (self.align != 0): 254 s += ' align="%d"' % (self.align) 255 if (self.init != 0): 256 s += ' init="%d"' % (self.init) 2101 if (self.binpath != ''): s += ' binpath="%s"' % (self.binpath) 2102 if (self.align != 0 ): s += ' align="%d"' % (self.align) 2103 if (self.init != 0 ): s += ' init="%d"' % (self.init) 257 2104 s += ' />\n' 2105 258 2106 return s 259 2107 260 ######################### 261 class Cluster ( object ): 262 ######################### 263 def __init__( self, x, y ): 264 self.x = x 265 self.y = y 266 self.psegs = [] 267 self.peripherals = [] 268 self.procs = [] 2108 ############################################# 2109 def cbin( self, mapping, verbose, expected ): # C binary structure for Vobj 2110 2111 # check index 2112 if (self.index != expected): 2113 print 'error in Vobj.cbin() : vobj global index = %d / expected = %d' \ 2114 % (self.index, expected ) 2115 sys.exit(1) 2116 elif ( verbose ): 2117 print '*** cbin for vobj[%d] %s' % (self.index, self.name) 2118 2119 # compute numerical value for vtype 2120 vtype_int = 0xFFFFFFFF 2121 for x in xrange( len(VOBJTYPES) ): 2122 if ( self.vtype == VOBJTYPES[x] ): 2123 vtype_int = x 2124 if ( vtype_int == 0xFFFFFFFF ): 2125 print 'error in Vobj.cbin() : undefined vobj type %s' % self.vtype 2126 sys.exit(1) 2127 2128 byte_stream = bytearray() 2129 byte_stream += mapping.str2bytes( 32, self.name ) # vobj name 2130 byte_stream += mapping.str2bytes( 64, self.binpath ) # pathname for .elf file 2131 byte_stream += mapping.int2bytes( 4 , vtype_int ) # vobj type 2132 byte_stream += mapping.int2bytes( 4 , self.length ) # vobj size 2133 byte_stream += mapping.int2bytes( 4 , self.align ) # required alignment 2134 byte_stream += mapping.int2bytes( 4 , 0 ) # virtual base address 2135 byte_stream += mapping.int2bytes( 8 , 0 ) # physical base address 2136 byte_stream += mapping.int2bytes( 4 , self.init ) # init value 2137 2138 if ( verbose ): 2139 print 'binpath = %s' % self.binpath 2140 print 'type = %s' % self.vtype 2141 print 'length = %x' % self.length 2142 2143 return byte_stream 2144 2145 ########################################################################################### 2146 class Processor ( object ): 2147 ########################################################################################### 2148 def __init__( self, 2149 x, 2150 y, 2151 lpid ): 2152 2153 self.index = 0 # global index ( set by addProc() ) 2154 self.x = x # x cluster coordinate 2155 self.y = y # y cluster coordinate 2156 self.lpid = lpid # processor local index 2157 269 2158 return 270 2159 271 #################### 272 def __str__( self ): # xml for a cluster 273 s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y) 274 for pseg in self.psegs: 275 s += str( pseg ) # psegs type RAM 276 for peri in self.peripherals: 277 s += str(peri.pseg) # psegs type PERI 278 for proc in self.procs: 279 s += str( proc ) # processors 280 for peri in self.peripherals: 281 s += str( peri ) # peripherals 282 s += ' </cluster>\n' 283 return s 284 285 ########################### 286 class Processor ( object ): 287 ########################### 288 def __init__( self, x, y, lpid ): 289 self.x = x 290 self.y = y 291 self.lpid = lpid 292 return 293 294 #################### 295 def __str__( self ): # xml for a processor 2160 ################ 2161 def xml( self ): # xml for a processor 296 2162 return ' <proc index="%d" />\n' % (self.lpid) 297 2163 298 ###################### 2164 ############################################# 2165 def cbin( self, mapping, verbose, expected ): # C binary structure for Proc 2166 2167 if ( verbose ): 2168 print '*** cbin for proc %d in cluster (%d,%d)' % (self.lpid, self.x, self.y) 2169 2170 # check index 2171 if (self.index != expected): 2172 print 'error in Proc.cbin() : proc global index = %d / expected = %d' \ 2173 % (self.index, expected ) 2174 sys.exit(1) 2175 2176 byte_stream = bytearray() 2177 byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index 2178 2179 return byte_stream 2180 2181 ########################################################################################### 299 2182 class Pseg ( object ): 300 ###################### 301 def __init__( self, name, base, size, segtype ): 302 self.name = name 303 self.base = base 304 self.size = size 305 self.segtype = segtype 306 assert segtype in ['RAM','PERI'] 2183 ########################################################################################### 2184 def __init__( self, 2185 name, 2186 base, 2187 size, 2188 x, 2189 y, 2190 segtype ): 2191 2192 assert( segtype in PSEGTYPES ) 2193 2194 self.index = 0 # global index ( set by addPseg() ) 2195 self.name = name # pseg name (unique in cluster) 2196 self.base = base # physical base address 2197 self.size = size # segment size (bytes) 2198 self.x = x # cluster x coordinate 2199 self.y = y # cluster y coordinate 2200 self.segtype = segtype # RAM / PERI (defined in mapping_info.h) 2201 307 2202 return 308 2203 309 #################### 310 def __str__( self ): # xml for a pseg 2204 ################ 2205 def xml( self ): # xml for a pseg 2206 311 2207 return ' <pseg name="%s" type="%s" base="0x%x" length="0x%x" />\n' \ 312 2208 % (self.name, self.segtype, self.base, self.size) 313 2209 314 ############################ 315 class Peripheral ( object ): 316 ############################ 317 def __init__( self, name, base, size, ptype, subtype, channels = 1): 318 self.channels = channels 319 self.ptype = ptype 320 self.subtype = subtype 321 self.pseg = Pseg( name, base, size, 'PERI' ) 2210 ###################################################### 2211 def cbin( self, mapping, verbose, expected, cluster ): # C binary structure for Pseg 2212 2213 if ( verbose ): 2214 print '*** cbin for pseg[%d] %s in cluster[%d,%d]' \ 2215 % (self.index, self.name, cluster.x, cluster.y) 2216 2217 # check index 2218 if (self.index != expected): 2219 print 'error in Pseg.cbin() : pseg global index = %d / expected = %d' \ 2220 % (self.index, expected ) 2221 sys.exit(1) 2222 2223 # compute numerical value for segtype 2224 segtype_int = 0xFFFFFFFF 2225 for x in xrange( len(PSEGTYPES) ): 2226 if ( self.segtype == PSEGTYPES[x] ): 2227 segtype_int = x 2228 if ( segtype_int == 0xFFFFFFFF ): 2229 print 'error in Pseg.cbin() : undefined segment type %s' % self.segtype 2230 sys.exit(1) 2231 2232 byte_stream = bytearray() 2233 byte_stream += mapping.str2bytes( 32, self.name ) # pseg name 2234 byte_stream += mapping.int2bytes( 8 , self.base ) # physical base address 2235 byte_stream += mapping.int2bytes( 8 , self.size ) # segment length 2236 byte_stream += mapping.int2bytes( 4 , segtype_int ) # segment type 2237 byte_stream += mapping.int2bytes( 4 , cluster.index ) # cluster global index 2238 byte_stream += mapping.int2bytes( 4 , 0 ) # linked list of vsegs 2239 2240 if ( verbose ): 2241 print 'pbase = %x' % self.base 2242 print 'size = %x' % self.size 2243 print 'type = %s' % self.segtype 2244 2245 return byte_stream 2246 2247 ########################################################################################### 2248 class Periph ( object ): 2249 ########################################################################################### 2250 def __init__( self, 2251 pseg, # associated pseg 2252 ptype, # peripheral type 2253 subtype = 'NONE', # peripheral subtype 2254 channels = 1, # for multi-channels peripherals 2255 arg = 0 ): # optional argument (semantic depends on ptype) 2256 2257 assert ptype in PERIPHTYPES 2258 2259 assert subtype in PERIPHSUBTYPES 2260 2261 self.index = 0 # global index ( set by addPeriph() ) 2262 self.channels = channels 2263 self.ptype = ptype 2264 self.subtype = subtype 2265 self.arg = arg 2266 self.pseg = pseg 2267 self.irqs = [] 322 2268 return 323 2269 324 ################ ####325 def __str__( self ): # xml for a peripheral326 s = ' <periph type="%s" subtype="%s" psegname="%s" channels="%d" >\n' \ 327 % ( self.ptype, self.subtype, self.pseg.name, self.channels )328 if ( self.ptype == 'PIC' ):329 for i in self.irqs:330 s += str( i ) # picIrq331 if ( (self.ptype == 'XCU') or (self.ptype == 'ICU') ):332 for i in self.irqs:333 s += str( i ) # xcuIrq2270 ################ 2271 def xml( self ): # xml for a periph 2272 2273 s = ' <periph type="%s"' % self.ptype 2274 s += ' subtype="%s"' % self.subtype 2275 s += ' psegname="%s"' % self.pseg.name 2276 s += ' channels="%d"' % self.channels 2277 s += ' arg="%d" >\n' % self.arg 2278 if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') or (self.ptype == 'ICU') ): 2279 for irq in self.irqs: s += irq.xml() 334 2280 s += ' </periph>\n' 2281 335 2282 return s 336 2283 337 ######################## 338 class Tty( Peripheral ): 339 ######################## 340 def __init__( self, name, base, size, channels ): 341 Peripheral.__init__( self, name, base, size, 'TTY', 'NONE', channels ) 2284 ############################################# 2285 def cbin( self, mapping, verbose, expected ): # C binary structure for Periph 2286 2287 if ( verbose ): 2288 print '*** cbin for periph %s in cluster [%d,%d]' \ 2289 % (self.ptype, self.pseg.x, self.pseg.y) 2290 2291 # check index 2292 if (self.index != expected): 2293 print 'error in Periph.cbin() : periph global index = %d / expected = %d' \ 2294 % (self.index, expected ) 2295 sys.exit(1) 2296 2297 # compute pseg global index 2298 pseg_id = self.pseg.index 2299 2300 # compute first irq global index 2301 if ( len(self.irqs) > 0 ): 2302 irq_id = self.irqs[0].index 2303 else: 2304 irq_id = 0 2305 2306 # compute numerical value for ptype 2307 ptype_id = 0xFFFFFFFF 2308 for x in xrange( len(PERIPHTYPES) ): 2309 if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x 2310 if ( ptype_id == 0xFFFFFFFF ): 2311 print 'error in Periph.cbin() : undefined peripheral type %s' % self.ptype 2312 sys.exit(1) 2313 2314 # compute numerical value for subtype 2315 subtype_id = 0xFFFFFFFF 2316 for x in xrange( len(PERIPHSUBTYPES) ): 2317 if ( self.subtype == PERIPHSUBTYPES[x] ): subtype_id = x 2318 2319 # compute 2320 byte_stream = bytearray() 2321 byte_stream += mapping.int2bytes( 4 , ptype_id ) # peripheral type 2322 byte_stream += mapping.int2bytes( 4 , subtype_id ) # peripheral subtype 2323 byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index 2324 byte_stream += mapping.int2bytes( 4 , self.channels ) # number of channels 2325 byte_stream += mapping.int2bytes( 4 , self.arg ) # optionnal argument 2326 byte_stream += mapping.int2bytes( 4 , len( self.irqs ) ) # number of input irqs 2327 byte_stream += mapping.int2bytes( 4 , irq_id ) # first irq global index 2328 2329 if ( verbose ): 2330 print 'ptype = %d' % ptype_id 2331 print 'pseg_id = %d' % pseg_id 2332 print 'nb_irqs = %d' % len( self.irqs ) 2333 print 'irq_id = %d' % irq_id 2334 return byte_stream 2335 2336 ########################################################################################### 2337 class Irq ( object ): 2338 ########################################################################################### 2339 def __init__( self, 2340 irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only) 2341 srcid, # input IRQ index (for XCU or PIC) 2342 isrtype, # Type of ISR to be executed 2343 channel = 0 ): # channel index for multi-channel ISR 2344 2345 assert irqtype in IRQTYPES 2346 assert isrtype in ISRTYPES 2347 assert srcid < 32 2348 2349 self.index = 0 # global index ( set by addIrq() ) 2350 self.irqtype = irqtype # IRQ type 2351 self.srcid = srcid # source IRQ index 2352 self.isrtype = isrtype # ISR type 2353 self.channel = channel # channel index (for multi-channels ISR) 342 2354 return 343 2355 344 ######################## 345 class Dma( Peripheral ): 346 ######################## 347 def __init__( self, name, base, size, channels ): 348 Peripheral.__init__( self, name, base, size, 'DMA', 'NONE', channels ) 2356 ################ 2357 def xml( self ): # xml for Irq 2358 2359 return ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" />\n' \ 2360 % ( self.irqtype, self.srcid, self.isrtype, self.channel ) 2361 2362 ############################################# 2363 def cbin( self, mapping, verbose, expected ): # C binary structure for Irq 2364 2365 if ( verbose ): 2366 print '*** cbin for irq[%d]' % (self.index) 2367 2368 # check index 2369 if (self.index != expected): 2370 print 'error in Irq.cbin() : irq global index = %d / expected = %d' \ 2371 % (self.index, expected ) 2372 sys.exit(1) 2373 2374 # compute numerical value for irqtype 2375 irqtype_id = 0xFFFFFFFF 2376 for x in xrange( len(IRQTYPES) ): 2377 if ( self.irqtype == IRQTYPES[x] ): 2378 irqtype_id = x 2379 if ( irqtype_id == 0xFFFFFFFF ): 2380 print 'error in Irq.cbin() : undefined irqtype %s' % self.irqtype 2381 sys.exit(1) 2382 2383 # compute numerical value for isrtype 2384 isrtype_id = 0xFFFFFFFF 2385 for x in xrange( len(ISRTYPES) ): 2386 if ( self.isrtype == ISRTYPES[x] ): 2387 isrtype_id = x 2388 if ( isrtype_id == 0xFFFFFFFF ): 2389 print 'error in Irq.cbin() : undefined isrtype %s' % self.isrtype 2390 sys.exit(1) 2391 2392 byte_stream = bytearray() 2393 byte_stream += mapping.int2bytes( 4, irqtype_id ) 2394 byte_stream += mapping.int2bytes( 4, self.srcid ) 2395 byte_stream += mapping.int2bytes( 4, isrtype_id ) 2396 byte_stream += mapping.int2bytes( 4, self.channel ) 2397 byte_stream += mapping.int2bytes( 4, 0 ) 2398 byte_stream += mapping.int2bytes( 4, 0 ) 2399 2400 if ( verbose ): 2401 print 'irqtype = %s' % self.irqtype 2402 print 'srcid = %d' % self.srcid 2403 print 'isrtype = %s' % self.isrtype 2404 print 'channel = %d' % self.channel 2405 2406 return byte_stream 2407 2408 ########################################################################################### 2409 class Coproc ( object ): 2410 ########################################################################################### 2411 def __init__( self, 2412 pseg ): # associated pseg 2413 2414 self.index = 0 # global index value set by addCoproc() 2415 self.pseg = pseg 2416 self.ports = [] 2417 349 2418 return 350 2419 351 ######################## 352 class Bdv( Peripheral ): 353 ######################## 354 def __init__( self, name, base, size ): 355 Peripheral.__init__( self, name, base, size, 'IOC', 'BDV' ) 2420 ################ 2421 def xml( self ): # xml for Coproc 2422 2423 print 'error in Coproc.xml() : not defined yet' 2424 sys.exit(1) 2425 2426 return 2427 2428 ############################################# 2429 def cbin( self, mapping, verbose, expected ): # C binary structure for Coproc 2430 2431 if ( verbose ): 2432 print '*** cbin for coproc in cluster (%d,%d)' % (self.pseg.x, self.pseg.y) 2433 2434 # check index 2435 if (self.index != expected): 2436 print 'error in Coproc.cbin() : coproc global index = %d / expected = %d' \ 2437 % (self.index, expected ) 2438 sys.exit(1) 2439 2440 # compute pseg global index 2441 pseg_id = self.pseg.index 2442 2443 # compute first port global index 2444 port_id = self.ports[0].index 2445 2446 byte_stream = bytearray() 2447 byte_stream += mapping.str2bytes( 32, self.pseg.name ) # probablement inutile (AG) 2448 byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index 2449 byte_stream += mapping.int2bytes( 4 , len( self.ports ) ) # number of input irqs 2450 byte_stream += mapping.int2bytes( 4 , port_id ) # first port global index 2451 2452 if ( verbose ): 2453 print 'irqtype = %s' % self.irqtype 2454 print 'pseg_id = %d' % pseg_id 2455 print 'nb_ports = %d' % len( self.ports ) 2456 print 'port_id %d' % port_id 2457 2458 return byte_stream 2459 2460 ########################################################################################### 2461 class Cpport ( object ): 2462 ########################################################################################### 2463 def __init__( self, 2464 direction, 2465 vspacename, 2466 mwmrname ): 2467 2468 self.index = 0 # global index ( set by addCpport() ) 2469 self.direction = direction # TO_COPROC / FROM_COPROC 2470 self.vspacename = vspacename # name of vspace containing mwmr channel 2471 self.mwmrname = mwmrname # name of vobj defining mwmr channel 2472 356 2473 return 357 2474 358 ######################## 359 class Spi( Peripheral ): 360 ######################## 361 def __init__( self, name, base, size ): 362 Peripheral.__init__( self, name, base, size, 'IOC', 'SPI' ) 363 return 364 365 ######################## 366 class Hba( Peripheral ): 367 ######################## 368 def __init__( self, name, base, size, channels ): 369 Peripheral.__init__( self, name, base, size, 'IOC', 'HBA', channels ) 370 return 371 372 ######################## 373 class Nic( Peripheral ): 374 ######################## 375 def __init__( self, name, base, size, channels ): 376 Peripheral.__init__( self, name, base, size, 'NIC', 'NONE', channels ) 377 return 378 379 ######################## 380 class Cma( Peripheral ): 381 ######################## 382 def __init__( self, name, base, size, channels ): 383 Peripheral.__init__( self, name, base, size, 'CMA', 'NONE', channels ) 384 return 385 386 ######################## 387 class Fbf( Peripheral ): 388 ######################## 389 def __init__( self, name, base, size ): 390 Peripheral.__init__( self, name, base, size, 'FBF', 'NONE' ) 391 return 392 393 ######################## 394 class Tim( Peripheral ): 395 ######################## 396 def __init__( self, name, base, size, channels ): 397 Peripheral.__init__( self, name, base, size, 'TIM', 'NONE', channels ) 398 return 399 400 ######################## 401 class Iob( Peripheral ): 402 ######################## 403 def __init__( self, name, base, size ): 404 Peripheral.__init__( self, name, base, size, 'IOB', 'NONE' ) 405 return 406 407 ######################## 408 class Rom( Peripheral ): 409 ######################## 410 def __init__( self, name, base, size ): 411 Peripheral.__init__( self, name, base, size, 'ROM', 'NONE' ) 412 return 413 414 ######################## 415 class Mmc( Peripheral ): 416 ######################## 417 def __init__( self, name, base, size ): 418 Peripheral.__init__( self, name, base, size, 'MMC', 'NONE' ) 419 return 420 421 ######################## 422 class Xcu( Peripheral ): 423 ######################## 424 def __init__( self, name, base, size, channels ): 425 Peripheral.__init__( self, name, base, size, 'XCU', 'NONE', channels ) 426 self.irqs = [] 427 return 428 429 def add ( self, irq ): 430 self.irqs.append( irq ) 431 return 432 433 ######################## 434 class Icu( Peripheral ): 435 ######################## 436 def __init__( self, name, base, size, channels ): 437 Peripheral.__init__( self, name, base, size, 'ICU', 'NONE', channels ) 438 self.irqs = [] 439 return 440 441 ###################### 442 def add ( self, irq ): 443 self.irqs.append( irq ) 444 return 445 446 ######################## 447 class Pic( Peripheral ): 448 ######################## 449 def __init__( self, name, base, size, channels ): 450 Peripheral.__init__( self, name, base, size, 'PIC', 'NONE', channels ) 451 self.irqs = [] 452 return 453 454 ###################### 455 def add ( self, irq ): 456 self.irqs.append( irq ) 457 return 458 459 ######################## 460 class XcuIrq ( object ): 461 ######################## 462 def __init__( self, srctype, srcid, isrtype, channel = 0, dstid = 0 ): 463 assert srctype in ['HWI','WTI','PTI'] 464 assert isrtype in ['ISR_DEFAULT','ISR_TICK','ISR_TTY_RX','ISR_TTY_TX', 465 'ISR_BDV', 'ISR_TIMER', 'ISR_WAKUP', 'ISR_NIC_RX', 466 'ISR_NIC_TX','ISR_CMA','ISR_MMC'] 467 assert srcid < 32 468 self.srctype = srctype 469 self.srcid = srcid 470 self.isrtype = isrtype 471 self.channel = channel 472 self.dstid = dstid 473 return 474 475 #################### 476 def __str__( self ): # xml for an xcuIrq 477 s = ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" dstid="%d" />\n' \ 478 % (self.srctype, self.srcid, self.isrtype, self.channel, self.dstid) 479 return s 480 481 ######################## 482 class PicIrq ( object ): 483 ######################## 484 def __init__( self, srcid, dstx, dsty, dstid ): 485 assert srcid < 32 486 self.srcid = srcid 487 self.dstx = dstx 488 self.dsty = dsty 489 self.dstid = dstid 490 return 491 492 #################### 493 def __str__( self ): # xml for a picIrq 494 s = ' <irq srcid="%d" dstx="%d" dsty="%d" dstid="%d" />\n' \ 495 % (self.srcid, self.dstx, self.dsty, self.dstid) 496 return s 2475 ################ 2476 def xml( self ): # xml for Cpport 2477 2478 print 'error in Cpport.xml() : not defined yet' 2479 sys.exit(1) 2480 2481 return 2482 2483 ############################################# 2484 def cbin( self, mapping, verbose, expected ): # C binary structure for Cpport 2485 2486 if ( verbose ): 2487 print '*** cbin for cpport[%d]' % (self.index) 2488 2489 # check index 2490 if ( self.index != expected ): 2491 print 'error in Cpport.cbin() : port global index = %d / expected = %d' \ 2492 % ( self.index, expected ) 2493 sys.exit(1) 2494 2495 # compute numerical value for direction 2496 if ( self.direction == 'TO_COPROC' ): 2497 dir_int = 0 2498 else: 2499 dir_int = 1 2500 2501 # compute vspace global index 2502 vspace_id = 0xFFFFFFFF 2503 for vspace in mapping.vspaces: 2504 if ( self.vspacename == vspace.name ): 2505 vspace_id = vspace.index 2506 if (vspace_id == 0xFFFFFFFF): 2507 print 'error in Cpport.cbin() : vspace name %s not found' \ 2508 % ( self.vspacename ) 2509 sys.exit(1) 2510 2511 # compute mwmr global index 2512 mwmr_id = 0xFFFFFFFF 2513 for vseg in mapping.vspace[vspace_id].vsegs: 2514 for vobj in vseg.vobjs: 2515 if (self.mwmrname == vobj.name): 2516 mwmr_id = vobj.index 2517 if (mwmr_id == 0xFFFFFFFF): 2518 print 'error in Cpport.cbin() : mwmr vobj name %s not found in vspace %s' \ 2519 % ( self.mwmrname, self.vspacename ) 2520 sys.exit(1) 2521 2522 byte_stream = bytearray() 2523 byte_stream += mapping.int2bytes( 4 , dir_int ) # pseg global index 2524 byte_stream += mapping.int2bytes( 4 , vspace_id ) # vspace global index 2525 byte_stream += mapping.int2bytes( 4 , mwmr_id ) # mwmr vobj global index 2526 2527 if ( verbose ): 2528 print 'direction = %s' % self.direction 2529 print 'vspace_id = %d' % vspace_id 2530 print 'mwmr_id = %d' % mwmr_id 2531 2532 return byte_stream 497 2533 498 2534
Note: See TracChangeset
for help on using the changeset viewer.