Index: soft/giet_vm/giet_python/mapping.py
===================================================================
--- soft/giet_vm/giet_python/mapping.py	(revision 327)
+++ soft/giet_vm/giet_python/mapping.py	(revision 328)
@@ -143,4 +143,5 @@
                   x_io = 0,                      # cluster_io x coordinate
                   y_io = 0,                      # cluster_io y coordinate
+                  peri_increment = 0x10000,      # address increment for globals
                   reset_address = 0xBFC00000 ):  # Processor wired boot_address
 
@@ -158,7 +159,6 @@
         self.x_io           = x_io
         self.y_io           = y_io
+        self.peri_increment = peri_increment
         self.reset_address  = reset_address
-
-        self.vseg_increment = 0x10000
 
         self.total_vspaces  = 0
@@ -344,9 +344,6 @@
                    pseg,                # destination pseg name
                    identity   = False,  # identity mapping required if true
-                   replicated = False,  # replicated in all clusters if true
                    binpath    = '' ):   # pathname for binary code
 
-        assert (identity and replicated) == False
-
         assert mode in VSEGMODES
 
@@ -357,36 +354,16 @@
         assert (x < self.x_size) and (y < self.y_size)
 
-        if ( replicated ):                  # replicated
-            for x_rep in xrange( self.x_size ):            
-                for y_rep in xrange( self.y_size ):            
-                    vbase_rep = vbase + (((x_rep << self.y_width) + y_rep) << 16)
-                    name_rep  = name + '_%d_%d' % ( x_rep , y_rep )
-  
-                    # add one vseg [x,y] into mapping
-                    vseg = Vseg( name_rep, vbase_rep, mode, x_rep, y_rep, pseg, identity )
-                    self.globs.append( vseg )
-                    self.total_globals += 1
-                    vseg.index = self.total_vsegs 
-                    self.total_vsegs += 1
+        # add one vseg into mapping
+        vseg = Vseg( name, vbase, mode, x, y, pseg, identity )
+        self.globs.append( vseg )
+        self.total_globals += 1
+        vseg.index = self.total_vsegs 
+        self.total_vsegs += 1
             
-                    # add one vobj [x,y] in the mapping
-                    vobj = Vobj( name_rep, size, vtype, binpath, 0, 0 )
-                    vseg.vobjs.append( vobj )
-                    vobj.index = self.total_vobjs
-                    self.total_vobjs += 1
-
-        else:                          # single vseg
-            # add one vseg into mapping
-            vseg = Vseg( name, vbase, mode, x, y, pseg, identity )
-            self.globs.append( vseg )
-            self.total_globals += 1
-            vseg.index = self.total_vsegs 
-            self.total_vsegs += 1
-            
-            # add one vobj into mapping
-            vobj = Vobj( name, size, vtype, binpath, 0, 0 )
-            vseg.vobjs.append( vobj )
-            vobj.index = self.total_vobjs
-            self.total_vobjs += 1
+        # add one vobj into mapping
+        vobj = Vobj( name, size, vtype, binpath, 0, 0 )
+        vseg.vobjs.append( vobj )
+        vobj.index = self.total_vobjs
+        self.total_vobjs += 1
 
         return
@@ -825,4 +802,5 @@
         nb_fbf       = 0
         fbf_channels = 0
+        fbf_arg      = 0
         seg_fbf_base = 0xFFFFFFFF
         seg_fbf_size = 0
@@ -885,4 +863,5 @@
         nb_xcu       = 0
         xcu_channels = 0
+        xcu_arg      = 0
         seg_xcu_base = 0xFFFFFFFF
         seg_xcu_size = 0
@@ -911,4 +890,5 @@
                     seg_fbf_size = periph.pseg.size
                     fbf_channels = periph.channels
+                    fbf_arg      = periph.arg
                     nb_fbf +=1
 
@@ -986,4 +966,5 @@
                     seg_xcu_size = periph.pseg.size
                     xcu_channels = periph.channels
+                    xcu_arg      = periph.arg
                     nb_xcu +=1
     
@@ -1048,5 +1029,5 @@
                 boot_stack_found        = True
 
-        # check all BOOT vsegs are found and identity mapping
+        # check that BOOT vsegs are found and identity mapping
         if ( (boot_mapping_found == False) or (boot_mapping_ident == False) ):
              print 'error in hard_config() : seg_boot_mapping missing or not ident'
@@ -1126,4 +1107,9 @@
         s += '#define USE_RAMDISK            %d\n'    % self.use_ramdisk
         s += '\n'
+        s += '#define FBUF_X_SIZE            %d\n'    % fbf_arg
+        s += '#define FBUF_Y_SIZE            %d\n'    % fbf_arg
+        s += '\n'
+        s += '#define XCU_NB_INPUTS          %d\n'    % xcu_arg
+        s += '\n'
 
         s += '/* physical base addresses for peripherals */\n'
@@ -1177,5 +1163,5 @@
         s += '#define SEG_RDK_SIZE           0x%x\n'  % seg_rdk_size
         s += '\n'
-        s += '#define VSEG_CLUSTER_INCREMENT 0x%x\n'  % self.vseg_increment
+        s += '#define PERI_CLUSTER_INCREMENT 0x%x\n'  % self.peri_increment
         s += '\n'
 
