Changeset 356 for soft/giet_vm/giet_python

Timestamp:

Jul 3, 2014, 4:50:55 PM (10 years ago)

Author:

alain

Message:

Bloup...

File:

• soft/giet_vm/giet_python/mapping.py (modified) (5 diffs)

soft/giet_vm/giet_python/mapping.py

@@ -144 +144 @@
                   y_io = 0,                      # cluster_io y coordinate
                   peri_increment = 0x10000,      # address increment for globals
-                  reset_address = 0xBFC00000 ):  # Processor wired boot_address
+                  reset_address  = 0xBFC00000,   # Processor wired boot_address
+                  ram_base       = 0,            # RAM physical base address in cluster[0,0]
+                  ram_size       = 0 ):          # RAM size in each cluster (bytes)
 
         self.signature      = 0xDACE2014
@@ -161 +163 @@
         self.peri_increment = peri_increment
         self.reset_address  = reset_address
+        self.ram_base       = ram_base
+        self.ram_size       = ram_size
+
 
         self.total_vspaces  = 0
@@ -193 +198 @@
        
         # check coordinates (obtained from the base address)
-        cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
+        paddr_lsb_width = self.paddr_width - self.x_width - self.y_width
+        cluster_xy = base >> paddr_lsb_width
         x = cluster_xy >> (self.y_width);
         y = cluster_xy & ((1 << self.y_width) - 1) 
@@ -201 +207 @@
         assert (x < self.x_size) and (y < self.y_size)
         
+        assert ( (base & ((1<<paddr_lsb_width)-1)) == self.ram_base )
+
+        assert ( size == self.ram_size )
+
         cluster_id = (x * self.y_size) + y
 
@@ -1118 +1128 @@
         s += '\n'
 
-        s += '/* physical base addresses for peripherals */\n'
+        s += '/* base addresses and sizes for physical segments */\n'
+        s += '\n'
+        s += '#define SEG_RAM_BASE           0x%x\n'  % self.ram_base            
+        s += '#define SEG_RAM_SIZE           0x%x\n'  % self.ram_size            
         s += '\n'
         s += '#define SEG_CMA_BASE           0x%x\n'  % seg_cma_base