Changeset 427 for soft/giet_vm
- Timestamp:
- Oct 4, 2014, 3:18:01 PM (10 years ago)
- Location:
- soft/giet_vm/giet_boot
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
soft/giet_vm/giet_boot/boot.c
r412 r427 274 274 unsigned int ppn ) // 28 bits right-justified 275 275 { 276 // compute index in PT1277 unsigned int ix1 = vpn >> 9; // 11 bits for ix1278 279 // get page table physical base address280 paddr_t pt1_pbase = _ptabs_paddr[vspace_id][x][y];281 282 // check pt1_base283 if ( pt1_pbase == 0 )284 {285 _puts("\n[BOOT ERROR] in boot_add_pte1() : illegal pbase address for PTAB[");286 _putd( vspace_id );287 _puts(",");288 _putd( x );289 _puts(",");290 _putd( y );291 _puts("]\n");292 _exit();293 }294 295 // compute pte1 : 2 bits V T / 8 bits flags / 3 bits RSVD / 19 bits bppi296 unsigned int pte1 = PTE_V |297 (flags & 0x3FC00000) |298 ((ppn>>9) & 0x0007FFFF);299 300 // write pte1 in PT1301 _physical_write( pt1_pbase + 4*ix1, pte1 );302 276 303 277 #if (BOOT_DEBUG_PT > 1) … … 310 284 _puts("] : vpn = "); 311 285 _putx( vpn ); 286 #endif 287 288 // compute index in PT1 289 unsigned int ix1 = vpn >> 9; // 11 bits for ix1 290 291 // get page table physical base address 292 paddr_t pt1_pbase = _ptabs_paddr[vspace_id][x][y]; 293 294 // check pt1_base 295 if ( pt1_pbase == 0 ) 296 { 297 _puts("\n[BOOT ERROR] in boot_add_pte1() : illegal pbase address for PTAB["); 298 _putd( vspace_id ); 299 _puts(","); 300 _putd( x ); 301 _puts(","); 302 _putd( y ); 303 _puts("]\n"); 304 _exit(); 305 } 306 307 // compute pte1 : 2 bits V T / 8 bits flags / 3 bits RSVD / 19 bits bppi 308 unsigned int pte1 = PTE_V | 309 (flags & 0x3FC00000) | 310 ((ppn>>9) & 0x0007FFFF); 311 312 // write pte1 in PT1 313 _physical_write( pt1_pbase + 4*ix1, pte1 ); 314 315 #if (BOOT_DEBUG_PT > 1) 312 316 _puts(" / ppn = "); 313 317 _putx( ppn ); … … 333 337 unsigned int ppn ) // 28 bits right-justified 334 338 { 339 340 #if (BOOT_DEBUG_PT > 1) 341 _puts(" - PTE2 in PTAB["); 342 _putd( vspace_id ); 343 _puts(","); 344 _putd( x ); 345 _puts(","); 346 _putd( y ); 347 _puts("] : vpn = "); 348 _putx( vpn ); 349 #endif 350 335 351 unsigned int ix1; 336 352 unsigned int ix2; … … 394 410 395 411 #if (BOOT_DEBUG_PT > 1) 396 _puts(" - PTE2 in PTAB[");397 _putd( vspace_id );398 _puts(",");399 _putd( x );400 _puts(",");401 _putd( y );402 _puts("] : vpn = ");403 _putx( vpn );404 412 _puts(" / ppn = "); 405 413 _putx( ppn ); … … 456 464 // 457 465 ///////////////////////////////////////////////////////////////////////////////////// 458 void boot_vseg_map( mapping_vseg_t* vseg ) 466 void boot_vseg_map( mapping_vseg_t* vseg, 467 unsigned int vspace_id ) 459 468 { 460 469 mapping_header_t* header = (mapping_header_t *)SEG_BOOT_MAPPING_BASE; … … 484 493 if ( vobj[vobj_id].type == VOBJ_TYPE_PTAB ) is_ptab = 1; 485 494 else is_ptab = 0; 495 496 // compute actual vspace index 497 unsigned int vsid; 498 if ( vspace_id == 0xFFFFFFFF ) vsid = 0; 499 else vsid = vspace_id; 486 500 487 501 //////////// First step : compute vseg length and vobj(s) vbase … … 549 563 { 550 564 unsigned int ix1 = vpn >> 9; // 11 bits 551 paddr_t paddr = _ptabs_paddr[ 0][x_dest][y_dest] + (ix1<<2);565 paddr_t paddr = _ptabs_paddr[vsid][x_dest][y_dest] + (ix1<<2); 552 566 unsigned int pte1 = _physical_read( paddr ); 553 567 if ( (pte1 & PTE_V) == 0 ) // BPP not allocated yet … … 580 594 //////////// by dividing the vseg in several sub-segments. 581 595 //////////// - register it in _ptabs_vaddr & _ptabs_paddr arrays, 582 //////////// and initialize the max_pt2 and next_pt2 allocators. 596 //////////// and initialize next_pt2 allocators. 597 //////////// - reset all entries in first level page tables 583 598 584 599 if ( is_ptab ) … … 593 608 594 609 // each PTAB must be aligned on a 8 Kbytes boundary 595 nsp = ( vseg->length <<12 ) / nspaces;610 nsp = ( vseg->length >> 12 ) / nspaces; 596 611 if ( (nsp & 0x1) == 0x1 ) nsp = nsp - 1; 597 612 … … 601 616 for ( vs = 0 ; vs < nspaces ; vs++ ) 602 617 { 603 offset += nsp;604 618 _ptabs_vaddr [vs][x_dest][y_dest] = (vpn + offset) << 12; 605 619 _ptabs_paddr [vs][x_dest][y_dest] = ((paddr_t)(ppn + offset)) << 12; 606 620 _ptabs_next_pt2[vs][x_dest][y_dest] = 0; 621 offset += nsp; 622 /* 623 // reset all entries in PT1 (8 Kbytes) 624 _physical_memset( _ptabs_paddr[vs][x_dest][y_dest], PT1_SIZE, 0 ); 625 626 */ 607 627 } 608 628 } … … 637 657 // - PTEs are replicated in all clusters for a non local vseg. 638 658 ///////////////////////////////////////////////////////////////////////////////////// 639 void boot_vseg_pte _init( mapping_vseg_t* vseg,640 659 void boot_vseg_pte( mapping_vseg_t* vseg, 660 unsigned int vspace_id ) 641 661 { 642 662 // compute the "global" vseg attribute and actual vspace index … … 802 822 } 803 823 } // end for pages 804 } // end boot_vseg_pte _init()824 } // end boot_vseg_pte() 805 825 806 826 /////////////////////////////////////////////////////////////////////////////// … … 818 838 // _ptabs_vaddr and _ptabs_paddr arrays if the vseg is a PTAB. 819 839 // 820 // B) page table initialisation : the boot_vseg_pte _init() function initialise840 // B) page table initialisation : the boot_vseg_pte() function initialise 821 841 // the PTEs (both PTE1 and PTE2) in one or several page tables: 822 842 // - PTEs are replicated in all vspaces for a global vseg. … … 858 878 if ( (vobj[vobj_id].type == VOBJ_TYPE_PTAB) ) 859 879 { 860 boot_vseg_map( &vseg[vseg_id] );880 boot_vseg_map( &vseg[vseg_id], 0xFFFFFFFF ); 861 881 vseg[vseg_id].mapped = 1; 862 882 } … … 868 888 if ( (vobj[vobj_id].type == VOBJ_TYPE_PTAB) ) 869 889 { 870 boot_vseg_pte _init( &vseg[vseg_id], 0xFFFFFFFF );890 boot_vseg_pte( &vseg[vseg_id], 0xFFFFFFFF ); 871 891 vseg[vseg_id].mapped = 1; 872 892 } … … 885 905 (vseg[vseg_id].mapped == 0) ) 886 906 { 887 boot_vseg_map( &vseg[vseg_id] );907 boot_vseg_map( &vseg[vseg_id], 0xFFFFFFFF ); 888 908 vseg[vseg_id].mapped = 1; 889 boot_vseg_pte _init( &vseg[vseg_id], 0xFFFFFFFF );909 boot_vseg_pte( &vseg[vseg_id], 0xFFFFFFFF ); 890 910 } 891 911 } … … 901 921 if ( vseg[vseg_id].mapped == 0 ) 902 922 { 903 boot_vseg_map( &vseg[vseg_id] );923 boot_vseg_map( &vseg[vseg_id], 0xFFFFFFFF ); 904 924 vseg[vseg_id].mapped = 1; 905 boot_vseg_pte _init( &vseg[vseg_id], 0xFFFFFFFF );925 boot_vseg_pte( &vseg[vseg_id], 0xFFFFFFFF ); 906 926 } 907 927 } … … 922 942 vseg_id++) 923 943 { 924 boot_vseg_map( &vseg[vseg_id] );944 boot_vseg_map( &vseg[vseg_id], vspace_id ); 925 945 vseg[vseg_id].mapped = 1; 926 boot_vseg_pte _init( &vseg[vseg_id], vspace_id );946 boot_vseg_pte( &vseg[vseg_id], vspace_id ); 927 947 } 928 948 } … … 1602 1622 #endif 1603 1623 // compute gpid (global processor index) and scheduler base address 1604 unsigned int gpid = cluster_xy * NB_PROCS_MAX+ lpid;1624 unsigned int gpid = (cluster_xy << P_WIDTH) + lpid; 1605 1625 psched = _schedulers[x][y][lpid]; 1606 1626 … … 2545 2565 /////////////////////////////////////////////////////////////////////////////// 2546 2566 2567 // all processor initialise the SCHED register 2568 // from the _schedulers[x][y][lpid array] 2569 unsigned int cluster_xy = gpid >> P_WIDTH; 2570 unsigned int lpid = gpid & ((1<<P_WIDTH)-1); 2571 unsigned int x = cluster_xy >> Y_WIDTH; 2572 unsigned int y = cluster_xy & ((1<<Y_WIDTH)-1); 2573 _set_sched( (unsigned int)_schedulers[x][y][lpid] ); 2574 2575 // all processors (but Proc[0,0,0]) activate MMU 2576 if ( gpid != 0 ) 2577 { 2578 _set_mmu_ptpr( (unsigned int)(_ptabs_paddr[0][x][y]>>13) ); 2579 _set_mmu_mode( 0xF ); 2580 } 2581 2547 2582 // all processors reset BEV bit in the status register to use 2548 2583 // the GIET_VM exception handler instead of the PRELOADER exception handler 2549 2584 _set_sr( 0 ); 2550 2551 // all processor initialise the SCHED register2552 // from the _schedulers[x][y][lpid array]2553 unsigned int cluster_xy = gpid / NB_PROCS_MAX;2554 unsigned int lpid = gpid % NB_PROCS_MAX;2555 unsigned int x = cluster_xy >> Y_WIDTH;2556 unsigned int y = cluster_xy & ((1<<Y_WIDTH)-1);2557 _set_sched( (unsigned int)_schedulers[x][y][lpid] );2558 2559 // all processors (but Proc[0,0,0]) activate MMU2560 if ( gpid != 0 )2561 {2562 _set_mmu_ptpr( (unsigned int)(_ptabs_paddr[0][x][y]>>13) );2563 _set_mmu_mode( 0xF );2564 }2565 2585 2566 2586 // all processors jump to kernel_init -
soft/giet_vm/giet_boot/boot_entry.S
r366 r427 46 46 47 47 mfc0 k0, CP0_PROCID 48 andi k0, k0, 0x3FF /* k0 <= proc_xyl */ 49 la t7, NB_PROCS_MAX /* t7 <= NBPROCS */ 50 divu k0, t7 51 mfhi t1 /* t1 <= lpid */ 52 mflo t2 /* t2 <= cluster_xy */ 53 srl t3, t2, 4 /* t3 <= x coordinate */ 54 andi t4, t2, 0xF /* t4 <= y coordinate */ 55 la t6, Y_SIZE /* t6 <= Y_SIZE */ 48 andi k0, k0, 0xFFF /* k0 <= proc_xyl */ 49 andi t1, k0, ((1<<P_WIDTH)-1) /* t1 <= lpid */ 50 srl t2, k0, P_WIDTH /* t2 <= cluster_xy */ 51 srl t3, t2, Y_WIDTH /* t3 <= x coordinate */ 52 andi t4, t2, ((1<<Y_WIDTH)-1) /* t4 <= y coordinate */ 53 la t6, Y_SIZE /* t6 <= Y_SIZE */ 56 54 multu t3, t6 57 55 mflo t5 58 addu t5, t5, t4 /* t5 <= cluster_id */ 56 addu t5, t5, t4 /* t5 <= cluster_id */ 57 li t7, NB_PROCS_MAX 59 58 multu t5, t7 60 59 mflo t0 61 addu t0, t0, t1 /* t0 <= proc_id*/60 addu t0, t0, t1 /* t0 <= proc_id */ 62 61 63 62
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