Changeset 560 for soft

Timestamp:

Apr 13, 2015, 5:34:00 PM (10 years ago)

Author:

alain

Message:

Introducing support for MWR coprocessors in the hard_config.h file

File:

• soft/giet_vm/giet_python/mapping.py (modified) (9 diffs)

soft/giet_vm/giet_python/mapping.py

@@ -75 +75 @@
                   'GCD',
                   'DCT',
+                  'CPY',
                  ]
    
@@ -723 +724 @@
         seg_ioc_base = 0xFFFFFFFF
         seg_ioc_size = 0
+        use_ioc_bdv  = False
+        use_ioc_sdc  = False
+        use_ioc_hba  = False
 
         nb_mmc       = 0
@@ -737 +741 @@
         mwr_arg2     = 0
         mwr_arg3     = 0
+        use_mwr_gcd  = False
+        use_mwr_dct  = False
+        use_mwr_cpy  = False
 
         nb_nic       = 0
@@ -778 +785 @@
         seg_drom_base = 0xFFFFFFFF
         seg_drom_size = 0
-
-        use_bdv = False
-        use_sdc = False
-        use_hba = False
 
         # get peripherals attributes
@@ -817 +820 @@
                     ioc_channels = periph.channels
                     nb_ioc += 1
-
-                    if self.use_ramdisk: continue
-
-                    if   ( periph.subtype == 'BDV' ): use_bdv = True
-                    elif ( periph.subtype == 'HBA' ): use_hba = True
-                    elif ( periph.subtype == 'SDC' ): use_sdc = True
+                    if ( periph.subtype == 'BDV' ): use_ioc_bdv = True
+                    if ( periph.subtype == 'HBA' ): use_ioc_hba = True
+                    if ( periph.subtype == 'SDC' ): use_ioc_sdc = True
 
                 elif ( periph.ptype == 'MMC' ):
@@ -839 +839 @@
                     mwr_arg3     = periph.arg3
                     nb_mwr +=1
+                    if ( periph.subtype == 'GCD' ): use_mwr_gcd = True
+                    if ( periph.subtype == 'DCT' ): use_mwr_dct = True
+                    if ( periph.subtype == 'CPY' ): use_mwr_cpy = True
 
                 elif ( periph.ptype == 'ROM' ):
@@ -901 +904 @@
 
         # one and only one type of IOC controller
-        nb_iocs = 0
-        if use_hba         : nb_iocs += 1
-        if use_bdv         : nb_iocs += 1
-        if use_sdc         : nb_iocs += 1
-        if self.use_ramdisk: nb_iocs += 1
-        assert ( nb_iocs == 1 )
+        nb_ioc_types = 0
+        if use_ioc_hba:       nb_ioc_types += 1
+        if use_ioc_bdv:       nb_ioc_types += 1
+        if use_ioc_sdc:       nb_ioc_types += 1
+        if self.use_ramdisk:  nb_ioc_types += 1
+        assert ( nb_ioc_types == 1 )
+
+        # one and only one type of MWR controller
+        nb_mwr_types = 0
+        if use_mwr_gcd:       nb_mwr_types += 1
+        if use_mwr_dct:       nb_mwr_types += 1
+        if use_mwr_cpy:       nb_mwr_types += 1
+        if ( nb_mwr > 0 ) : assert ( nb_mwr_types == 1 )
 
         # Compute total number of processors
@@ -1012 +1022 @@
         s += '\n'
         s += '#define USE_XCU                %d\n'    % ( nb_xcu != 0 )
+        s += '#define USE_DMA                %d\n'    % ( nb_dma != 0 )
+        s += '\n'
         s += '#define USE_IOB                %d\n'    % ( nb_iob != 0 )
         s += '#define USE_PIC                %d\n'    % ( nb_pic != 0 )
@@ -1017 +1029 @@
         s += '#define USE_NIC                %d\n'    % ( nb_nic != 0 )
         s += '\n'
-        s += '#define USE_IOC_BDV            %d\n'    % use_bdv
-        s += '#define USE_IOC_SDC            %d\n'    % use_sdc
-        s += '#define USE_IOC_HBA            %d\n'    % use_hba
+        s += '#define USE_IOC_BDV            %d\n'    % use_ioc_bdv
+        s += '#define USE_IOC_SDC            %d\n'    % use_ioc_sdc
+        s += '#define USE_IOC_HBA            %d\n'    % use_ioc_hba
         s += '#define USE_IOC_RDK            %d\n'    % self.use_ramdisk
+        s += '\n'
+        s += '#define USE_MWR_GCD            %d\n'    % use_mwr_gcd
+        s += '#define USE_MWR_DCT            %d\n'    % use_mwr_dct
+        s += '#define USE_MWR_CPY            %d\n'    % use_mwr_cpy
         s += '\n'
         s += '#define FBUF_X_SIZE            %d\n'    % fbf_arg0