Index: soft/giet_vm/giet_boot/boot.c =================================================================== --- soft/giet_vm/giet_boot/boot.c (revision 756) +++ soft/giet_vm/giet_boot/boot.c (revision 757) @@ -133,9 +133,9 @@ // Temporaty buffer used to load one complete .elf file __attribute__((section(".kdata"))) -unsigned char _boot_elf_buffer[GIET_ELF_BUFFER_SIZE] __attribute__((aligned(64))); +unsigned char _boot_elf_buffer[GIET_ELF_BUFFER_SIZE] __attribute__((aligned(64))); // Physical memory allocators array (one per cluster) __attribute__((section(".kdata"))) -pmem_alloc_t boot_pmem_alloc[X_SIZE][Y_SIZE]; +pmem_alloc_t _boot_pmem_alloc[X_SIZE][Y_SIZE]; // Schedulers virtual base addresses array (one per processor) @@ -149,5 +149,5 @@ // Page tables physical base addresses (one per vspace and per cluster) __attribute__((section(".kdata"))) -paddr_t _ptabs_paddr[GIET_NB_VSPACE_MAX][X_SIZE][Y_SIZE]; +unsigned long long _ptabs_paddr[GIET_NB_VSPACE_MAX][X_SIZE][Y_SIZE]; // Page tables pt2 allocators (one per vspace and per cluster) @@ -191,146 +191,4 @@ extern void boot_entry(); - -////////////////////////////////////////////////////////////////////////////// -// This function registers a new PTE1 in the page table defined -// by the vspace_id argument, and the (x,y) coordinates. -// It updates only the first level PT1. -// As each vseg is mapped by a different processor, the PT1 entry cannot -// be concurrently accessed, and we don't need to take any lock. -// -// Implementation note: -// This function checks that the PT1 entry is not already mapped, -// to enforce the rule: only one vseg in a given BPP. -// The 4 vsegs used by the boot code being packed in one single BPP, -// this verif is not done for all identity mapping vsegs. -////////////////////////////////////////////////////////////////////////////// -void boot_add_pte1( unsigned int vspace_id, - unsigned int x, - unsigned int y, - unsigned int vpn, // 20 bits right-justified - unsigned int flags, // 10 bits left-justified - unsigned int ppn, // 28 bits right-justified - unsigned int ident ) // identity mapping if non zero -{ - unsigned int pte1; // PTE1 value - paddr_t paddr; // PTE1 physical address - - // compute index in PT1 - unsigned int ix1 = vpn >> 9; // 11 bits for ix1 - - // get PT1 physical base address - paddr_t pt1_base = _ptabs_paddr[vspace_id][x][y]; - - if ( pt1_base == 0 ) - { - _printf("\n[BOOT ERROR] in boot_add_pte1() : no PTAB in cluster[%d,%d]" - " containing processors\n", x , y ); - _exit(); - } - - // compute pte1 physical address - paddr = pt1_base + 4*ix1; - - // check PTE1 not already mapped - if ( ident == 0 ) - { - if ( _physical_read( paddr ) & PTE_V ) - { - _printf("\n[BOOT ERROR] in boot_add_pte1() : vpn %x already mapped " - "in PTAB[%d,%d] for vspace %d\n", vpn , x , y , vspace_id ); - _exit(); - } - } - - // compute pte1 : 2 bits V T / 8 bits flags / 3 bits RSVD / 19 bits bppi - pte1 = PTE_V | (flags & 0x3FC00000) | ((ppn>>9) & 0x0007FFFF); - - // write pte1 in PT1 - _physical_write( paddr , pte1 ); - - asm volatile ("sync"); - -} // end boot_add_pte1() - -////////////////////////////////////////////////////////////////////////////// -// This function registers a new PTE2 in the page table defined -// by the vspace_id argument, and the (x,y) coordinates. -// It updates both the first level PT1 and the second level PT2. -// As the set of PT2s is implemented as a fixed size array (no dynamic -// allocation), this function checks a possible overflow of the PT2 array. -// As a given entry in PT1 can be shared by several vsegs, mapped by -// different processors, we need to take the lock protecting PTAB[v][x][y]. -////////////////////////////////////////////////////////////////////////////// -void boot_add_pte2( unsigned int vspace_id, - unsigned int x, - unsigned int y, - unsigned int vpn, // 20 bits right-justified - unsigned int flags, // 10 bits left-justified - unsigned int ppn, // 28 bits right-justified - unsigned int ident ) // identity mapping if non zero -{ - unsigned int ix1; - unsigned int ix2; - paddr_t pt2_pbase; // PT2 physical base address - paddr_t pte2_paddr; // PTE2 physical address - unsigned int pt2_id; // PT2 index - unsigned int ptd; // PTD : entry in PT1 - - ix1 = vpn >> 9; // 11 bits for ix1 - ix2 = vpn & 0x1FF; // 9 bits for ix2 - - // get page table physical base address - paddr_t pt1_pbase = _ptabs_paddr[vspace_id][x][y]; - - if ( pt1_pbase == 0 ) - { - _printf("\n[BOOT ERROR] in boot_add_pte2() : no PTAB for vspace %d " - "in cluster[%d,%d]\n", vspace_id , x , y ); - _exit(); - } - - // get lock protecting PTAB[vspace_id][x][y] - _spin_lock_acquire( &_ptabs_spin_lock[vspace_id][x][y] ); - - // get ptd in PT1 - ptd = _physical_read( pt1_pbase + 4 * ix1 ); - - if ((ptd & PTE_V) == 0) // undefined PTD: compute PT2 base address, - // and set a new PTD in PT1 - { - // get a new pt2_id - pt2_id = _ptabs_next_pt2[vspace_id][x][y]; - _ptabs_next_pt2[vspace_id][x][y] = pt2_id + 1; - - // check overflow - if (pt2_id == _ptabs_max_pt2) - { - _printf("\n[BOOT ERROR] in boot_add_pte2() : PTAB[%d,%d,%d]" - " contains not enough PT2s\n", vspace_id, x, y ); - _exit(); - } - - pt2_pbase = pt1_pbase + PT1_SIZE + PT2_SIZE * pt2_id; - ptd = PTE_V | PTE_T | (unsigned int) (pt2_pbase >> 12); - - // set PTD into PT1 - _physical_write( pt1_pbase + 4*ix1, ptd); - } - else // valid PTD: compute PT2 base address - { - pt2_pbase = ((paddr_t)(ptd & 0x0FFFFFFF)) << 12; - } - - // set PTE in PT2 : flags & PPN in two 32 bits words - pte2_paddr = pt2_pbase + 8 * ix2; - _physical_write(pte2_paddr , (PTE_V | flags) ); - _physical_write(pte2_paddr + 4 , ppn ); - - // release lock protecting PTAB[vspace_id][x][y] - _spin_lock_release( &_ptabs_spin_lock[vspace_id][x][y] ); - - asm volatile ("sync"); - -} // end boot_add_pte2() //////////////////////////////////////////////////////////////////////////////////// @@ -442,5 +300,5 @@ { // compute pointer on physical memory allocator in dest cluster - pmem_alloc_t* palloc = &boot_pmem_alloc[x_dest][y_dest]; + pmem_alloc_t* palloc = &_boot_pmem_alloc[x_dest][y_dest]; if ( big == 0 ) // allocate contiguous SPPs @@ -480,10 +338,11 @@ offset = 0; - // each PTAB must be aligned on a 8 Kbytes boundary + // compute max_pt2: each PTAB must be aligned on a 8 Kbytes boundary nsp = ( vseg->length >> 12 ) / nspaces; if ( (nsp & 0x1) == 0x1 ) nsp = nsp - 1; - - // compute max_pt2 _ptabs_max_pt2 = ((nsp<<12) - PT1_SIZE) / PT2_SIZE; + + // save max_pt2 in header + header->max_pt2 = _ptabs_max_pt2; for ( vs = 0 ; vs < nspaces ; vs++ ) @@ -586,5 +445,5 @@ if ( big ) // big pages => PTE1s { - boot_add_pte1( vsid, + _v2p_add_pte1( vsid, x_dest, y_dest, @@ -596,5 +455,5 @@ else // small pages => PTE2s { - boot_add_pte2( vsid, + _v2p_add_pte2( vsid, x_dest, y_dest, @@ -615,5 +474,5 @@ if ( big ) // big pages => PTE1s { - boot_add_pte1( vsid, + _v2p_add_pte1( vsid, x, y, @@ -625,5 +484,5 @@ else // small pages => PTE2s { - boot_add_pte2( vsid, + _v2p_add_pte2( vsid, x, y, @@ -643,5 +502,5 @@ if ( big ) // big pages => PTE1s { - boot_add_pte1( v, + _v2p_add_pte1( v, x_dest, y_dest, @@ -653,5 +512,5 @@ else // small pages = PTE2s { - boot_add_pte2( v, + _v2p_add_pte2( v, x_dest, y_dest, @@ -675,5 +534,5 @@ if ( big ) // big pages => PTE1s { - boot_add_pte1( v, + _v2p_add_pte1( v, x, y, @@ -685,5 +544,5 @@ else // small pages -> PTE2s { - boot_add_pte2( v, + _v2p_add_pte2( v, x, y, @@ -830,10 +689,18 @@ vseg_id++) { - pseg = _get_pseg_base(header) + vseg[vseg_id].psegid; - cluster = _get_cluster_base(header) + pseg->clusterid; - if ( (cluster->x == cx) && (cluster->y == cy) ) - { - boot_vseg_map( &vseg[vseg_id], vspace_id ); - boot_vseg_pte( &vseg[vseg_id], vspace_id ); + if ( vseg[vseg_id].type == VSEG_TYPE_MMAP ) // no static mapping + { + // psegid used as page allocator in MMAP vseg + vseg[vseg_id].psegid = 0; + } + else // static mapping + { + pseg = _get_pseg_base(header) + vseg[vseg_id].psegid; + cluster = _get_cluster_base(header) + pseg->clusterid; + if ( (cluster->x == cx) && (cluster->y == cy) ) + { + boot_vseg_map( &vseg[vseg_id], vspace_id ); + boot_vseg_pte( &vseg[vseg_id], vspace_id ); + } } } @@ -1074,4 +941,5 @@ psched->context[IDLE_THREAD_INDEX].slot[CTX_PTPR_ID] = _ptabs_paddr[0][x][y]>>13; psched->context[IDLE_THREAD_INDEX].slot[CTX_PTAB_ID] = _ptabs_vaddr[0][x][y]; + psched->context[IDLE_THREAD_INDEX].slot[CTX_NPT2_ID] = _ptabs_next_pt2[0][x][y]; psched->context[IDLE_THREAD_INDEX].slot[CTX_TTY_ID] = 0; psched->context[IDLE_THREAD_INDEX].slot[CTX_LTID_ID] = IDLE_THREAD_INDEX; @@ -1245,4 +1113,7 @@ unsigned int ctx_ptab = _ptabs_vaddr[vspace_id][req_x][req_y]; + // ctx_npt2 : page_table PT2 allocator + unsigned int ctx_npt2 = _ptabs_next_pt2[vspace_id][req_x][req_y]; + // ctx_entry : Get the virtual address of the memory location containing // the thread entry point : the start_vector is stored by GCC in the @@ -1282,4 +1153,5 @@ psched->context[ltid].slot[CTX_PTPR_ID] = ctx_ptpr; psched->context[ltid].slot[CTX_PTAB_ID] = ctx_ptab; + psched->context[ltid].slot[CTX_NPT2_ID] = ctx_npt2; psched->context[ltid].slot[CTX_LTID_ID] = ltid; psched->context[ltid].slot[CTX_TRDID_ID] = ctx_trdid; @@ -1310,4 +1182,5 @@ " - ctx[PTPR] = %x\n" " - ctx[PTAB] = %x\n" + " - ctx[NPT2] = %x\n" " - ctx[VSID] = %d\n" " - ctx[NORUN] = %x\n" @@ -1323,4 +1196,5 @@ psched->context[ltid].slot[CTX_PTPR_ID], psched->context[ltid].slot[CTX_PTAB_ID], + psched->context[ltid].slot[CTX_NPT2_ID], psched->context[ltid].slot[CTX_VSID_ID], psched->context[ltid].slot[CTX_NORUN_ID], @@ -1758,4 +1632,5 @@ unsigned int pseg_min = cluster[cluster_id].pseg_offset; unsigned int pseg_max = pseg_min + cluster[cluster_id].psegs; + for ( pseg_id = pseg_min ; pseg_id < pseg_max ; pseg_id++ ) { @@ -1831,5 +1706,5 @@ mapping_cluster_t* cluster = _get_cluster_base(header); - _printf("\n[BOOT] Mapping %s loaded at cycle %d\n", + _printf("\n[BOOT] Mapping %s at cycle %d\n", header->name , _get_proctime() );