58 | | .1 : each processor get its scheduler virtual address from CP0_SCHED register and contributes to _schedulers[] array initialisation. |
59 | | .2 : each processor loops on all allocated tasks to build the _ptabs_vaddr[] & _ptabs_ptprs[] arrays from the tasks contexts. |
60 | | .3 : each processor computes and set the XCU masks, as specified in the HWI, PTI, and WTI interrupt vectors. |
61 | | .4 : each processor starts its TICK timer if it has at least at least one task allocated. |
62 | | .5 : each processor updates the idle_task context (CTX_SP, CTX_RA, CTX_EPC). |
63 | | .6 : when all processors reach the synchronisation barrier, each processor set registers SP, SR, PTPR, EPC, with the values corresponding to the first allocated task, and jump to user code. |
| 58 | 1. each processor get its scheduler virtual address from CP0_SCHED register and contributes to _schedulers[] array initialisation. |
| 59 | 2. each processor loops on all allocated tasks to build the _ptabs_vaddr[] & _ptabs_ptprs[] arrays from the tasks contexts. |
| 60 | 3. each processor computes and set the XCU masks, as specified in the HWI, PTI, and WTI interrupt vectors. |
| 61 | 4. each processor starts its TICK timer if it has at least at least one task allocated. |
| 62 | 5. each processor updates the idle_task context (CTX_SP, CTX_RA, CTX_EPC). |
| 63 | 6. when all processors reach the synchronisation barrier, each processor set registers SP, SR, PTPR, EPC, with the values corresponding to the first allocated task, and jump to user code. |