Changes between Version 18 and Version 19 of boot_loader


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Timestamp:
Feb 5, 2015, 10:33:23 AM (10 years ago)
Author:
alain
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  • boot_loader

    v18 v19  
    55The boot procedure is done in three phases:
    66 * The generic ''reset'' code (hard-coded in the external ROM) is executed by processor (0,0,0), and load the GIET_VM boot-loader code, stored in the ''boot.elf'' file, from the external disk to the physical memory.
    7  * The GIET_VM boot-loader is executed in parallel by all processors (x,y,0). It load the ''map.bin'' file, build the page tables, initializes the schedulers as specified in the mapping, initializes the peripherals, and load the kernel code, as well as the user application(s) code into memory.
     7 * The GIET_VM boot-loader is executed in parallel by all processors P(x,y,0): one processor per cluster. It loads the ''map.bin'' file, build the page tables, initializes the schedulers as specified in the mapping, initializes the peripherals, and load the kernel code, as well as the user application(s) code into memory.
    88 * Finally, the GIET_VM ''kernel_init()'' function is executed by all processors, and completes the kernel initialization.
    99
    … …  
    1616== Phase 2 : Boot Initialisation ==
    1717
    18 The GIET_VM boot-loader is defined in the [source:soft/giet_vm/giet_boot/boot.c boot.c] file.
     18The GIET_VM boot-loader is defined in the [source:soft/giet_vm/giet_boot/boot.c boot.c] and [source:soft/giet_vm/giet_boot/boot_entry.S boot_entry.S] files.
    1919The main steps are the following:
    2020
     21=== step 0 ===
     22The ''boot_entry.S'' file defines the entry point in the GIET_VM bootloader. This assembly code is executed by all processors.
     23It allocates a stack from the seg_boot_stack segment (defined by the SEG_BOOT_STACK_BASE and SEG_BOOT_STACK_SIZE parameters in the ''hard_config.h'' file), and initialises the CP0_SP (stack pointer) register.
     24 * The stack size for P(x,y,0) is 1.25 Kbytes.
     25 * The stack size for other processors is 0.25 Kbytes.
     26 * The SEG_BOOT_STACK_SIZE cannot be smaller than : 0x100 * (NN_PROCS_MAX-1) + 0x500) * X_SIZE * Y_SIZE
     27
    2128=== step 1 ===
    22 Processor P(0,0,0) initializes the FAT,  initializes the TTY0 lock, initialises the synchronisation barrier, and load the ''map.bin''file. Then processor P(0,0,0) use inter-processor-interrupts (WTI) to start the parallel execution, and activate processor P(x,y,0) in all clusters containing processors.
     29Processor P(0,0,0) initializes the FAT,  initializes the TTY0 lock, initialises the synchronisation barrier, and load the ''map.bin''file. Then processor P(0,0,0) use inter-processor-interrupts (WTI) to start the parallel execution, and activate processors P(x,y,0) in all clusters containing processors.
    2330
    2431=== step2 ===
    … …  
    2936
    3037=== step 3 ===
    31 In each cluster(x,y), processor P(x,y,0) makes the local page table initialisation (function '''boot_ptabs_init()''') as specified in the mapping.  There is one page table per user application (vspace) defined in the mapping, and it is replicated in all clusters containing processors. In each cluster, all pages tables are packed in one segment (seg_ptab) occupying one single big page (2 Mbytes). Global vsegs are mapped in all vspaces. Any vseg (but the peripherals)can be mapped on any physical segment. As the kernel read-only segments (seg_kcode and seg_kinit) are replicated in all clusters to avoid contention, the content of the page tables depends on the cluster-coordinates: for the kernel code, a given virtual address is mapped to different physical addresses, depending on the cluster coordinates.
     38In each cluster(x,y), processor P(x,y,0) makes the local page table initialisation (function '''boot_ptabs_init()''') as specified in the mapping.  There is one page table per user application (vspace) defined in the mapping, and it is replicated in all clusters containing processors. In each cluster, all pages tables are packed in one segment (seg_ptab) occupying one single big page (2 Mbytes). Global vsegs are mapped in all vspaces. Any vseg (but the peripherals) can be mapped on any physical segment. As the kernel read-only segments (seg_kcode and seg_kinit) are replicated in all clusters to avoid contention, the content of the page tables depends on the cluster-coordinates: for the kernel code, a given virtual address is mapped to different physical addresses, depending on the cluster coordinates.
    3239
    3340=== step 4 ===
    … …  
    4855== Phase 3 : Kernel Initialisation ==
    4956
    50 This code is executed by all processors, but sequencially. All processors enter the same [source:soft/giet_vm/giet_kernel/kernel_init.c kernel_init.c] code that makes the following actions:
     57This code is executed in parallel by all processors P(x,y,p). All processors enter the same [source:soft/giet_vm/giet_kernel/kernel_init.c kernel_init.c] code and execute the following steps, separated
     58by synchronization barriers when required.
    5159
    52  * '''step 0''' : processor[0][0][0] makes kernel_heap[x][y] array and kernel fat initialisation.
    53  * '''step 1''' : each processor get its scheduler virtual address from CP0_SCHED register and contributes to _schedulers[x][y][p] array initialisation.
    54  * '''step 2''' : each processor loops on all allocated tasks to build the _ptabs_vaddr[vspace] & _ptabs_ptprs[vspace] arrays from the tasks contexts.
    55  * '''step 3''' : each processor computes and set the XCU masks, as specified in the HWI, PTI, and WTI interrupt vectors.
    56  * '''step 4''' : each processor starts its TICK timer if it has at least one task allocated.
    57  * '''step 5''' : each processor updates the idle_task context (CTX_SP, CTX_RA, CTX_EPC).
    58  * '''step 6''' : when all processors reach the synchronisation barrier, each processor set registers SP, SR, PTPR, EPC, with the values corresponding to the first allocated task, and jump to user code.
     60=== step 0 ===
     61Processor P(0,0,0) makes kernel_heap[x][y] array, kernel fat initialization, TTY0 lock initialization, and barrier initialization.
     62
     63=== step 1 ===
     64Each processor P(x,y,p) get its scheduler virtual address from CP0_SCHED register and contributes to _schedulers[x][y][p] array initialization.
     65
     66=== step 2 ===
     67Each processor P(x,y,p) loops on all allocated tasks to build the _ptabs_vaddr[vspace] & _ptabs_ptprs[vspace] arrays from the tasks contexts.
     68
     69=== step 3 ===
     70Each processor P(x,y,p) computes and set the XCU masks, as specified in the HWI, PTI, and WTI interrupt vectors.
     71
     72=== step 4 ===
     73Each processor P(x,y,p) starts its TICK timer if it has at least one task allocated.
     74
     75=== step 5 ===
     76Each processor updates its private idle_task context (CTX_SP, CTX_RA, CTX_EPC).
     77
     78=== step 6 ===
     79Each processor P(x,y,p) set registers SP, SR, PTPR, EPC, with the values corresponding to the first allocated task, and jump to user code.
    5980
    6081